X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FAllocationOrder.cpp;h=3fa1f8ff206cdf0373efc6867e0e5ccbb724a9f8;hb=fe532525cc4912ec0d1b4e91fa0396122dd087b3;hp=a76791025d9a013f6f42017460779239b8e3553b;hpb=a1514e24cc24b050f53a12650e047799358833a1;p=oota-llvm.git diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp index a76791025d9..3fa1f8ff206 100644 --- a/lib/CodeGen/AllocationOrder.cpp +++ b/lib/CodeGen/AllocationOrder.cpp @@ -22,7 +22,6 @@ #include "llvm/CodeGen/VirtRegMap.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -35,6 +34,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM); + rewind(); DEBUG({ if (!Hints.empty()) { @@ -44,22 +44,9 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, dbgs() << '\n'; } }); -} - -bool AllocationOrder::isHint(unsigned PhysReg) const { - return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end(); -} - -unsigned AllocationOrder::next() { - if (Pos < Hints.size()) - return Hints[Pos++]; - ArrayRef::iterator I = Order.begin() + (Pos - Hints.size()); - ArrayRef::iterator E = Order.end(); - while (I != E) { - unsigned Reg = *I++; - ++Pos; - if (!isHint(Reg)) - return Reg; - } - return 0; +#ifndef NDEBUG + for (unsigned I = 0, E = Hints.size(); I != E; ++I) + assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() && + "Target hint is outside allocation order."); +#endif }