X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FAllocationOrder.h;h=aed461a7ed028d2e62c4a5458d4fcaf5f2c48901;hb=1db3d0820f8057dd03ade1585bfa5f2bf53cfe33;hp=9bcbc732ed3c5019803c835ce5197fefeeb8074d;hpb=a1514e24cc24b050f53a12650e047799358833a1;p=oota-llvm.git

diff --git a/lib/CodeGen/AllocationOrder.h b/lib/CodeGen/AllocationOrder.h
index 9bcbc732ed3..aed461a7ed0 100644
--- a/lib/CodeGen/AllocationOrder.h
+++ b/lib/CodeGen/AllocationOrder.h
@@ -28,7 +28,7 @@ class VirtRegMap;
 class AllocationOrder {
   SmallVector<MCPhysReg, 16> Hints;
   ArrayRef<MCPhysReg> Order;
-  unsigned Pos;
+  int Pos;
 
 public:
   /// Create a new AllocationOrder for VirtReg.
@@ -39,19 +39,45 @@ public:
                   const VirtRegMap &VRM,
                   const RegisterClassInfo &RegClassInfo);
 
+  /// Get the allocation order without reordered hints.
+  ArrayRef<MCPhysReg> getOrder() const { return Order; }
+
   /// Return the next physical register in the allocation order, or 0.
   /// It is safe to call next() again after it returned 0, it will keep
   /// returning 0 until rewind() is called.
-  unsigned next();
+  unsigned next() {
+    if (Pos < 0)
+      return Hints.end()[Pos++];
+    while (Pos < int(Order.size())) {
+      unsigned Reg = Order[Pos++];
+      if (!isHint(Reg))
+        return Reg;
+    }
+    return 0;
+  }
+
+  /// As next(), but allow duplicates to be returned, and stop before the
+  /// Limit'th register in the RegisterClassInfo allocation order.
+  ///
+  /// This can produce more than Limit registers if there are hints.
+  unsigned nextWithDups(unsigned Limit) {
+    if (Pos < 0)
+      return Hints.end()[Pos++];
+    if (Pos < int(Limit))
+      return Order[Pos++];
+    return 0;
+  }
 
   /// Start over from the beginning.
-  void rewind() { Pos = 0; }
+  void rewind() { Pos = -int(Hints.size()); }
 
   /// Return true if the last register returned from next() was a preferred register.
-  bool isHint() const { return Pos <= Hints.size(); }
+  bool isHint() const { return Pos <= 0; }
 
   /// Return true if PhysReg is a preferred register.
-  bool isHint(unsigned PhysReg) const;
+  bool isHint(unsigned PhysReg) const {
+    return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
+  }
 };
 
 } // end namespace llvm