X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FCriticalAntiDepBreaker.h;h=ceef74d1a4400f1e694f719c867733653cae3ade;hb=d6b76f9466f267ac5ec8ac0f3afa83da0d810490;hp=cc42dd2b8e3295f582f599e15b5903d8149f18ff;hpb=66db3a0f10e96ae190c8a46a1a8d5242928d068c;p=oota-llvm.git diff --git a/lib/CodeGen/CriticalAntiDepBreaker.h b/lib/CodeGen/CriticalAntiDepBreaker.h index cc42dd2b8e3..ceef74d1a44 100644 --- a/lib/CodeGen/CriticalAntiDepBreaker.h +++ b/lib/CodeGen/CriticalAntiDepBreaker.h @@ -13,85 +13,95 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CODEGEN_CRITICALANTIDEPBREAKER_H -#define LLVM_CODEGEN_CRITICALANTIDEPBREAKER_H +#ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H +#define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H #include "AntiDepBreaker.h" +#include "llvm/ADT/BitVector.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/CodeGen/ScheduleDAG.h" -#include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/ADT/BitVector.h" -#include "llvm/ADT/SmallSet.h" #include namespace llvm { +class RegisterClassInfo; +class TargetInstrInfo; +class TargetRegisterInfo; + class CriticalAntiDepBreaker : public AntiDepBreaker { MachineFunction& MF; MachineRegisterInfo &MRI; + const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; + const RegisterClassInfo &RegClassInfo; - /// AllocatableSet - The set of allocatable registers. + /// The set of allocatable registers. /// We'll be ignoring anti-dependencies on non-allocatable registers, /// because they may not be safe to break. const BitVector AllocatableSet; - /// Classes - For live regs that are only used in one register class in a + /// For live regs that are only used in one register class in a /// live range, the register class. If the register is not live, the /// corresponding value is null. If the register is live but used in /// multiple register classes, the corresponding value is -1 casted to a /// pointer. - const TargetRegisterClass * - Classes[TargetRegisterInfo::FirstVirtualRegister]; + std::vector Classes; - /// RegRegs - Map registers to all their references within a live range. + /// Map registers to all their references within a live range. std::multimap RegRefs; + typedef std::multimap::const_iterator + RegRefIter; - /// KillIndices - The index of the most recent kill (proceding bottom-up), + /// The index of the most recent kill (proceeding bottom-up), /// or ~0u if the register is not live. - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector KillIndices; - /// DefIndices - The index of the most recent complete def (proceding bottom - /// up), or ~0u if the register is live. - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; + /// The index of the most recent complete def (proceeding + /// bottom up), or ~0u if the register is live. + std::vector DefIndices; - /// KeepRegs - A set of registers which are live and cannot be changed to + /// A set of registers which are live and cannot be changed to /// break anti-dependencies. - SmallSet KeepRegs; + BitVector KeepRegs; public: - CriticalAntiDepBreaker(MachineFunction& MFi); + CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo&); ~CriticalAntiDepBreaker(); - /// Start - Initialize anti-dep breaking for a new basic block. - void StartBlock(MachineBasicBlock *BB); + /// Initialize anti-dep breaking for a new basic block. + void StartBlock(MachineBasicBlock *BB) override; - /// BreakAntiDependencies - Identifiy anti-dependencies along the critical - /// path + /// Identifiy anti-dependencies along the critical path /// of the ScheduleDAG and break them by renaming registers. - /// unsigned BreakAntiDependencies(const std::vector& SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, - unsigned InsertPosIndex); + unsigned InsertPosIndex, + DbgValueVector &DbgValues) override; - /// Observe - Update liveness information to account for the current + /// Update liveness information to account for the current /// instruction, which will not be scheduled. - /// - void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex); + void Observe(MachineInstr *MI, unsigned Count, + unsigned InsertPosIndex) override; - /// Finish - Finish anti-dep breaking for a basic block. - void FinishBlock(); + /// Finish anti-dep breaking for a basic block. + void FinishBlock() override; private: void PrescanInstruction(MachineInstr *MI); void ScanInstruction(MachineInstr *MI, unsigned Count); - unsigned findSuitableFreeRegister(MachineInstr *MI, + bool isNewRegClobberedByRefs(RegRefIter RegRefBegin, + RegRefIter RegRefEnd, + unsigned NewReg); + unsigned findSuitableFreeRegister(RegRefIter RegRefBegin, + RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, - const TargetRegisterClass *); + const TargetRegisterClass *RC, + SmallVectorImpl &Forbid); }; }