X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLLVMTargetMachine.cpp;h=97fe35c2f4b09c72ab3d2821a905b7e65b43c2ca;hb=126d90770bdb17e6925b2fe26de99aa079b7b9b3;hp=04c59107f8ce628d5cbcadab0aff3407bffa761a;hpb=73ee9c3fb1f15cbfb2f91a4f645834c94a76a949;p=oota-llvm.git

diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index 04c59107f8c..97fe35c2f4b 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -19,6 +19,7 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/Collector.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetAsmInfo.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
@@ -37,12 +38,9 @@ static cl::opt<bool>
 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
               cl::desc("Perform sinking on machine code"));
 static cl::opt<bool>
-AlignLoops("align-loops", cl::init(true), cl::Hidden,
-              cl::desc("Align loop headers"));
-static cl::opt<bool>
-PerformLICM("machine-licm",
-            cl::init(false), cl::Hidden,
-            cl::desc("Perform loop-invariant code motion on machine code"));
+EnableLICM("machine-licm",
+           cl::init(false), cl::Hidden,
+           cl::desc("Perform loop-invariant code motion on machine code"));
 
 // When this works it will be on by default.
 static cl::opt<bool>
@@ -61,12 +59,12 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (!Fast) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
-      PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
+      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
   }
   
   PM.add(createGCLoweringPass());
 
-  if (!ExceptionHandling)
+  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
     PM.add(createLowerInvokePass(getTargetLowering()));
 
   // Make sure that no unreachable blocks are instruction selected.
@@ -76,7 +74,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   if (PrintISelInput)
-    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
+    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
                                  &cerr));
   
   // Ask the target for an isel.
@@ -87,30 +85,41 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (PerformLICM)
+  if (EnableLICM)
     PM.add(createMachineLICMPass());
   
   if (EnableSinking)
     PM.add(createMachineSinkingPass());
 
+  // Run pre-ra passes.
+  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
   // Perform register allocation to convert to a concrete x86 representation
   PM.add(createRegisterAllocator());
   
-  if (PrintMachineCode)
+  // Perform stack slot coloring.
+  if (!Fast)
+    PM.add(createStackSlotColoringPass());
+
+  if (PrintMachineCode)  // Print the register-allocated code
     PM.add(createMachineFunctionPrinterPass(cerr));
-    
-  PM.add(createLowerSubregsPass());
   
-  if (PrintMachineCode)  // Print the subreg lowered code
-    PM.add(createMachineFunctionPrinterPass(cerr));
-
   // Run post-ra passes.
   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
+  PM.add(createLowerSubregsPass());
+  
+  if (PrintMachineCode)  // Print the subreg lowered code
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
   PM.add(createPrologEpilogCodeInserter());
   
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+  
   // Second pass scheduler.
   if (!Fast && !DisablePostRAScheduler)
     PM.add(createPostRAScheduler());
@@ -135,7 +144,7 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (AlignLoops && !OptimizeForSize)
+  if (!Fast && !OptimizeForSize)
     PM.add(createLoopAlignerPass());
 
   switch (FileType) {
@@ -187,12 +196,12 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
   if (!Fast) {
     PM.add(createLoopStrengthReducePass(getTargetLowering()));
     if (PrintLSR)
-      PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
+      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
   }
   
   PM.add(createGCLoweringPass());
   
-  if (!ExceptionHandling)
+  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
     PM.add(createLowerInvokePass(getTargetLowering()));
   
   // Make sure that no unreachable blocks are instruction selected.
@@ -202,7 +211,7 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
     PM.add(createCodeGenPreparePass(getTargetLowering()));
 
   if (PrintISelInput)
-    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
+    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
                                  &cerr));
 
   // Ask the target for an isel.
@@ -213,31 +222,42 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  if (PerformLICM)
+  if (EnableLICM)
     PM.add(createMachineLICMPass());
   
   if (EnableSinking)
     PM.add(createMachineSinkingPass());
 
-  // Perform register allocation to convert to a concrete x86 representation
+  // Run pre-ra passes.
+  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
+  // Perform register allocation.
   PM.add(createRegisterAllocator());
-  
+
+  // Perform stack slot coloring.
+  if (!Fast)
+    PM.add(createStackSlotColoringPass());
+
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
     
+  // Run post-ra passes.
+  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(cerr));
+
+  if (PrintMachineCode)  // Print the register-allocated code
+    PM.add(createMachineFunctionPrinterPass(cerr));
+  
   PM.add(createLowerSubregsPass());
   
   if (PrintMachineCode)  // Print the subreg lowered code
     PM.add(createMachineFunctionPrinterPass(cerr));
 
-  // Run post-ra passes.
-  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(cerr));
-
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
   PM.add(createPrologEpilogCodeInserter());
   
-  if (PrintMachineCode)  // Print the register-allocated code
+  if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
   
   // Second pass scheduler.
@@ -249,6 +269,7 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 
   PM.add(createGCMachineCodeAnalysisPass());
+
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));