X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLLVMTargetMachine.cpp;h=97fe35c2f4b09c72ab3d2821a905b7e65b43c2ca;hb=126d90770bdb17e6925b2fe26de99aa079b7b9b3;hp=351554bb193e9c6d57006e17f747883d3c03aa26;hpb=459525df1e003597077197b5f802bd5d9cd7d94c;p=oota-llvm.git diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 351554bb193..97fe35c2f4b 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -19,6 +19,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Collector.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -37,9 +38,9 @@ static cl::opt EnableSinking("enable-sinking", cl::init(false), cl::Hidden, cl::desc("Perform sinking on machine code")); static cl::opt -PerformLICM("machine-licm", - cl::init(false), cl::Hidden, - cl::desc("Perform loop-invariant code motion on machine code")); +EnableLICM("machine-licm", + cl::init(false), cl::Hidden, + cl::desc("Perform loop-invariant code motion on machine code")); // When this works it will be on by default. static cl::opt @@ -48,7 +49,7 @@ DisablePostRAScheduler("disable-post-RA-scheduler", cl::init(true)); FileModel::Model -LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, +LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, std::ostream &Out, CodeGenFileType FileType, bool Fast) { @@ -58,12 +59,12 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, if (!Fast) { PM.add(createLoopStrengthReducePass(getTargetLowering())); if (PrintLSR) - PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr)); + PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr)); } PM.add(createGCLoweringPass()); - if (!ExceptionHandling) + if (!getTargetAsmInfo()->doesSupportExceptionHandling()) PM.add(createLowerInvokePass(getTargetLowering())); // Make sure that no unreachable blocks are instruction selected. @@ -73,7 +74,7 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, PM.add(createCodeGenPreparePass(getTargetLowering())); if (PrintISelInput) - PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n", + PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n", &cerr)); // Ask the target for an isel. @@ -84,30 +85,41 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (PerformLICM) + if (EnableLICM) PM.add(createMachineLICMPass()); if (EnableSinking) PM.add(createMachineSinkingPass()); + // Run pre-ra passes. + if (addPreRegAlloc(PM, Fast) && PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + // Perform register allocation to convert to a concrete x86 representation PM.add(createRegisterAllocator()); - if (PrintMachineCode) + // Perform stack slot coloring. + if (!Fast) + PM.add(createStackSlotColoringPass()); + + if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(cerr)); - - PM.add(createLowerSubregsPass()); - if (PrintMachineCode) // Print the subreg lowered code - PM.add(createMachineFunctionPrinterPass(cerr)); - // Run post-ra passes. if (addPostRegAlloc(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + PM.add(createLowerSubregsPass()); + + if (PrintMachineCode) // Print the subreg lowered code + PM.add(createMachineFunctionPrinterPass(cerr)); + // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); + if (PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + // Second pass scheduler. if (!Fast && !DisablePostRAScheduler) PM.add(createPostRAScheduler()); @@ -132,6 +144,9 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + if (!Fast && !OptimizeForSize) + PM.add(createLoopAlignerPass()); + switch (FileType) { default: break; @@ -152,7 +167,7 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, /// addPassesToEmitFileFinish - If the passes to emit the specified file had to /// be split up (e.g., to add an object writer pass), this method can be used to /// finish up adding passes to emit the file, if necessary. -bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM, +bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, MachineCodeEmitter *MCE, bool Fast) { if (MCE) @@ -172,7 +187,7 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM, /// of functions. This method should returns true if machine code emission is /// not supported. /// -bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, +bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, MachineCodeEmitter &MCE, bool Fast) { // Standard LLVM-Level Passes. @@ -181,13 +196,13 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, if (!Fast) { PM.add(createLoopStrengthReducePass(getTargetLowering())); if (PrintLSR) - PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr)); + PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr)); } PM.add(createGCLoweringPass()); - // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass(getTargetLowering())); + if (!getTargetAsmInfo()->doesSupportExceptionHandling()) + PM.add(createLowerInvokePass(getTargetLowering())); // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); @@ -196,7 +211,7 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, PM.add(createCodeGenPreparePass(getTargetLowering())); if (PrintISelInput) - PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n", + PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n", &cerr)); // Ask the target for an isel. @@ -207,31 +222,42 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (PerformLICM) + if (EnableLICM) PM.add(createMachineLICMPass()); if (EnableSinking) PM.add(createMachineSinkingPass()); - // Perform register allocation to convert to a concrete x86 representation + // Run pre-ra passes. + if (addPreRegAlloc(PM, Fast) && PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + + // Perform register allocation. PM.add(createRegisterAllocator()); - + + // Perform stack slot coloring. + if (!Fast) + PM.add(createStackSlotColoringPass()); + if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + // Run post-ra passes. + if (addPostRegAlloc(PM, Fast) && PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + + if (PrintMachineCode) // Print the register-allocated code + PM.add(createMachineFunctionPrinterPass(cerr)); + PM.add(createLowerSubregsPass()); if (PrintMachineCode) // Print the subreg lowered code PM.add(createMachineFunctionPrinterPass(cerr)); - // Run post-ra passes. - if (addPostRegAlloc(PM, Fast) && PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(cerr)); - // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); - if (PrintMachineCode) // Print the register-allocated code + if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); // Second pass scheduler. @@ -243,6 +269,7 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); PM.add(createGCMachineCodeAnalysisPass()); + if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr));