X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLiveIntervalAnalysis.cpp;h=d6931df896dc4c05d63c4514114ee9e878175f13;hb=c69485e34d57e17fe2c3acab64e519d6a6945197;hp=ff247ad4597f08d0107b87ca2183d656163f7c8f;hpb=95dad830bbf975cb4cea4e1ac685781a18676a7a;p=oota-llvm.git diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index ff247ad4597..d6931df896d 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -36,6 +36,7 @@ #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include +#include #include using namespace llvm; @@ -54,7 +55,6 @@ static cl::opt EnableFastSpilling("fast-spill", cl::init(false), cl::Hidden); STATISTIC(numIntervals, "Number of original intervals"); -STATISTIC(numIntervalsAfter, "Number of intervals after coalescing"); STATISTIC(numFolds , "Number of loads/stores folded into instructions"); STATISTIC(numSplits , "Number of intervals split"); @@ -126,13 +126,18 @@ void LiveIntervals::computeNumbering() { I != E; ++I) { bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second; assert(inserted && "multiple MachineInstr -> index mappings"); + inserted = true; i2miMap_.push_back(I); MIIndex += InstrSlots::NUM; FunctionSize++; - // Insert an empty slot after every instruction. - MIIndex += InstrSlots::NUM; - i2miMap_.push_back(0); + // Insert max(1, numdefs) empty slots after every instruction. + unsigned Slots = I->getDesc().getNumDefs(); + if (Slots == 0) + Slots = 1; + MIIndex += InstrSlots::NUM * Slots; + while (Slots--) + i2miMap_.push_back(0); } // Set the MBB2IdxMap entry for this MBB. @@ -194,7 +199,7 @@ void LiveIntervals::computeNumbering() { // Remap the VNInfo def index, which works the same as the // start indices above. VN's with special sentinel defs // don't need to be remapped. - if (vni->def != ~0U && vni->def != ~1U) { + if (vni->isDefAccurate() && !vni->isUnused()) { unsigned index = vni->def / InstrSlots::NUM; unsigned offset = vni->def % InstrSlots::NUM; if (offset == InstrSlots::LOAD) { @@ -239,6 +244,49 @@ void LiveIntervals::computeNumbering() { } } +void LiveIntervals::scaleNumbering(int factor) { + // Need to + // * scale MBB begin and end points + // * scale all ranges. + // * Update VNI structures. + // * Scale instruction numberings + + // Scale the MBB indices. + Idx2MBBMap.clear(); + for (MachineFunction::iterator MBB = mf_->begin(), MBBE = mf_->end(); + MBB != MBBE; ++MBB) { + std::pair &mbbIndices = MBB2IdxMap[MBB->getNumber()]; + mbbIndices.first = InstrSlots::scale(mbbIndices.first, factor); + mbbIndices.second = InstrSlots::scale(mbbIndices.second, factor); + Idx2MBBMap.push_back(std::make_pair(mbbIndices.first, MBB)); + } + std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare()); + + // Scale the intervals. + for (iterator LI = begin(), LE = end(); LI != LE; ++LI) { + LI->second->scaleNumbering(factor); + } + + // Scale MachineInstrs. + Mi2IndexMap oldmi2iMap = mi2iMap_; + unsigned highestSlot = 0; + for (Mi2IndexMap::iterator MI = oldmi2iMap.begin(), ME = oldmi2iMap.end(); + MI != ME; ++MI) { + unsigned newSlot = InstrSlots::scale(MI->second, factor); + mi2iMap_[MI->first] = newSlot; + highestSlot = std::max(highestSlot, newSlot); + } + + i2miMap_.clear(); + i2miMap_.resize(highestSlot + 1); + for (Mi2IndexMap::iterator MI = mi2iMap_.begin(), ME = mi2iMap_.end(); + MI != ME; ++MI) { + i2miMap_[MI->second] = MI->first; + } + +} + + /// runOnMachineFunction - Register allocate the whole function /// bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { @@ -256,13 +304,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { numIntervals += getNumIntervals(); - DOUT << "********** INTERVALS **********\n"; - for (iterator I = begin(), E = end(); I != E; ++I) { - I->second->print(DOUT, tri_); - DOUT << "\n"; - } - - numIntervalsAfter += getNumIntervals(); DEBUG(dump()); return true; } @@ -301,8 +342,8 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li, if (index == end) break; MachineInstr *MI = getInstructionFromIndex(index); - unsigned SrcReg, DstReg; - if (tii_->isMoveInstr(*MI, SrcReg, DstReg)) + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) if (SrcReg == li.reg || DstReg == li.reg) continue; for (unsigned i = 0; i != MI->getNumOperands(); ++i) { @@ -326,6 +367,47 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li, return false; } +/// conflictsWithPhysRegRef - Similar to conflictsWithPhysRegRef except +/// it can check use as well. +bool LiveIntervals::conflictsWithPhysRegRef(LiveInterval &li, + unsigned Reg, bool CheckUse, + SmallPtrSet &JoinedCopies) { + for (LiveInterval::Ranges::const_iterator + I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) { + for (unsigned index = getBaseIndex(I->start), + end = getBaseIndex(I->end-1) + InstrSlots::NUM; index != end; + index += InstrSlots::NUM) { + // Skip deleted instructions. + MachineInstr *MI = 0; + while (index != end) { + MI = getInstructionFromIndex(index); + if (MI) + break; + index += InstrSlots::NUM; + } + if (index == end) break; + + if (JoinedCopies.count(MI)) + continue; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (!MO.isReg()) + continue; + if (MO.isUse() && !CheckUse) + continue; + unsigned PhysReg = MO.getReg(); + if (PhysReg == 0 || TargetRegisterInfo::isVirtualRegister(PhysReg)) + continue; + if (tri_->isSubRegister(Reg, PhysReg)) + return true; + } + } + } + + return false; +} + + void LiveIntervals::printRegName(unsigned reg) const { if (TargetRegisterInfo::isPhysicalRegister(reg)) cerr << tri_->getName(reg); @@ -358,12 +440,14 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, defIndex = getUseIndex(MIIdx); VNInfo *ValNo; MachineInstr *CopyMI = NULL; - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - tii_->isMoveInstr(*mi, SrcReg, DstReg)) + mi->getOpcode() == TargetInstrInfo::SUBREG_TO_REG || + tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = mi; - ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator); + // Earlyclobbers move back one. + ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator); assert(ValNo->id == 0 && "First value in interval is not 0?"); @@ -382,7 +466,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // If the kill happens after the definition, we have an intra-block // live range. if (killIdx > defIndex) { - assert(vi.AliveBlocks.none() && + assert(vi.AliveBlocks.empty() && "Shouldn't be alive across any blocks!"); LiveRange LR(defIndex, killIdx, ValNo); interval.addRange(LR); @@ -403,14 +487,13 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // Iterate over all of the blocks that the variable is completely // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the // live interval. - for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { - if (vi.AliveBlocks[i]) { - LiveRange LR(getMBBStartIdx(i), - getMBBEndIdx(i)+1, // MBB ends at -1. - ValNo); - interval.addRange(LR); - DOUT << " +" << LR; - } + for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(), + E = vi.AliveBlocks.end(); I != E; ++I) { + LiveRange LR(getMBBStartIdx(*I), + getMBBEndIdx(*I)+1, // MBB ends at -1. + ValNo); + interval.addRange(LR); + DOUT << " +" << LR; } // Finally, this virtual register is live from the start of any killing @@ -430,7 +513,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // must be due to phi elimination or two addr elimination. If this is // the result of two address elimination, then the vreg is one of the // def-and-use register operand. - if (mi->isRegReDefinedByTwoAddr(interval.reg, MOIdx)) { + if (mi->isRegTiedToUseOperand(MOIdx)) { // If this is a two-address definition, then we have already processed // the live range. The only problem is that we didn't realize there // are actually two values in the live interval. Because of this we @@ -439,7 +522,6 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, assert(interval.containsOneValue()); unsigned DefIndex = getDefIndex(interval.getValNumInfo(0)->def); unsigned RedefIndex = getDefIndex(MIIdx); - // Earlyclobbers move back one. if (MO.isEarlyClobber()) RedefIndex = getUseIndex(MIIdx); @@ -457,11 +539,15 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // The new value number (#1) is defined by the instruction we claimed // defined value #0. VNInfo *ValNo = interval.getNextValue(OldValNo->def, OldValNo->copy, + false, // update at * VNInfoAllocator); - + ValNo->setFlags(OldValNo->getFlags()); // * <- updating here + // Value#0 is now defined by the 2-addr instruction. OldValNo->def = RedefIndex; OldValNo->copy = 0; + if (MO.isEarlyClobber()) + OldValNo->setHasRedefByEC(true); // Add the new live interval which replaces the range for the input copy. LiveRange LR(DefIndex, RedefIndex, ValNo); @@ -493,12 +579,14 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, DOUT << " Removing [" << Start << "," << End << "] from: "; interval.print(DOUT, tri_); DOUT << "\n"; interval.removeRange(Start, End); - VNI->hasPHIKill = true; + VNI->setHasPHIKill(true); DOUT << " RESULT: "; interval.print(DOUT, tri_); // Replace the interval with one of a NEW value number. Note that this // value number isn't actually defined by an instruction, weird huh? :) - LiveRange LR(Start, End, interval.getNextValue(~0, 0, VNInfoAllocator)); + LiveRange LR(Start, End, + interval.getNextValue(mbb->getNumber(), 0, false, VNInfoAllocator)); + LR.valno->setIsPHIDef(true); DOUT << " replace range with " << LR; interval.addRange(LR); interval.addKill(LR.valno, End); @@ -509,24 +597,24 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // live until the end of the block. We've already taken care of the // rest of the live range. unsigned defIndex = getDefIndex(MIIdx); - // Earlyclobbers move back one. if (MO.isEarlyClobber()) defIndex = getUseIndex(MIIdx); VNInfo *ValNo; MachineInstr *CopyMI = NULL; - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - tii_->isMoveInstr(*mi, SrcReg, DstReg)) + mi->getOpcode() == TargetInstrInfo::SUBREG_TO_REG || + tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = mi; - ValNo = interval.getNextValue(defIndex, CopyMI, VNInfoAllocator); + ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator); unsigned killIndex = getMBBEndIdx(mbb) + 1; LiveRange LR(defIndex, killIndex, ValNo); interval.addRange(LR); interval.addKill(ValNo, killIndex); - ValNo->hasPHIKill = true; + ValNo->setHasPHIKill(true); DOUT << " +" << LR; } } @@ -572,14 +660,24 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, DOUT << " killed"; end = getUseIndex(baseIndex) + 1; goto exit; - } else if (mi->modifiesRegister(interval.reg, tri_)) { - // Another instruction redefines the register before it is ever read. - // Then the register is essentially dead at the instruction that defines - // it. Hence its interval is: - // [defSlot(def), defSlot(def)+1) - DOUT << " dead"; - end = start + 1; - goto exit; + } else { + int DefIdx = mi->findRegisterDefOperandIdx(interval.reg, false, tri_); + if (DefIdx != -1) { + if (mi->isRegTiedToUseOperand(DefIdx)) { + // Two-address instruction. + end = getDefIndex(baseIndex); + if (mi->getOperand(DefIdx).isEarlyClobber()) + end = getUseIndex(baseIndex); + } else { + // Another instruction redefines the register before it is ever read. + // Then the register is essentially dead at the instruction that defines + // it. Hence its interval is: + // [defSlot(def), defSlot(def)+1) + DOUT << " dead"; + end = start + 1; + } + goto exit; + } } baseIndex += InstrSlots::NUM; @@ -587,8 +685,8 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, // The only case we should have a dead physreg here without a killing or // instruction where we know it's dead is if it is live-in to the function - // and never used. - assert(!CopyMI && "physreg was not killed in defining block!"); + // and never used. Another possible case is the implicit use of the + // physical register has been deleted by two-address pass. end = start + 1; exit: @@ -596,8 +694,11 @@ exit: // Already exists? Extend old live interval. LiveInterval::iterator OldLR = interval.FindLiveRangeContaining(start); - VNInfo *ValNo = (OldLR != interval.end()) - ? OldLR->valno : interval.getNextValue(start, CopyMI, VNInfoAllocator); + bool Extend = OldLR != interval.end(); + VNInfo *ValNo = Extend + ? OldLR->valno : interval.getNextValue(start, CopyMI, true, VNInfoAllocator); + if (MO.isEarlyClobber() && Extend) + ValNo->setHasRedefByEC(true); LiveRange LR(start, end, ValNo); interval.addRange(LR); interval.addKill(LR.valno, end); @@ -614,19 +715,20 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, getOrCreateInterval(MO.getReg())); else if (allocatableRegs_[MO.getReg()]) { MachineInstr *CopyMI = NULL; - unsigned SrcReg, DstReg; + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - tii_->isMoveInstr(*MI, SrcReg, DstReg)) + MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG || + tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = MI; - handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, + handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, getOrCreateInterval(MO.getReg()), CopyMI); // Def of a register also defines its sub-registers. for (const unsigned* AS = tri_->getSubRegisters(MO.getReg()); *AS; ++AS) // If MI also modifies the sub-register explicitly, avoid processing it // more than once. Do not pass in TRI here so it checks for exact match. if (!MI->modifiesRegister(*AS)) - handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, + handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, getOrCreateInterval(*AS), 0); } } @@ -645,12 +747,14 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, getInstructionFromIndex(baseIndex) == 0) baseIndex += InstrSlots::NUM; unsigned end = baseIndex; + bool SeenDefUse = false; while (mi != MBB->end()) { if (mi->killsRegister(interval.reg, tri_)) { DOUT << " killed"; end = getUseIndex(baseIndex) + 1; - goto exit; + SeenDefUse = true; + break; } else if (mi->modifiesRegister(interval.reg, tri_)) { // Another instruction redefines the register before it is ever read. // Then the register is essentially dead at the instruction that defines @@ -658,19 +762,21 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, // [defSlot(def), defSlot(def)+1) DOUT << " dead"; end = getDefIndex(start) + 1; - goto exit; + SeenDefUse = true; + break; } baseIndex += InstrSlots::NUM; - while (baseIndex / InstrSlots::NUM < i2miMap_.size() && - getInstructionFromIndex(baseIndex) == 0) - baseIndex += InstrSlots::NUM; ++mi; + if (mi != MBB->end()) { + while (baseIndex / InstrSlots::NUM < i2miMap_.size() && + getInstructionFromIndex(baseIndex) == 0) + baseIndex += InstrSlots::NUM; + } } -exit: // Live-in register might not be used at all. - if (end == MIIdx) { + if (!SeenDefUse) { if (isAlias) { DOUT << " dead"; end = getDefIndex(MIIdx) + 1; @@ -680,7 +786,11 @@ exit: } } - LiveRange LR(start, end, interval.getNextValue(~0U, 0, VNInfoAllocator)); + VNInfo *vni = + interval.getNextValue(MBB->getNumber(), 0, false, VNInfoAllocator); + vni->setIsPHIDef(true); + LiveRange LR(start, end, vni); + interval.addRange(LR); interval.addKill(LR.valno, end); DOUT << " +" << LR << '\n'; @@ -732,8 +842,12 @@ void LiveIntervals::computeIntervals() { handleRegisterDef(MBB, MI, MIIndex, MO, i); } } - - MIIndex += InstrSlots::NUM; + + // Skip over the empty slots after each instruction. + unsigned Slots = MI->getDesc().getNumDefs(); + if (Slots == 0) + Slots = 1; + MIIndex += InstrSlots::NUM * Slots; // Skip over empty indices. while (MIIndex / InstrSlots::NUM < i2miMap_.size() && @@ -743,14 +857,14 @@ void LiveIntervals::computeIntervals() { } } -bool LiveIntervals::findLiveInMBBs(const LiveRange &LR, +bool LiveIntervals::findLiveInMBBs(unsigned Start, unsigned End, SmallVectorImpl &MBBs) const { std::vector::const_iterator I = - std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), LR.start); + std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start); bool ResVal = false; while (I != Idx2MBBMap.end()) { - if (LR.end <= I->first) + if (I->first >= End) break; MBBs.push_back(I->second); ResVal = true; @@ -759,24 +873,58 @@ bool LiveIntervals::findLiveInMBBs(const LiveRange &LR, return ResVal; } +bool LiveIntervals::findReachableMBBs(unsigned Start, unsigned End, + SmallVectorImpl &MBBs) const { + std::vector::const_iterator I = + std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), Start); + + bool ResVal = false; + while (I != Idx2MBBMap.end()) { + if (I->first > End) + break; + MachineBasicBlock *MBB = I->second; + if (getMBBEndIdx(MBB) > End) + break; + for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), + SE = MBB->succ_end(); SI != SE; ++SI) + MBBs.push_back(*SI); + ResVal = true; + ++I; + } + return ResVal; +} + LiveInterval* LiveIntervals::createInterval(unsigned reg) { - float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? - HUGE_VALF : 0.0F; + float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F; return new LiveInterval(reg, Weight); } +/// dupInterval - Duplicate a live interval. The caller is responsible for +/// managing the allocated memory. +LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) { + LiveInterval *NewLI = createInterval(li->reg); + NewLI->Copy(*li, mri_, getVNInfoAllocator()); + return NewLI; +} + /// getVNInfoSourceReg - Helper function that parses the specified VNInfo /// copy field and returns the source register that defines it. unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const { if (!VNI->copy) return 0; - if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) - return VNI->copy->getOperand(1).getReg(); - if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG) + if (VNI->copy->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { + // If it's extracting out of a physical register, return the sub-register. + unsigned Reg = VNI->copy->getOperand(1).getReg(); + if (TargetRegisterInfo::isPhysicalRegister(Reg)) + Reg = tri_->getSubReg(Reg, VNI->copy->getOperand(2).getImm()); + return Reg; + } else if (VNI->copy->getOpcode() == TargetInstrInfo::INSERT_SUBREG || + VNI->copy->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) return VNI->copy->getOperand(2).getReg(); - unsigned SrcReg, DstReg; - if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg)) + + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (tii_->isMoveInstr(*VNI->copy, SrcReg, DstReg, SrcSubReg, DstSubReg)) return SrcReg; assert(0 && "Unrecognized copy instruction!"); return 0; @@ -897,7 +1045,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li, MachineRegisterInfo::def_iterator I = mri_->def_begin(Reg), E = mri_->def_end(); - // For the def, it should be the only def. + // For the def, it should be the only def of that register. if (MO.isDef() && (next(I) != E || IsLiveIn)) return false; @@ -910,7 +1058,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li, else if (Reg != ImpUse) return false; } - // For uses, there should be only one associate def. + // For the use, there should be only one associated def. if (I != E && (next(I) != E || IsLiveIn)) return false; } @@ -940,6 +1088,15 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li, return true; } +/// isReMaterializable - Returns true if the definition MI of the specified +/// val# of the specified interval is re-materializable. +bool LiveIntervals::isReMaterializable(const LiveInterval &li, + const VNInfo *ValNo, MachineInstr *MI) { + SmallVector Dummy1; + bool Dummy2; + return isReMaterializable(li, ValNo, MI, Dummy1, Dummy2); +} + /// isReMaterializable - Returns true if every definition of MI of every /// val# of the specified interval is re-materializable. bool LiveIntervals::isReMaterializable(const LiveInterval &li, @@ -949,13 +1106,12 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li, for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end(); i != e; ++i) { const VNInfo *VNI = *i; - unsigned DefIdx = VNI->def; - if (DefIdx == ~1U) + if (VNI->isUnused()) continue; // Dead val#. // Is the def for the val# rematerializable? - if (DefIdx == ~0u) + if (!VNI->isDefAccurate()) return false; - MachineInstr *ReMatDefMI = getInstructionFromIndex(DefIdx); + MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def); bool DefIsLoad = false; if (!ReMatDefMI || !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad)) @@ -972,8 +1128,6 @@ static bool FilterFoldedOps(MachineInstr *MI, SmallVector &Ops, unsigned &MRInfo, SmallVector &FoldOps) { - const TargetInstrDesc &TID = MI->getDesc(); - MRInfo = 0; for (unsigned i = 0, e = Ops.size(); i != e; ++i) { unsigned OpIdx = Ops[i]; @@ -985,8 +1139,7 @@ static bool FilterFoldedOps(MachineInstr *MI, MRInfo |= (unsigned)VirtRegMap::isMod; else { // Filter out two-address use operand(s). - if (!MO.isImplicit() && - TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) { + if (MI->isRegTiedToDefOperand(OpIdx)) { MRInfo = VirtRegMap::isModRef; continue; } @@ -1126,9 +1279,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, const MachineLoopInfo *loopInfo, unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse, DenseMap &MBBVRegsMap, - std::vector &NewLIs, float &SSWeight) { - MachineBasicBlock *MBB = MI->getParent(); - unsigned loopDepth = loopInfo->getLoopDepth(MBB); + std::vector &NewLIs) { bool CanFold = false; RestartInstruction: for (unsigned i = 0; i != MI->getNumOperands(); ++i) { @@ -1209,10 +1360,16 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, // the INSERT_SUBREG and both target registers that would overlap. HasUse = false; - // Update stack slot spill weight if we are splitting. - float Weight = getSpillWeight(HasDef, HasUse, loopDepth); - if (!TrySplit) - SSWeight += Weight; + // Create a new virtual register for the spill interval. + // Create the new register now so we can map the fold instruction + // to the new register so when it is unfolded we get the correct + // answer. + bool CreatedNewVReg = false; + if (NewVReg == 0) { + NewVReg = mri_->createVirtualRegister(rc); + vrm.grow(); + CreatedNewVReg = true; + } if (!TryFold) CanFold = false; @@ -1221,16 +1378,21 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, // optimal point to insert a load / store later. if (!TrySplit) { if (tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index, - Ops, FoldSS, FoldSlot, Reg)) { + Ops, FoldSS, FoldSlot, NewVReg)) { // Folding the load/store can completely change the instruction in // unpredictable ways, rescan it from the beginning. + + if (FoldSS) { + // We need to give the new vreg the same stack slot as the + // spilled interval. + vrm.assignVirt2StackSlot(NewVReg, FoldSlot); + } + HasUse = false; HasDef = false; CanFold = false; - if (isRemoved(MI)) { - SSWeight -= Weight; + if (isNotInMIMap(MI)) break; - } goto RestartInstruction; } } else { @@ -1239,13 +1401,6 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, } } - // Create a new virtual register for the spill interval. - bool CreatedNewVReg = false; - if (NewVReg == 0) { - NewVReg = mri_->createVirtualRegister(rc); - vrm.grow(); - CreatedNewVReg = true; - } mop.setReg(NewVReg); if (mop.isImplicit()) rewriteImplicitOps(li, MI, NewVReg, vrm); @@ -1289,7 +1444,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, if (DefIsReMat && ImpUse) MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true)); - // create a new register interval for this spill / remat. + // Create a new register interval for this spill / remat. LiveInterval &nI = getOrCreateInterval(NewVReg); if (CreatedNewVReg) { NewLIs.push_back(&nI); @@ -1301,7 +1456,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, if (HasUse) { if (CreatedNewVReg) { LiveRange LR(getLoadIndex(index), getUseIndex(index)+1, - nI.getNextValue(~0U, 0, VNInfoAllocator)); + nI.getNextValue(0, 0, false, VNInfoAllocator)); DOUT << " +" << LR; nI.addRange(LR); } else { @@ -1315,7 +1470,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, } if (HasDef) { LiveRange LR(getDefIndex(index), getStoreIndex(index), - nI.getNextValue(~0U, 0, VNInfoAllocator)); + nI.getNextValue(0, 0, false, VNInfoAllocator)); DOUT << " +" << LR; nI.addRange(LR); } @@ -1372,7 +1527,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, BitVector &RestoreMBBs, DenseMap > &RestoreIdxes, DenseMap &MBBVRegsMap, - std::vector &NewLIs, float &SSWeight) { + std::vector &NewLIs) { bool AllCanFold = true; unsigned NewVReg = 0; unsigned start = getBaseIndex(I->start); @@ -1474,7 +1629,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, index, end, MI, ReMatOrigDefMI, ReMatDefMI, Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, CanDelete, vrm, rc, ReMatIds, loopInfo, NewVReg, - ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs, SSWeight); + ImpUse, HasDef, HasUse, MBBVRegsMap, NewLIs); if (!HasDef && !HasUse) continue; @@ -1630,18 +1785,10 @@ LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm, } } -namespace { - struct LISorter { - bool operator()(LiveInterval* A, LiveInterval* B) { - return A->beginNumber() < B->beginNumber(); - } - }; -} - std::vector LiveIntervals:: addIntervalsForSpillsFast(const LiveInterval &li, const MachineLoopInfo *loopInfo, - VirtRegMap &vrm, float& SSWeight) { + VirtRegMap &vrm) { unsigned slot = vrm.assignVirt2StackSlot(li.reg); std::vector added; @@ -1655,8 +1802,6 @@ addIntervalsForSpillsFast(const LiveInterval &li, const TargetRegisterClass* rc = mri_->getRegClass(li.reg); - SSWeight = 0.0f; - MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg); while (RI != mri_->reg_end()) { MachineInstr* MI = &*RI; @@ -1701,14 +1846,14 @@ addIntervalsForSpillsFast(const LiveInterval &li, unsigned index = getInstructionIndex(MI); if (HasUse) { LiveRange LR(getLoadIndex(index), getUseIndex(index), - nI.getNextValue(~0U, 0, getVNInfoAllocator())); + nI.getNextValue(0, 0, false, getVNInfoAllocator())); DOUT << " +" << LR; nI.addRange(LR); vrm.addRestorePoint(NewVReg, MI); } if (HasDef) { LiveRange LR(getDefIndex(index), getStoreIndex(index), - nI.getNextValue(~0U, 0, getVNInfoAllocator())); + nI.getNextValue(0, 0, false, getVNInfoAllocator())); DOUT << " +" << LR; nI.addRange(LR); vrm.addSpillPoint(NewVReg, true, MI); @@ -1719,35 +1864,22 @@ addIntervalsForSpillsFast(const LiveInterval &li, DOUT << "\t\t\t\tadded new interval: "; DEBUG(nI.dump()); DOUT << '\n'; - - unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent()); - if (HasUse) { - if (HasDef) - SSWeight += getSpillWeight(true, true, loopDepth); - else - SSWeight += getSpillWeight(false, true, loopDepth); - } else - SSWeight += getSpillWeight(true, false, loopDepth); } RI = mri_->reg_begin(li.reg); } - // Clients expect the new intervals to be returned in sorted order. - std::sort(added.begin(), added.end(), LISorter()); - return added; } std::vector LiveIntervals:: addIntervalsForSpills(const LiveInterval &li, SmallVectorImpl &SpillIs, - const MachineLoopInfo *loopInfo, VirtRegMap &vrm, - float &SSWeight) { + const MachineLoopInfo *loopInfo, VirtRegMap &vrm) { if (EnableFastSpilling) - return addIntervalsForSpillsFast(li, loopInfo, vrm, SSWeight); + return addIntervalsForSpillsFast(li, loopInfo, vrm); assert(li.weight != HUGE_VALF && "attempt to spill already spilled interval!"); @@ -1756,10 +1888,7 @@ addIntervalsForSpills(const LiveInterval &li, li.print(DOUT, tri_); DOUT << '\n'; - // Spill slot weight. - SSWeight = 0.0f; - - // Each bit specify whether it a spill is required in the MBB. + // Each bit specify whether a spill is required in the MBB. BitVector SpillMBBs(mf_->getNumBlockIDs()); DenseMap > SpillIdxes; BitVector RestoreMBBs(mf_->getNumBlockIDs()); @@ -1800,7 +1929,7 @@ addIntervalsForSpills(const LiveInterval &li, int LdSlot = 0; bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot); bool isLoad = isLoadSS || - (DefIsReMat && (ReMatDefMI->getDesc().isSimpleLoad())); + (DefIsReMat && (ReMatDefMI->getDesc().canFoldAsLoad())); bool IsFirstRange = true; for (LiveInterval::Ranges::const_iterator I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) { @@ -1813,18 +1942,17 @@ addIntervalsForSpills(const LiveInterval &li, Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, false, vrm, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, - MBBVRegsMap, NewLIs, SSWeight); + MBBVRegsMap, NewLIs); } else { rewriteInstructionsForSpills(li, false, I, NULL, 0, Slot, 0, false, false, false, false, vrm, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, - MBBVRegsMap, NewLIs, SSWeight); + MBBVRegsMap, NewLIs); } IsFirstRange = false; } - SSWeight = 0.0f; // Already accounted for when split. handleSpilledImpDefs(li, vrm, rc, NewLIs); return NewLIs; } @@ -1839,12 +1967,11 @@ addIntervalsForSpills(const LiveInterval &li, i != e; ++i) { const VNInfo *VNI = *i; unsigned VN = VNI->id; - unsigned DefIdx = VNI->def; - if (DefIdx == ~1U) + if (VNI->isUnused()) continue; // Dead val#. // Is the def for the val# rematerializable? - MachineInstr *ReMatDefMI = (DefIdx == ~0u) - ? 0 : getInstructionFromIndex(DefIdx); + MachineInstr *ReMatDefMI = VNI->isDefAccurate() + ? getInstructionFromIndex(VNI->def) : 0; bool dummy; if (ReMatDefMI && isReMaterializable(li, VNI, ReMatDefMI, SpillIs, dummy)) { // Remember how to remat the def of this val#. @@ -1855,7 +1982,7 @@ addIntervalsForSpills(const LiveInterval &li, ReMatDefs[VN] = Clone; bool CanDelete = true; - if (VNI->hasPHIKill) { + if (VNI->hasPHIKill()) { // A kill is a phi node, not all of its uses can be rematerialized. // It must not be deleted. CanDelete = false; @@ -1873,8 +2000,15 @@ addIntervalsForSpills(const LiveInterval &li, } // One stack slot per live interval. - if (NeedStackSlot && vrm.getPreSplitReg(li.reg) == 0) - Slot = vrm.assignVirt2StackSlot(li.reg); + if (NeedStackSlot && vrm.getPreSplitReg(li.reg) == 0) { + if (vrm.getStackSlot(li.reg) == VirtRegMap::NO_STACK_SLOT) + Slot = vrm.assignVirt2StackSlot(li.reg); + + // This case only occurs when the prealloc splitter has already assigned + // a stack slot to this vreg. + else + Slot = vrm.getStackSlot(li.reg); + } // Create new intervals and rewrite defs and uses. for (LiveInterval::Ranges::const_iterator @@ -1886,12 +2020,12 @@ addIntervalsForSpills(const LiveInterval &li, int LdSlot = 0; bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot); bool isLoad = isLoadSS || - (DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad()); + (DefIsReMat && ReMatDefMI->getDesc().canFoldAsLoad()); rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI, Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, CanDelete, vrm, rc, ReMatIds, loopInfo, SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes, - MBBVRegsMap, NewLIs, SSWeight); + MBBVRegsMap, NewLIs); } // Insert spills / restores if we are splitting. @@ -1905,8 +2039,6 @@ addIntervalsForSpills(const LiveInterval &li, if (NeedStackSlot) { int Id = SpillMBBs.find_first(); while (Id != -1) { - MachineBasicBlock *MBB = mf_->getBlockNumbered(Id); - unsigned loopDepth = loopInfo->getLoopDepth(MBB); std::vector &spills = SpillIdxes[Id]; for (unsigned i = 0, e = spills.size(); i != e; ++i) { int index = spills[i].index; @@ -1944,7 +2076,7 @@ addIntervalsForSpills(const LiveInterval &li, if (CanFold && !Ops.empty()) { if (tryFoldMemoryOperand(MI, vrm, NULL, index, Ops, true, Slot,VReg)){ Folded = true; - if (FoundUse > 0) { + if (FoundUse) { // Also folded uses, do not issue a load. eraseRestoreInfo(Id, index, VReg, RestoreMBBs, RestoreIdxes); nI.removeRange(getLoadIndex(index), getUseIndex(index)+1); @@ -1963,10 +2095,6 @@ addIntervalsForSpills(const LiveInterval &li, if (isKill) AddedKill.insert(&nI); } - - // Update spill slot weight. - if (!isReMat) - SSWeight += getSpillWeight(true, false, loopDepth); } Id = SpillMBBs.find_next(Id); } @@ -1974,9 +2102,6 @@ addIntervalsForSpills(const LiveInterval &li, int Id = RestoreMBBs.find_first(); while (Id != -1) { - MachineBasicBlock *MBB = mf_->getBlockNumbered(Id); - unsigned loopDepth = loopInfo->getLoopDepth(MBB); - std::vector &restores = RestoreIdxes[Id]; for (unsigned i = 0, e = restores.size(); i != e; ++i) { int index = restores[i].index; @@ -2015,18 +2140,20 @@ addIntervalsForSpills(const LiveInterval &li, int LdSlot = 0; bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot); // If the rematerializable def is a load, also try to fold it. - if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad()) + if (isLoadSS || ReMatDefMI->getDesc().canFoldAsLoad()) Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index, Ops, isLoadSS, LdSlot, VReg); - unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI); - if (ImpUse) { - // Re-matting an instruction with virtual register use. Add the - // register as an implicit use on the use MI and update the register - // interval's spill weight to HUGE_VALF to prevent it from being - // spilled. - LiveInterval &ImpLi = getInterval(ImpUse); - ImpLi.weight = HUGE_VALF; - MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true)); + if (!Folded) { + unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI); + if (ImpUse) { + // Re-matting an instruction with virtual register use. Add the + // register as an implicit use on the use MI and update the register + // interval's spill weight to HUGE_VALF to prevent it from being + // spilled. + LiveInterval &ImpLi = getInterval(ImpUse); + ImpLi.weight = HUGE_VALF; + MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true)); + } } } } @@ -2036,10 +2163,6 @@ addIntervalsForSpills(const LiveInterval &li, nI.removeRange(getLoadIndex(index), getUseIndex(index)+1); else vrm.addRestorePoint(VReg, MI); - - // Update spill slot weight. - if (!isReMat) - SSWeight += getSpillWeight(false, true, loopDepth); } Id = RestoreMBBs.find_next(Id); } @@ -2057,8 +2180,7 @@ addIntervalsForSpills(const LiveInterval &li, MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx); int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg, false); assert(UseIdx != -1); - if (LastUse->getOperand(UseIdx).isImplicit() || - LastUse->getDesc().getOperandConstraint(UseIdx,TOI::TIED_TO) == -1){ + if (!LastUse->isRegTiedToDefOperand(UseIdx)) { LastUse->getOperand(UseIdx).setIsKill(); vrm.addKillPoint(LI->reg, LastUseIdx); } @@ -2113,8 +2235,9 @@ unsigned LiveIntervals::getNumConflictsWithPhysReg(const LiveInterval &li, } /// spillPhysRegAroundRegDefsUses - Spill the specified physical register -/// around all defs and uses of the specified interval. -void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, +/// around all defs and uses of the specified interval. Return true if it +/// was able to cut its interval. +bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, unsigned PhysReg, VirtRegMap &vrm) { unsigned SpillReg = getRepresentativeReg(PhysReg); @@ -2122,9 +2245,10 @@ void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, // If there are registers which alias PhysReg, but which are not a // sub-register of the chosen representative super register. Assert // since we can't handle it yet. - assert(*AS == SpillReg || !allocatableRegs_[*AS] || + assert(*AS == SpillReg || !allocatableRegs_[*AS] || !hasInterval(*AS) || tri_->isSuperRegister(*AS, SpillReg)); + bool Cut = false; LiveInterval &pli = getInterval(SpillReg); SmallPtrSet SeenMIs; for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li.reg), @@ -2137,7 +2261,20 @@ void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, unsigned Index = getInstructionIndex(MI); if (pli.liveAt(Index)) { vrm.addEmergencySpill(SpillReg, MI); - pli.removeRange(getLoadIndex(Index), getStoreIndex(Index)+1); + unsigned StartIdx = getLoadIndex(Index); + unsigned EndIdx = getStoreIndex(Index)+1; + if (pli.isInOneLiveRange(StartIdx, EndIdx)) { + pli.removeRange(StartIdx, EndIdx); + Cut = true; + } else { + cerr << "Ran out of registers during register allocation!\n"; + if (MI->getOpcode() == TargetInstrInfo::INLINEASM) { + cerr << "Please check your inline asm statement for invalid " + << "constraints:\n"; + MI->print(cerr.stream(), tm_); + } + exit(1); + } for (const unsigned* AS = tri_->getSubRegisters(SpillReg); *AS; ++AS) { if (!hasInterval(*AS)) continue; @@ -2147,6 +2284,7 @@ void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, } } } + return Cut; } LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg, @@ -2154,8 +2292,8 @@ LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg, LiveInterval& Interval = getOrCreateInterval(reg); VNInfo* VN = Interval.getNextValue( getInstructionIndex(startInst) + InstrSlots::DEF, - startInst, getVNInfoAllocator()); - VN->hasPHIKill = true; + startInst, true, getVNInfoAllocator()); + VN->setHasPHIKill(true); VN->kills.push_back(getMBBEndIdx(startInst->getParent())); LiveRange LR(getInstructionIndex(startInst) + InstrSlots::DEF, getMBBEndIdx(startInst->getParent()) + 1, VN);