X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLiveIntervalAnalysis.cpp;h=d75bf3fb0efd1d59ddfb057663e9feaa7b477e83;hb=712ad0c36dcfacb30620c793a6ffe4e80bd5d569;hp=ebf9dcd2dd12e40d5ae2a774bddb71852ca695e1;hpb=cc0d156f7bca0811aade0a95b0e7419176383c90;p=oota-llvm.git diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index ebf9dcd2dd1..d75bf3fb0ef 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -1,4 +1,4 @@ -//===-- LiveIntervals.cpp - Live Interval Analysis ------------------------===// +//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// // // The LLVM Compiler Infrastructure // @@ -16,7 +16,8 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "liveintervals" -#include "LiveIntervals.h" +#include "LiveIntervalAnalysis.h" +#include "VirtRegMap.h" #include "llvm/Value.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/CodeGen/LiveVariables.h" @@ -27,425 +28,559 @@ #include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "Support/CommandLine.h" -#include "Support/Debug.h" -#include "Support/Statistic.h" -#include "Support/STLExtras.h" -#include "VirtRegMap.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" +#include #include -#include - using namespace llvm; namespace { - RegisterAnalysis X("liveintervals", - "Live Interval Analysis"); + RegisterAnalysis X("liveintervals", "Live Interval Analysis"); - Statistic<> numIntervals - ("liveintervals", "Number of original intervals"); + Statistic<> numIntervals + ("liveintervals", "Number of original intervals"); - Statistic<> numIntervalsAfter - ("liveintervals", "Number of intervals after coalescing"); + Statistic<> numIntervalsAfter + ("liveintervals", "Number of intervals after coalescing"); - Statistic<> numJoins - ("liveintervals", "Number of interval joins performed"); + Statistic<> numJoins + ("liveintervals", "Number of interval joins performed"); - Statistic<> numPeep - ("liveintervals", "Number of identity moves eliminated after coalescing"); + Statistic<> numPeep + ("liveintervals", "Number of identity moves eliminated after coalescing"); - Statistic<> numFolded - ("liveintervals", "Number of loads/stores folded into instructions"); + Statistic<> numFolded + ("liveintervals", "Number of loads/stores folded into instructions"); - cl::opt - EnableJoining("join-liveintervals", - cl::desc("Join compatible live intervals"), - cl::init(true)); + cl::opt + EnableJoining("join-liveintervals", + cl::desc("Join compatible live intervals"), + cl::init(true)); }; void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addPreserved(); - AU.addRequired(); - AU.addPreservedID(PHIEliminationID); - AU.addRequiredID(PHIEliminationID); - AU.addRequiredID(TwoAddressInstructionPassID); - AU.addRequired(); - MachineFunctionPass::getAnalysisUsage(AU); + AU.addPreserved(); + AU.addRequired(); + AU.addPreservedID(PHIEliminationID); + AU.addRequiredID(PHIEliminationID); + AU.addRequiredID(TwoAddressInstructionPassID); + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); } void LiveIntervals::releaseMemory() { - mi2iMap_.clear(); - i2miMap_.clear(); - r2iMap_.clear(); - r2rMap_.clear(); - intervals_.clear(); + mi2iMap_.clear(); + i2miMap_.clear(); + r2iMap_.clear(); + r2rMap_.clear(); } /// runOnMachineFunction - Register allocate the whole function /// bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { - mf_ = &fn; - tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); - lv_ = &getAnalysis(); - - // number MachineInstrs - unsigned miIndex = 0; - for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end(); - mbb != mbbEnd; ++mbb) - for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); - mi != miEnd; ++mi) { - bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second; - assert(inserted && "multiple MachineInstr -> index mappings"); - i2miMap_.push_back(mi); - miIndex += InstrSlots::NUM; - } + mf_ = &fn; + tm_ = &fn.getTarget(); + mri_ = tm_->getRegisterInfo(); + tii_ = tm_->getInstrInfo(); + lv_ = &getAnalysis(); + allocatableRegs_ = mri_->getAllocatableSet(fn); + r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); + + // If this function has any live ins, insert a dummy instruction at the + // beginning of the function that we will pretend "defines" the values. This + // is to make the interval analysis simpler by providing a number. + if (fn.livein_begin() != fn.livein_end()) { + unsigned FirstLiveIn = fn.livein_begin()->first; + + // Find a reg class that contains this live in. + const TargetRegisterClass *RC = 0; + for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), + E = mri_->regclass_end(); RCI != E; ++RCI) + if ((*RCI)->contains(FirstLiveIn)) { + RC = *RCI; + break; + } + + MachineInstr *OldFirstMI = fn.begin()->begin(); + mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(), + FirstLiveIn, FirstLiveIn, RC); + assert(OldFirstMI != fn.begin()->begin() && + "copyRetToReg didn't insert anything!"); + } + + // number MachineInstrs + unsigned miIndex = 0; + for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end(); + mbb != mbbEnd; ++mbb) + for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); + mi != miEnd; ++mi) { + bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second; + assert(inserted && "multiple MachineInstr -> index mappings"); + i2miMap_.push_back(mi); + miIndex += InstrSlots::NUM; + } + + // Note intervals due to live-in values. + if (fn.livein_begin() != fn.livein_end()) { + MachineBasicBlock *Entry = fn.begin(); + for (MachineFunction::livein_iterator I = fn.livein_begin(), + E = fn.livein_end(); I != E; ++I) { + handlePhysicalRegisterDef(Entry, Entry->begin(), + getOrCreateInterval(I->first), 0, 0); + for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS) + handlePhysicalRegisterDef(Entry, Entry->begin(), + getOrCreateInterval(*AS), 0, 0); + } + } - computeIntervals(); - - numIntervals += intervals_.size(); - - // join intervals if requested - if (EnableJoining) joinIntervals(); - - numIntervalsAfter += intervals_.size(); - - // perform a final pass over the instructions and compute spill - // weights, coalesce virtual registers and remove identity moves - const LoopInfo& loopInfo = getAnalysis(); - const TargetInstrInfo& tii = *tm_->getInstrInfo(); - - for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); - mbbi != mbbe; ++mbbi) { - MachineBasicBlock* mbb = mbbi; - unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); - - for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); - mii != mie; ) { - // if the move will be an identity move delete it - unsigned srcReg, dstReg; - if (tii.isMoveInstr(*mii, srcReg, dstReg) && - rep(srcReg) == rep(dstReg)) { - // remove from def list - LiveInterval& interval = getOrCreateInterval(rep(dstReg)); - // remove index -> MachineInstr and - // MachineInstr -> index mappings - Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii); - if (mi2i != mi2iMap_.end()) { - i2miMap_[mi2i->second/InstrSlots::NUM] = 0; - mi2iMap_.erase(mi2i); - } - mii = mbbi->erase(mii); - ++numPeep; - } - else { - for (unsigned i = 0; i < mii->getNumOperands(); ++i) { - const MachineOperand& mop = mii->getOperand(i); - if (mop.isRegister() && mop.getReg() && - MRegisterInfo::isVirtualRegister(mop.getReg())) { - // replace register with representative register - unsigned reg = rep(mop.getReg()); - mii->SetMachineOperandReg(i, reg); - - Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg); - assert(r2iit != r2iMap_.end()); - r2iit->second->weight += - (mop.isUse() + mop.isDef()) * pow(10.0F, loopDepth); - } - } - ++mii; - } + computeIntervals(); + + numIntervals += getNumIntervals(); + +#if 1 + DEBUG(std::cerr << "********** INTERVALS **********\n"); + DEBUG(for (iterator I = begin(), E = end(); I != E; ++I) + std::cerr << I->second << "\n"); +#endif + + // join intervals if requested + if (EnableJoining) joinIntervals(); + + numIntervalsAfter += getNumIntervals(); + + // perform a final pass over the instructions and compute spill + // weights, coalesce virtual registers and remove identity moves + const LoopInfo& loopInfo = getAnalysis(); + + for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); + mbbi != mbbe; ++mbbi) { + MachineBasicBlock* mbb = mbbi; + unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); + + for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); + mii != mie; ) { + // if the move will be an identity move delete it + unsigned srcReg, dstReg, RegRep; + if (tii_->isMoveInstr(*mii, srcReg, dstReg) && + (RegRep = rep(srcReg)) == rep(dstReg)) { + // remove from def list + LiveInterval &interval = getOrCreateInterval(RegRep); + // remove index -> MachineInstr and + // MachineInstr -> index mappings + Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii); + if (mi2i != mi2iMap_.end()) { + i2miMap_[mi2i->second/InstrSlots::NUM] = 0; + mi2iMap_.erase(mi2i); + } + mii = mbbi->erase(mii); + ++numPeep; + } + else { + for (unsigned i = 0; i < mii->getNumOperands(); ++i) { + const MachineOperand& mop = mii->getOperand(i); + if (mop.isRegister() && mop.getReg() && + MRegisterInfo::isVirtualRegister(mop.getReg())) { + // replace register with representative register + unsigned reg = rep(mop.getReg()); + mii->SetMachineOperandReg(i, reg); + + LiveInterval &RegInt = getInterval(reg); + RegInt.weight += + (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); + } } + ++mii; + } } + } - intervals_.sort(); - DEBUG(std::cerr << "********** INTERVALS **********\n"); - DEBUG(std::copy(intervals_.begin(), intervals_.end(), - std::ostream_iterator(std::cerr, "\n"))); - DEBUG(std::cerr << "********** MACHINEINSTRS **********\n"); - DEBUG( - for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); - mbbi != mbbe; ++mbbi) { - std::cerr << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; - for (MachineBasicBlock::iterator mii = mbbi->begin(), - mie = mbbi->end(); mii != mie; ++mii) { - std::cerr << getInstructionIndex(mii) << '\t'; - mii->print(std::cerr, tm_); - } - }); - - return true; + DEBUG(dump()); + return true; } -namespace { - /// CompareIntervalStar - This is a simple comparison function for interval - /// pointers. It compares based on their starting point. - struct CompareIntervalStar { - bool operator()(LiveInterval *LHS, LiveInterval* RHS) const { - return LHS->start() < RHS->start(); - } - }; +/// print - Implement the dump method. +void LiveIntervals::print(std::ostream &O, const Module* ) const { + O << "********** INTERVALS **********\n"; + for (const_iterator I = begin(), E = end(); I != E; ++I) + O << " " << I->second << "\n"; + + O << "********** MACHINEINSTRS **********\n"; + for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); + mbbi != mbbe; ++mbbi) { + O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; + for (MachineBasicBlock::iterator mii = mbbi->begin(), + mie = mbbi->end(); mii != mie; ++mii) { + O << getInstructionIndex(mii) << '\t' << *mii; + } + } } -std::vector LiveIntervals::addIntervalsForSpills( - const LiveInterval& li, - VirtRegMap& vrm, - int slot) -{ - std::vector added; - - assert(li.weight != HUGE_VAL && - "attempt to spill already spilled interval!"); - - DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: " - << li << '\n'); - - const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); - - for (LiveInterval::Ranges::const_iterator - i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { - unsigned index = getBaseIndex(i->first); - unsigned end = getBaseIndex(i->second-1) + InstrSlots::NUM; - for (; index < end; index += InstrSlots::NUM) { - // skip deleted instructions - while (!getInstructionFromIndex(index)) index += InstrSlots::NUM; - MachineBasicBlock::iterator mi = getInstructionFromIndex(index); - - for_operand: - for (unsigned i = 0; i != mi->getNumOperands(); ++i) { - MachineOperand& mop = mi->getOperand(i); - if (mop.isRegister() && mop.getReg() == li.reg) { - if (MachineInstr* fmi = - mri_->foldMemoryOperand(mi, i, slot)) { - lv_->instructionChanged(mi, fmi); - vrm.virtFolded(li.reg, mi, fmi); - mi2iMap_.erase(mi); - i2miMap_[index/InstrSlots::NUM] = fmi; - mi2iMap_[fmi] = index; - MachineBasicBlock& mbb = *mi->getParent(); - mi = mbb.insert(mbb.erase(mi), fmi); - ++numFolded; - goto for_operand; - } - else { - // This is tricky. We need to add information in - // the interval about the spill code so we have to - // use our extra load/store slots. - // - // If we have a use we are going to have a load so - // we start the interval from the load slot - // onwards. Otherwise we start from the def slot. - unsigned start = (mop.isUse() ? - getLoadIndex(index) : - getDefIndex(index)); - // If we have a def we are going to have a store - // right after it so we end the interval after the - // use of the next instruction. Otherwise we end - // after the use of this instruction. - unsigned end = 1 + (mop.isDef() ? - getStoreIndex(index) : - getUseIndex(index)); - - // create a new register for this spill - unsigned nReg = - mf_->getSSARegMap()->createVirtualRegister(rc); - mi->SetMachineOperandReg(i, nReg); - vrm.grow(); - vrm.assignVirt2StackSlot(nReg, slot); - LiveInterval& nI = getOrCreateInterval(nReg); - assert(nI.empty()); - // the spill weight is now infinity as it - // cannot be spilled again - nI.weight = HUGE_VAL; - nI.addRange(start, end); - added.push_back(&nI); - // update live variables - lv_->addVirtualRegisterKilled(nReg, mi); - DEBUG(std::cerr << "\t\t\t\tadded new interval: " - << nI << '\n'); - } - } - } +std::vector LiveIntervals:: +addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { + // since this is called after the analysis is done we don't know if + // LiveVariables is available + lv_ = getAnalysisToUpdate(); + + std::vector added; + + assert(li.weight != HUGE_VAL && + "attempt to spill already spilled interval!"); + + DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: " + << li << '\n'); + + const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); + + for (LiveInterval::Ranges::const_iterator + i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { + unsigned index = getBaseIndex(i->start); + unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; + for (; index != end; index += InstrSlots::NUM) { + // skip deleted instructions + while (index != end && !getInstructionFromIndex(index)) + index += InstrSlots::NUM; + if (index == end) break; + + MachineBasicBlock::iterator mi = getInstructionFromIndex(index); + + for_operand: + for (unsigned i = 0; i != mi->getNumOperands(); ++i) { + MachineOperand& mop = mi->getOperand(i); + if (mop.isRegister() && mop.getReg() == li.reg) { + // First thing, attempt to fold the memory reference into the + // instruction. If we can do this, we don't need to insert spill + // code. + if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) { + if (lv_) + lv_->instructionChanged(mi, fmi); + vrm.virtFolded(li.reg, mi, i, fmi); + mi2iMap_.erase(mi); + i2miMap_[index/InstrSlots::NUM] = fmi; + mi2iMap_[fmi] = index; + MachineBasicBlock &MBB = *mi->getParent(); + mi = MBB.insert(MBB.erase(mi), fmi); + ++numFolded; + + // Folding the load/store can completely change the instruction in + // unpredictable ways, rescan it from the beginning. + goto for_operand; + } else { + // This is tricky. We need to add information in the interval about + // the spill code so we have to use our extra load/store slots. + // + // If we have a use we are going to have a load so we start the + // interval from the load slot onwards. Otherwise we start from the + // def slot. + unsigned start = (mop.isUse() ? + getLoadIndex(index) : + getDefIndex(index)); + // If we have a def we are going to have a store right after it so + // we end the interval after the use of the next + // instruction. Otherwise we end after the use of this instruction. + unsigned end = 1 + (mop.isDef() ? + getStoreIndex(index) : + getUseIndex(index)); + + // create a new register for this spill + unsigned nReg = mf_->getSSARegMap()->createVirtualRegister(rc); + mi->SetMachineOperandReg(i, nReg); + vrm.grow(); + vrm.assignVirt2StackSlot(nReg, slot); + LiveInterval& nI = getOrCreateInterval(nReg); + assert(nI.empty()); + + // the spill weight is now infinity as it + // cannot be spilled again + nI.weight = float(HUGE_VAL); + LiveRange LR(start, end, nI.getNextValue()); + DEBUG(std::cerr << " +" << LR); + nI.addRange(LR); + added.push_back(&nI); + + // update live variables if it is available + if (lv_) + lv_->addVirtualRegisterKilled(nReg, mi); + DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n'); + } } + } } + } - // FIXME: This method MUST return intervals in sorted order. If a - // particular machine instruction both uses and defines the vreg being - // spilled (e.g., vr = vr + 1) and if the def is processed before the - // use, the list ends up not sorted. - // - // The proper way to fix this is to process all uses of the vreg before we - // process any defs. However, this would require refactoring the above - // blob of code, which I'm not feeling up to right now. - std::sort(added.begin(), added.end(), CompareIntervalStar()); - return added; + return added; } void LiveIntervals::printRegName(unsigned reg) const { - if (MRegisterInfo::isPhysicalRegister(reg)) - std::cerr << mri_->getName(reg); - else - std::cerr << "%reg" << reg; + if (MRegisterInfo::isPhysicalRegister(reg)) + std::cerr << mri_->getName(reg); + else + std::cerr << "%reg" << reg; } void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb, MachineBasicBlock::iterator mi, LiveInterval& interval) { - DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); - LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); - - // Virtual registers may be defined multiple times (due to phi - // elimination). Much of what we do only has to be done once for the vreg. - // We use an empty interval to detect the first time we see a vreg. - if (interval.empty()) { - - // Get the Idx of the defining instructions. - unsigned defIndex = getDefIndex(getInstructionIndex(mi)); - - // Loop over all of the blocks that the vreg is defined in. There are - // two cases we have to handle here. The most common case is a vreg - // whose lifetime is contained within a basic block. In this case there - // will be a single kill, in MBB, which comes after the definition. - if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { - // FIXME: what about dead vars? - unsigned killIdx; - if (vi.Kills[0] != mi) - killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; - else - killIdx = defIndex+1; - - // If the kill happens after the definition, we have an intra-block - // live range. - if (killIdx > defIndex) { - assert(vi.AliveBlocks.empty() && - "Shouldn't be alive across any blocks!"); - interval.addRange(defIndex, killIdx); - return; - } - } - - // The other case we handle is when a virtual register lives to the end - // of the defining block, potentially live across some blocks, then is - // live into some number of blocks, but gets killed. Start by adding a - // range that goes from this definition to the end of the defining block. - interval.addRange(defIndex, - getInstructionIndex(&mbb->back()) + InstrSlots::NUM); - - // Iterate over all of the blocks that the variable is completely - // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the - // live interval. - for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { - if (vi.AliveBlocks[i]) { - MachineBasicBlock* mbb = mf_->getBlockNumbered(i); - if (!mbb->empty()) { - interval.addRange( - getInstructionIndex(&mbb->front()), - getInstructionIndex(&mbb->back()) + InstrSlots::NUM); - } - } - } - - // Finally, this virtual register is live from the start of any killing - // block to the 'use' slot of the killing instruction. - for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { - MachineInstr *Kill = vi.Kills[i]; - interval.addRange(getInstructionIndex(Kill->getParent()->begin()), - getUseIndex(getInstructionIndex(Kill))+1); - } + DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); + LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); + + // Virtual registers may be defined multiple times (due to phi + // elimination and 2-addr elimination). Much of what we do only has to be + // done once for the vreg. We use an empty interval to detect the first + // time we see a vreg. + if (interval.empty()) { + // Get the Idx of the defining instructions. + unsigned defIndex = getDefIndex(getInstructionIndex(mi)); + + unsigned ValNum = interval.getNextValue(); + assert(ValNum == 0 && "First value in interval is not 0?"); + ValNum = 0; // Clue in the optimizer. + + // Loop over all of the blocks that the vreg is defined in. There are + // two cases we have to handle here. The most common case is a vreg + // whose lifetime is contained within a basic block. In this case there + // will be a single kill, in MBB, which comes after the definition. + if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { + // FIXME: what about dead vars? + unsigned killIdx; + if (vi.Kills[0] != mi) + killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; + else + killIdx = defIndex+1; + + // If the kill happens after the definition, we have an intra-block + // live range. + if (killIdx > defIndex) { + assert(vi.AliveBlocks.empty() && + "Shouldn't be alive across any blocks!"); + LiveRange LR(defIndex, killIdx, ValNum); + interval.addRange(LR); + DEBUG(std::cerr << " +" << LR << "\n"); + return; + } + } + + // The other case we handle is when a virtual register lives to the end + // of the defining block, potentially live across some blocks, then is + // live into some number of blocks, but gets killed. Start by adding a + // range that goes from this definition to the end of the defining block. + LiveRange NewLR(defIndex, + getInstructionIndex(&mbb->back()) + InstrSlots::NUM, + ValNum); + DEBUG(std::cerr << " +" << NewLR); + interval.addRange(NewLR); + + // Iterate over all of the blocks that the variable is completely + // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the + // live interval. + for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { + if (vi.AliveBlocks[i]) { + MachineBasicBlock* mbb = mf_->getBlockNumbered(i); + if (!mbb->empty()) { + LiveRange LR(getInstructionIndex(&mbb->front()), + getInstructionIndex(&mbb->back()) + InstrSlots::NUM, + ValNum); + interval.addRange(LR); + DEBUG(std::cerr << " +" << LR); + } + } + } + + // Finally, this virtual register is live from the start of any killing + // block to the 'use' slot of the killing instruction. + for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { + MachineInstr *Kill = vi.Kills[i]; + LiveRange LR(getInstructionIndex(Kill->getParent()->begin()), + getUseIndex(getInstructionIndex(Kill))+1, + ValNum); + interval.addRange(LR); + DEBUG(std::cerr << " +" << LR); + } + + } else { + // If this is the second time we see a virtual register definition, it + // must be due to phi elimination or two addr elimination. If this is + // the result of two address elimination, then the vreg is the first + // operand, and is a def-and-use. + if (mi->getOperand(0).isRegister() && + mi->getOperand(0).getReg() == interval.reg && + mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) { + // If this is a two-address definition, then we have already processed + // the live range. The only problem is that we didn't realize there + // are actually two values in the live interval. Because of this we + // need to take the LiveRegion that defines this register and split it + // into two values. + unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); + unsigned RedefIndex = getDefIndex(getInstructionIndex(mi)); + + // Delete the initial value, which should be short and continuous, + // becuase the 2-addr copy must be in the same MBB as the redef. + interval.removeRange(DefIndex, RedefIndex); + + LiveRange LR(DefIndex, RedefIndex, interval.getNextValue()); + DEBUG(std::cerr << " replace range with " << LR); + interval.addRange(LR); + + // If this redefinition is dead, we need to add a dummy unit live + // range covering the def slot. + for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi), + E = lv_->dead_end(mi); KI != E; ++KI) + if (KI->second == interval.reg) { + interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); + break; + } + + DEBUG(std::cerr << "RESULT: " << interval); } else { - // If this is the second time we see a virtual register definition, it - // must be due to phi elimination. In this case, the defined value will - // be live until the end of the basic block it is defined in. - unsigned defIndex = getDefIndex(getInstructionIndex(mi)); - interval.addRange(defIndex, - getInstructionIndex(&mbb->back()) + InstrSlots::NUM); + // Otherwise, this must be because of phi elimination. If this is the + // first redefinition of the vreg that we have seen, go back and change + // the live range in the PHI block to be a different value number. + if (interval.containsOneValue()) { + assert(vi.Kills.size() == 1 && + "PHI elimination vreg should have one kill, the PHI itself!"); + + // Remove the old range that we now know has an incorrect number. + MachineInstr *Killer = vi.Kills[0]; + unsigned Start = getInstructionIndex(Killer->getParent()->begin()); + unsigned End = getUseIndex(getInstructionIndex(Killer))+1; + DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: " + << interval << "\n"); + interval.removeRange(Start, End); + DEBUG(std::cerr << "RESULT: " << interval); + + // Replace the interval with one of a NEW value number. + LiveRange LR(Start, End, interval.getNextValue()); + DEBUG(std::cerr << " replace range with " << LR); + interval.addRange(LR); + DEBUG(std::cerr << "RESULT: " << interval); + } + + // In the case of PHI elimination, each variable definition is only + // live until the end of the block. We've already taken care of the + // rest of the live range. + unsigned defIndex = getDefIndex(getInstructionIndex(mi)); + LiveRange LR(defIndex, + getInstructionIndex(&mbb->back()) + InstrSlots::NUM, + interval.getNextValue()); + interval.addRange(LR); + DEBUG(std::cerr << " +" << LR); } + } - DEBUG(std::cerr << '\n'); + DEBUG(std::cerr << '\n'); } -void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock* mbb, +void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, MachineBasicBlock::iterator mi, - LiveInterval& interval) + LiveInterval& interval, + unsigned SrcReg, unsigned DestReg) { - // A physical register cannot be live across basic block, so its - // lifetime must end somewhere in its defining basic block. - DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); - typedef LiveVariables::killed_iterator KillIter; - - MachineBasicBlock::iterator e = mbb->end(); - unsigned baseIndex = getInstructionIndex(mi); - unsigned start = getDefIndex(baseIndex); - unsigned end = start; - - // If it is not used after definition, it is considered dead at - // the instruction defining it. Hence its interval is: - // [defSlot(def), defSlot(def)+1) - for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi); - ki != ke; ++ki) { - if (interval.reg == ki->second) { - DEBUG(std::cerr << " dead"); - end = getDefIndex(start) + 1; - goto exit; - } + // A physical register cannot be live across basic block, so its + // lifetime must end somewhere in its defining basic block. + DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); + typedef LiveVariables::killed_iterator KillIter; + + unsigned baseIndex = getInstructionIndex(mi); + unsigned start = getDefIndex(baseIndex); + unsigned end = start; + + // If it is not used after definition, it is considered dead at + // the instruction defining it. Hence its interval is: + // [defSlot(def), defSlot(def)+1) + for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi); + ki != ke; ++ki) { + if (interval.reg == ki->second) { + DEBUG(std::cerr << " dead"); + end = getDefIndex(start) + 1; + goto exit; } + } - // If it is not dead on definition, it must be killed by a - // subsequent instruction. Hence its interval is: - // [defSlot(def), useSlot(kill)+1) - do { - ++mi; - baseIndex += InstrSlots::NUM; - for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi); - ki != ke; ++ki) { - if (interval.reg == ki->second) { - DEBUG(std::cerr << " killed"); - end = getUseIndex(baseIndex) + 1; - goto exit; - } - } - } while (mi != e); + // If it is not dead on definition, it must be killed by a + // subsequent instruction. Hence its interval is: + // [defSlot(def), useSlot(kill)+1) + while (true) { + ++mi; + assert(mi != MBB->end() && "physreg was not killed in defining block!"); + baseIndex += InstrSlots::NUM; + for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi); + ki != ke; ++ki) { + if (interval.reg == ki->second) { + DEBUG(std::cerr << " killed"); + end = getUseIndex(baseIndex) + 1; + goto exit; + } + } + } exit: - assert(start < end && "did not find end of interval?"); - interval.addRange(start, end); - DEBUG(std::cerr << '\n'); -} - -void LiveIntervals::handleRegisterDef(MachineBasicBlock* mbb, - MachineBasicBlock::iterator mi, - unsigned reg) -{ - if (MRegisterInfo::isPhysicalRegister(reg)) { - if (lv_->getAllocatablePhysicalRegisters()[reg]) { - handlePhysicalRegisterDef(mbb, mi, getOrCreateInterval(reg)); - for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as) - handlePhysicalRegisterDef(mbb, mi, getOrCreateInterval(*as)); + assert(start < end && "did not find end of interval?"); + + // Finally, if this is defining a new range for the physical register, and if + // that physreg is just a copy from a vreg, and if THAT vreg was a copy from + // the physreg, then the new fragment has the same value as the one copied + // into the vreg. + if (interval.reg == DestReg && !interval.empty() && + MRegisterInfo::isVirtualRegister(SrcReg)) { + + // Get the live interval for the vreg, see if it is defined by a copy. + LiveInterval &SrcInterval = getOrCreateInterval(SrcReg); + + if (SrcInterval.containsOneValue()) { + assert(!SrcInterval.empty() && "Can't contain a value and be empty!"); + + // Get the first index of the first range. Though the interval may have + // multiple liveranges in it, we only check the first. + unsigned StartIdx = SrcInterval.begin()->start; + MachineInstr *SrcDefMI = getInstructionFromIndex(StartIdx); + + // Check to see if the vreg was defined by a copy instruction, and that + // the source was this physreg. + unsigned VRegSrcSrc, VRegSrcDest; + if (tii_->isMoveInstr(*SrcDefMI, VRegSrcSrc, VRegSrcDest) && + SrcReg == VRegSrcDest && VRegSrcSrc == DestReg) { + // Okay, now we know that the vreg was defined by a copy from this + // physreg. Find the value number being copied and use it as the value + // for this range. + const LiveRange *DefRange = interval.getLiveRangeContaining(StartIdx-1); + if (DefRange) { + LiveRange LR(start, end, DefRange->ValId); + interval.addRange(LR); + DEBUG(std::cerr << " +" << LR << '\n'); + return; } + } } - else - handleVirtualRegisterDef(mbb, mi, getOrCreateInterval(reg)); -} + } -unsigned LiveIntervals::getInstructionIndex(MachineInstr* instr) const -{ - Mi2IndexMap::const_iterator it = mi2iMap_.find(instr); - return (it == mi2iMap_.end() ? - std::numeric_limits::max() : - it->second); + + LiveRange LR(start, end, interval.getNextValue()); + interval.addRange(LR); + DEBUG(std::cerr << " +" << LR << '\n'); } -MachineInstr* LiveIntervals::getInstructionFromIndex(unsigned index) const -{ - index /= InstrSlots::NUM; // convert index to vector index - assert(index < i2miMap_.size() && - "index does not correspond to an instruction"); - return i2miMap_[index]; +void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, + MachineBasicBlock::iterator MI, + unsigned reg) { + if (MRegisterInfo::isVirtualRegister(reg)) + handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg)); + else if (allocatableRegs_[reg]) { + unsigned SrcReg = 0, DestReg = 0; + bool IsMove = tii_->isMoveInstr(*MI, SrcReg, DestReg); + + handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg), + SrcReg, DestReg); + for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) + handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS), + SrcReg, DestReg); + } } /// computeIntervals - computes the live intervals for virtual @@ -454,130 +589,105 @@ MachineInstr* LiveIntervals::getInstructionFromIndex(unsigned index) const /// which a variable is live void LiveIntervals::computeIntervals() { - DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); - DEBUG(std::cerr << "********** Function: " - << ((Value*)mf_->getFunction())->getName() << '\n'); - - for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); - I != E; ++I) { - MachineBasicBlock* mbb = I; - DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n"); - - for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); - mi != miEnd; ++mi) { - const TargetInstrDescriptor& tid = - tm_->getInstrInfo()->get(mi->getOpcode()); - DEBUG(std::cerr << getInstructionIndex(mi) << "\t"; - mi->print(std::cerr, tm_)); - - // handle implicit defs - for (const unsigned* id = tid.ImplicitDefs; *id; ++id) - handleRegisterDef(mbb, mi, *id); - - // handle explicit defs - for (int i = mi->getNumOperands() - 1; i >= 0; --i) { - MachineOperand& mop = mi->getOperand(i); - // handle register defs - build intervals - if (mop.isRegister() && mop.getReg() && mop.isDef()) - handleRegisterDef(mbb, mi, mop.getReg()); - } - } + DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); + DEBUG(std::cerr << "********** Function: " + << ((Value*)mf_->getFunction())->getName() << '\n'); + bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end(); + + for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); + I != E; ++I) { + MachineBasicBlock* mbb = I; + DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n"); + + MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); + if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; } + for (; mi != miEnd; ++mi) { + const TargetInstrDescriptor& tid = + tm_->getInstrInfo()->get(mi->getOpcode()); + DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi); + + // handle implicit defs + for (const unsigned* id = tid.ImplicitDefs; *id; ++id) + handleRegisterDef(mbb, mi, *id); + + // handle explicit defs + for (int i = mi->getNumOperands() - 1; i >= 0; --i) { + MachineOperand& mop = mi->getOperand(i); + // handle register defs - build intervals + if (mop.isRegister() && mop.getReg() && mop.isDef()) + handleRegisterDef(mbb, mi, mop.getReg()); + } } -} - -unsigned LiveIntervals::rep(unsigned reg) -{ - Reg2RegMap::iterator it = r2rMap_.find(reg); - if (it != r2rMap_.end()) - return it->second = rep(it->second); - return reg; + } } void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) { - DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); - const TargetInstrInfo& tii = *tm_->getInstrInfo(); - - for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end(); - mi != mie; ++mi) { - const TargetInstrDescriptor& tid = tii.get(mi->getOpcode()); - DEBUG(std::cerr << getInstructionIndex(mi) << '\t'; - mi->print(std::cerr, tm_);); - - // we only join virtual registers with allocatable - // physical registers since we do not have liveness information - // on not allocatable physical registers - unsigned regA, regB; - if (tii.isMoveInstr(*mi, regA, regB) && - (MRegisterInfo::isVirtualRegister(regA) || - lv_->getAllocatablePhysicalRegisters()[regA]) && - (MRegisterInfo::isVirtualRegister(regB) || - lv_->getAllocatablePhysicalRegisters()[regB])) { - - // get representative registers - regA = rep(regA); - regB = rep(regB); - - // if they are already joined we continue - if (regA == regB) - continue; - - Reg2IntervalMap::iterator r2iA = r2iMap_.find(regA); - assert(r2iA != r2iMap_.end() && - "Found unknown vreg in 'isMoveInstr' instruction"); - Reg2IntervalMap::iterator r2iB = r2iMap_.find(regB); - assert(r2iB != r2iMap_.end() && - "Found unknown vreg in 'isMoveInstr' instruction"); - - Intervals::iterator intA = r2iA->second; - Intervals::iterator intB = r2iB->second; - - // both A and B are virtual registers - if (MRegisterInfo::isVirtualRegister(intA->reg) && - MRegisterInfo::isVirtualRegister(intB->reg)) { - - const TargetRegisterClass *rcA, *rcB; - rcA = mf_->getSSARegMap()->getRegClass(intA->reg); - rcB = mf_->getSSARegMap()->getRegClass(intB->reg); - // if they are not of the same register class we continue - if (rcA != rcB) - continue; - - // if their intervals do not overlap we join them - if (!intB->overlaps(*intA)) { - intA->join(*intB); - r2iB->second = r2iA->second; - r2rMap_.insert(std::make_pair(intB->reg, intA->reg)); - intervals_.erase(intB); - } - } else if (MRegisterInfo::isPhysicalRegister(intA->reg) ^ - MRegisterInfo::isPhysicalRegister(intB->reg)) { - if (MRegisterInfo::isPhysicalRegister(intB->reg)) { - std::swap(regA, regB); - std::swap(intA, intB); - std::swap(r2iA, r2iB); - } - - assert(MRegisterInfo::isPhysicalRegister(intA->reg) && - MRegisterInfo::isVirtualRegister(intB->reg) && - "A must be physical and B must be virtual"); - - const TargetRegisterClass *rcA, *rcB; - rcA = mri_->getRegClass(intA->reg); - rcB = mf_->getSSARegMap()->getRegClass(intB->reg); - // if they are not of the same register class we continue - if (rcA != rcB) - continue; - - if (!intA->overlaps(*intB) && - !overlapsAliases(*intA, *intB)) { - intA->join(*intB); - r2iB->second = r2iA->second; - r2rMap_.insert(std::make_pair(intB->reg, intA->reg)); - intervals_.erase(intB); - } - } + DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); + + for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end(); + mi != mie; ++mi) { + DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi); + + // we only join virtual registers with allocatable + // physical registers since we do not have liveness information + // on not allocatable physical registers + unsigned regA, regB; + if (tii_->isMoveInstr(*mi, regA, regB) && + (MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) && + (MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) { + + // Get representative registers. + regA = rep(regA); + regB = rep(regB); + + // If they are already joined we continue. + if (regA == regB) + continue; + + // If they are both physical registers, we cannot join them. + if (MRegisterInfo::isPhysicalRegister(regA) && + MRegisterInfo::isPhysicalRegister(regB)) + continue; + + // If they are not of the same register class, we cannot join them. + if (differingRegisterClasses(regA, regB)) + continue; + + LiveInterval &IntA = getInterval(regA); + LiveInterval &IntB = getInterval(regB); + assert(IntA.reg == regA && IntB.reg == regB && + "Register mapping is horribly broken!"); + + DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": "); + + // If two intervals contain a single value and are joined by a copy, it + // does not matter if the intervals overlap, they can always be joined. + bool TriviallyJoinable = + IntA.containsOneValue() && IntB.containsOneValue(); + + unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi)); + if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) && + !overlapsAliases(&IntA, &IntB)) { + IntB.join(IntA, MIDefIdx); + + if (!MRegisterInfo::isPhysicalRegister(regA)) { + r2iMap_.erase(regA); + r2rMap_[regA] = regB; + } else { + // Otherwise merge the data structures the other way so we don't lose + // the physreg information. + r2rMap_[regB] = regA; + IntB.reg = regA; + IntA.swap(IntB); + r2iMap_.erase(regB); } + DEBUG(std::cerr << "Joined. Result = " << IntB << "\n"); + ++numJoins; + } else { + DEBUG(std::cerr << "Interference!\n"); + } } + } } namespace { @@ -587,8 +697,8 @@ namespace { typedef std::pair DepthMBBPair; bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { if (LHS.first > RHS.first) return true; // Deeper loops first - return LHS.first == RHS.first && - LHS.second->getNumber() < RHS.second->getNumber(); + return LHS.first == RHS.first && + LHS.second->getNumber() < RHS.second->getNumber(); } }; } @@ -614,192 +724,58 @@ void LiveIntervals::joinIntervals() { // Sort by loop depth. std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); - // Finally, join intervals in loop nest order. + // Finally, join intervals in loop nest order. for (unsigned i = 0, e = MBBs.size(); i != e; ++i) joinIntervalsInMachineBB(MBBs[i].second); } -} - -bool LiveIntervals::overlapsAliases(const LiveInterval& lhs, - const LiveInterval& rhs) const -{ - assert(MRegisterInfo::isPhysicalRegister(lhs.reg) && - "first interval must describe a physical register"); - - for (const unsigned* as = mri_->getAliasSet(lhs.reg); *as; ++as) { - Reg2IntervalMap::const_iterator r2i = r2iMap_.find(*as); - assert(r2i != r2iMap_.end() && "alias does not have interval?"); - if (rhs.overlaps(*r2i->second)) - return true; - } - - return false; -} - -LiveInterval& LiveIntervals::getOrCreateInterval(unsigned reg) -{ - Reg2IntervalMap::iterator r2iit = r2iMap_.lower_bound(reg); - if (r2iit == r2iMap_.end() || r2iit->first != reg) { - intervals_.push_back(LiveInterval(reg)); - r2iit = r2iMap_.insert(r2iit, std::make_pair(reg, --intervals_.end())); - } - return *r2iit->second; + DEBUG(std::cerr << "*** Register mapping ***\n"); + DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i) + if (r2rMap_[i]) + std::cerr << " reg " << i << " -> reg " << r2rMap_[i] << "\n"); } -LiveInterval::LiveInterval(unsigned r) - : reg(r), - weight((MRegisterInfo::isPhysicalRegister(r) ? HUGE_VAL : 0.0F)) -{ -} - -bool LiveInterval::spilled() const -{ - return (weight == HUGE_VAL && - MRegisterInfo::isVirtualRegister(reg)); -} - -// An example for liveAt(): -// -// this = [1,4), liveAt(0) will return false. The instruction defining -// this spans slots [0,3]. The interval belongs to an spilled -// definition of the variable it represents. This is because slot 1 is -// used (def slot) and spans up to slot 3 (store slot). -// -bool LiveInterval::liveAt(unsigned index) const -{ - Range dummy(index, index+1); - Ranges::const_iterator r = std::upper_bound(ranges.begin(), - ranges.end(), - dummy); - if (r == ranges.begin()) - return false; - - --r; - return index >= r->first && index < r->second; -} - -// An example for overlaps(): -// -// 0: A = ... -// 4: B = ... -// 8: C = A + B ;; last use of A -// -// The live intervals should look like: -// -// A = [3, 11) -// B = [7, x) -// C = [11, y) -// -// A->overlaps(C) should return false since we want to be able to join -// A and C. -bool LiveInterval::overlaps(const LiveInterval& other) const -{ - Ranges::const_iterator i = ranges.begin(); - Ranges::const_iterator ie = ranges.end(); - Ranges::const_iterator j = other.ranges.begin(); - Ranges::const_iterator je = other.ranges.end(); - if (i->first < j->first) { - i = std::upper_bound(i, ie, *j); - if (i != ranges.begin()) --i; - } - else if (j->first < i->first) { - j = std::upper_bound(j, je, *i); - if (j != other.ranges.begin()) --j; - } - - while (i != ie && j != je) { - if (i->first == j->first) { - return true; - } - else { - if (i->first > j->first) { - swap(i, j); - swap(ie, je); - } - assert(i->first < j->first); - - if (i->second > j->first) { - return true; - } - else { - ++i; - } - } - } +/// Return true if the two specified registers belong to different register +/// classes. The registers may be either phys or virt regs. +bool LiveIntervals::differingRegisterClasses(unsigned RegA, + unsigned RegB) const { - return false; -} + // Get the register classes for the first reg. + if (MRegisterInfo::isPhysicalRegister(RegA)) { + assert(MRegisterInfo::isVirtualRegister(RegB) && + "Shouldn't consider two physregs!"); + return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); + } -void LiveInterval::addRange(unsigned start, unsigned end) -{ - assert(start < end && "Invalid range to add!"); - DEBUG(std::cerr << " +[" << start << ',' << end << ")"); - //assert(start < end && "invalid range?"); - Range range = std::make_pair(start, end); - Ranges::iterator it = - ranges.insert(std::upper_bound(ranges.begin(), ranges.end(), range), - range); - - it = mergeRangesForward(it); - it = mergeRangesBackward(it); + // Compare against the regclass for the second reg. + const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); + if (MRegisterInfo::isVirtualRegister(RegB)) + return RegClass != mf_->getSSARegMap()->getRegClass(RegB); + else + return !RegClass->contains(RegB); } -void LiveInterval::join(const LiveInterval& other) -{ - DEBUG(std::cerr << "\t\tjoining " << *this << " with " << other); - Ranges::iterator cur = ranges.begin(); - - for (Ranges::const_iterator i = other.ranges.begin(), - e = other.ranges.end(); i != e; ++i) { - cur = ranges.insert(std::upper_bound(cur, ranges.end(), *i), *i); - cur = mergeRangesForward(cur); - cur = mergeRangesBackward(cur); - } - weight += other.weight; - ++numJoins; - DEBUG(std::cerr << ". Result = " << *this << "\n"); -} +bool LiveIntervals::overlapsAliases(const LiveInterval *LHS, + const LiveInterval *RHS) const { + if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) { + if (!MRegisterInfo::isPhysicalRegister(RHS->reg)) + return false; // vreg-vreg merge has no aliases! + std::swap(LHS, RHS); + } -LiveInterval::Ranges::iterator LiveInterval:: -mergeRangesForward(Ranges::iterator it) -{ - Ranges::iterator n; - while ((n = next(it)) != ranges.end()) { - if (n->first > it->second) - break; - it->second = std::max(it->second, n->second); - n = ranges.erase(n); - } - return it; -} + assert(MRegisterInfo::isPhysicalRegister(LHS->reg) && + MRegisterInfo::isVirtualRegister(RHS->reg) && + "first interval must describe a physical register"); -LiveInterval::Ranges::iterator LiveInterval:: -mergeRangesBackward(Ranges::iterator it) -{ - while (it != ranges.begin()) { - Ranges::iterator p = prior(it); - if (it->first > p->second) - break; - - it->first = std::min(it->first, p->first); - it->second = std::max(it->second, p->second); - it = ranges.erase(p); - } + for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS) + if (RHS->overlaps(getInterval(*AS))) + return true; - return it; + return false; } -std::ostream& llvm::operator<<(std::ostream& os, const LiveInterval& li) -{ - os << "%reg" << li.reg << ',' << li.weight; - if (li.empty()) - return os << "EMPTY"; - - os << " = "; - for (LiveInterval::Ranges::const_iterator - i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { - os << "[" << i->first << "," << i->second << ")"; - } - return os; +LiveInterval LiveIntervals::createInterval(unsigned reg) { + float Weight = MRegisterInfo::isPhysicalRegister(reg) ? + (float)HUGE_VAL :0.0F; + return LiveInterval(reg, Weight); }