X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLiveIntervalAnalysis.h;h=5b78342e281d4747e8407546da76edfcdcb4b6f7;hb=91ef460285021b5bf43b3850f0f8958a09b8939c;hp=ca2558628ebeac0c404dd2c477e4d9e889b516c2;hpb=843b160a2040b3ec4d3452678450afa11704c473;p=oota-llvm.git

diff --git a/lib/CodeGen/LiveIntervalAnalysis.h b/lib/CodeGen/LiveIntervalAnalysis.h
index ca2558628eb..5b78342e281 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.h
+++ b/lib/CodeGen/LiveIntervalAnalysis.h
@@ -28,6 +28,7 @@ namespace llvm {
 
     class LiveVariables;
     class MRegisterInfo;
+    class VirtRegMap;
 
     class LiveIntervals : public MachineFunctionPass
     {
@@ -42,13 +43,17 @@ namespace llvm {
 
             Interval(unsigned r);
 
+            bool empty() const { return ranges.empty(); }
+
+            bool spilled() const;
+
             unsigned start() const {
-                assert(!ranges.empty() && "empty interval for register");
+                assert(!empty() && "empty interval for register");
                 return ranges.front().first;
             }
 
             unsigned end() const {
-                assert(!ranges.empty() && "empty interval for register");
+                assert(!empty() && "empty interval for register");
                 return ranges.back().second;
             }
 
@@ -83,8 +88,6 @@ namespace llvm {
         };
 
         typedef std::list<Interval> Intervals;
-        typedef std::map<unsigned, unsigned> Reg2RegMap;
-        typedef std::vector<MachineBasicBlock*> MachineBasicBlockPtrs;
 
     private:
         MachineFunction* mf_;
@@ -106,24 +109,63 @@ namespace llvm {
         typedef std::map<unsigned, Intervals::iterator> Reg2IntervalMap;
         Reg2IntervalMap r2iMap_;
 
+        typedef std::map<unsigned, unsigned> Reg2RegMap;
         Reg2RegMap r2rMap_;
 
         Intervals intervals_;
 
     public:
+        struct InstrSlots
+        {
+            enum {
+                LOAD  = 0,
+                USE   = 1,
+                DEF   = 2,
+                STORE = 3,
+                NUM   = 4,
+            };
+        };
+
+        static unsigned getBaseIndex(unsigned index) {
+            return index - (index % InstrSlots::NUM);
+        }
+        static unsigned getBoundaryIndex(unsigned index) {
+            return getBaseIndex(index + InstrSlots::NUM - 1);
+        }
+        static unsigned getLoadIndex(unsigned index) {
+            return getBaseIndex(index) + InstrSlots::LOAD;
+        }
+        static unsigned getUseIndex(unsigned index) {
+            return getBaseIndex(index) + InstrSlots::USE;
+        }
+        static unsigned getDefIndex(unsigned index) {
+            return getBaseIndex(index) + InstrSlots::DEF;
+        }
+        static unsigned getStoreIndex(unsigned index) {
+            return getBaseIndex(index) + InstrSlots::STORE;
+        }
+
         virtual void getAnalysisUsage(AnalysisUsage &AU) const;
         virtual void releaseMemory();
 
         /// runOnMachineFunction - pass entry point
         virtual bool runOnMachineFunction(MachineFunction&);
 
+        Interval& getInterval(unsigned reg) {
+            assert(r2iMap_.count(reg)&& "Interval does not exist for register");
+            return *r2iMap_.find(reg)->second;
+        }
+
+        /// getInstructionIndex - returns the base index of instr
         unsigned getInstructionIndex(MachineInstr* instr) const;
 
+        /// getInstructionFromIndex - given an index in any slot of an
+        /// instruction return a pointer the instruction
         MachineInstr* getInstructionFromIndex(unsigned index) const;
 
         Intervals& getIntervals() { return intervals_; }
 
-        void updateSpilledInterval(Interval& i);
+        void updateSpilledInterval(Interval& i, VirtRegMap& vrm, int slot);
 
     private:
         /// computeIntervals - compute live intervals