X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLowerSubregs.cpp;h=7871ba9c17e493d3db4dae0ebd35633408cfb1fc;hb=1d5b84508173b93faf513032b3847152e6060791;hp=232dc061e5851dcd334a6892711f334723d5eaae;hpb=4499e495eabe8de7d595416a03c56af4688df507;p=oota-llvm.git

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 232dc061e58..7871ba9c17e 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -6,243 +6,216 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+//
+// This file defines a MachineFunction pass which runs after register
+// allocation that turns subreg insert/extract instructions into register
+// copies, as needed. This ensures correct codegen even if the coalescer
+// isn't able to remove all subreg instructions.
+//
+//===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "lowersubregs"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Debug.h"
-#include "llvm/Support/Compiler.h"
+#include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 namespace {
-  struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
-   : public MachineFunctionPass {
+  struct LowerSubregsInstructionPass : public MachineFunctionPass {
+  private:
+    const TargetRegisterInfo *TRI;
+    const TargetInstrInfo *TII;
+
+  public:
     static char ID; // Pass identification, replacement for typeid
-    LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
-    
+    LowerSubregsInstructionPass() : MachineFunctionPass(ID) {}
+
     const char *getPassName() const {
       return "Subregister lowering instruction pass";
     }
 
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      AU.setPreservesCFG();
+      AU.addPreservedID(MachineLoopInfoID);
+      AU.addPreservedID(MachineDominatorsID);
+      MachineFunctionPass::getAnalysisUsage(AU);
+    }
+
     /// runOnMachineFunction - pass entry point
     bool runOnMachineFunction(MachineFunction&);
-    
-    bool LowerExtract(MachineInstr *MI);
-    bool LowerInsert(MachineInstr *MI);
+
+  private:
+    bool LowerSubregToReg(MachineInstr *MI);
+    bool LowerCopy(MachineInstr *MI);
+
+    void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
+                          const TargetRegisterInfo *TRI);
+    void TransferImplicitDefs(MachineInstr *MI);
   };
 
   char LowerSubregsInstructionPass::ID = 0;
 }
 
-FunctionPass *llvm::createLowerSubregsPass() { 
-  return new LowerSubregsInstructionPass(); 
+FunctionPass *llvm::createLowerSubregsPass() {
+  return new LowerSubregsInstructionPass();
 }
 
-// Returns the Register Class of a physical register.
-static const TargetRegisterClass *getPhysicalRegisterRegClass(
-        const TargetRegisterInfo &TRI,
-        unsigned reg) {
-  assert(TargetRegisterInfo::isPhysicalRegister(reg) &&
-         "reg must be a physical register");
-  // Pick the register class of the right type that contains this physreg.
-  for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(),
-         E = TRI.regclass_end(); I != E; ++I)
-    if ((*I)->contains(reg))
-      return *I;
-  assert(false && "Couldn't find the register class");
-  return 0;
+/// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
+/// and the lowered replacement instructions immediately precede it.
+/// Mark the replacement instructions with the dead flag.
+void
+LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
+                                              unsigned DstReg,
+                                              const TargetRegisterInfo *TRI) {
+  for (MachineBasicBlock::iterator MII =
+        prior(MachineBasicBlock::iterator(MI)); ; --MII) {
+    if (MII->addRegisterDead(DstReg, TRI))
+      break;
+    assert(MII != MI->getParent()->begin() &&
+           "copyPhysReg output doesn't reference destination register!");
+  }
 }
 
-bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
-   MachineBasicBlock *MBB = MI->getParent();
-   MachineFunction &MF = *MBB->getParent();
-   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
-   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
-   
-   assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
-          MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
-          MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
-
-   unsigned SuperReg = MI->getOperand(1).getReg();
-   unsigned SubIdx = MI->getOperand(2).getImm();
-
-   assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
-          "Extract supperg source must be a physical register");
-   unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
-   unsigned DstReg = MI->getOperand(0).getReg();
-
-   DOUT << "subreg: CONVERTING: " << *MI;
-
-   if (SrcReg != DstReg) {
-     const TargetRegisterClass *TRC = 0;
-     if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
-       TRC = getPhysicalRegisterRegClass(TRI, DstReg);
-     } else {
-       TRC = MF.getRegInfo().getRegClass(DstReg);
-     }
-     assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) &&
-             "Extract subreg and Dst must be of same register class");
-
-     TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
-     MachineBasicBlock::iterator dMI = MI;
-     DOUT << "subreg: " << *(--dMI);
-   }
-
-   DOUT << "\n";
-   MBB->remove(MI);
-   return true;
+/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
+/// replacement instructions immediately precede it.  Copy any implicit-def
+/// operands from MI to the replacement instruction.
+void
+LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
+  MachineBasicBlock::iterator CopyMI = MI;
+  --CopyMI;
+
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
+      continue;
+    CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
+  }
 }
 
-
-bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
+bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
   MachineBasicBlock *MBB = MI->getParent();
-  MachineFunction &MF = *MBB->getParent();
-  const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); 
-  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
-  unsigned DstReg = 0;
-  unsigned SrcReg = 0;
-  unsigned InsReg = 0;
-  unsigned SubIdx = 0;
-
-  // If only have 3 operands, then the source superreg is undef
-  // and we can supress the copy from the undef value
-  if (MI->getNumOperands() == 3) {
-    assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
-           (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
-            MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
-    DstReg = MI->getOperand(0).getReg();
-    SrcReg = DstReg;
-    InsReg = MI->getOperand(1).getReg();
-    SubIdx = MI->getOperand(2).getImm();
-  } else if (MI->getNumOperands() == 4) {
-    assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
-           (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
-           (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
-            MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
-    DstReg = MI->getOperand(0).getReg();
-    SrcReg = MI->getOperand(1).getReg();
-    InsReg = MI->getOperand(2).getReg();
-    SubIdx = MI->getOperand(3).getImm();     
-  } else 
-    assert(0 && "Malformed extract_subreg");
-
-  assert(SubIdx != 0 && "Invalid index for extract_subreg");
-  unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
-
-  assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
-         "Insert superreg source must be in a physical register");
+  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
+         MI->getOperand(1).isImm() &&
+         (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
+          MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
+
+  unsigned DstReg  = MI->getOperand(0).getReg();
+  unsigned InsReg  = MI->getOperand(2).getReg();
+  assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
+  unsigned SubIdx  = MI->getOperand(3).getImm();
+
+  assert(SubIdx != 0 && "Invalid index for insert_subreg");
+  unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
+
   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
          "Insert destination must be in a physical register");
   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
          "Inserted value must be in a physical register");
 
-  DOUT << "subreg: CONVERTING: " << *MI;
-       
-  // If the inserted register is already allocated into a subregister
-  // of the destination, we copy the subreg into the source
-  // However, this is only safe if the insert instruction is the kill
-  // of the source register
-  bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg);
-  if (revCopyOrder && InsReg != DstSubReg) {
-    if (MI->getOperand(1).isKill()) {
-      DstSubReg = TRI.getSubReg(SrcReg, SubIdx);
-      // Insert sub-register copy
-      const TargetRegisterClass *TRC1 = 0;
-      if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
-        TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
-      } else {
-        TRC1 = MF.getRegInfo().getRegClass(InsReg);
-      }
-      TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
-
-#ifndef NDEBUG
-      MachineBasicBlock::iterator dMI = MI;
-      DOUT << "subreg: " << *(--dMI);
-#endif
-    } else {
-      assert(0 && "Don't know how to convert this insert");
+  DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
+
+  if (DstSubReg == InsReg) {
+    // No need to insert an identify copy instruction.
+    // Watch out for case like this:
+    // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
+    // We must leave %RAX live.
+    if (DstReg != InsReg) {
+      MI->setDesc(TII->get(TargetOpcode::KILL));
+      MI->RemoveOperand(3);     // SubIdx
+      MI->RemoveOperand(1);     // Imm
+      DEBUG(dbgs() << "subreg: replace by: " << *MI);
+      return true;
     }
+    DEBUG(dbgs() << "subreg: eliminated!");
+  } else {
+    TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
+                     MI->getOperand(2).isKill());
+    // Transfer the kill/dead flags, if needed.
+    if (MI->getOperand(0).isDead())
+      TransferDeadFlag(MI, DstSubReg, TRI);
+    DEBUG({
+        MachineBasicBlock::iterator dMI = MI;
+        dbgs() << "subreg: " << *(--dMI);
+      });
   }
-#ifndef NDEBUG
-  if (InsReg == DstSubReg) {
-     DOUT << "subreg: Eliminated subreg copy\n";
-  }
-#endif
-
-  if (SrcReg != DstReg) {
-    // Insert super-register copy
-    const TargetRegisterClass *TRC0 = 0;
-    if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
-      TRC0 = getPhysicalRegisterRegClass(TRI, DstReg);
-    } else {
-      TRC0 = MF.getRegInfo().getRegClass(DstReg);
-    }
-    assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) &&
-            "Insert superreg and Dst must be of same register class");
 
-    TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
+  DEBUG(dbgs() << '\n');
+  MBB->erase(MI);
+  return true;
+}
 
-#ifndef NDEBUG
-    MachineBasicBlock::iterator dMI = MI;
-    DOUT << "subreg: " << *(--dMI);
-#endif
-  }
-  
-#ifndef NDEBUG
-  if (SrcReg == DstReg) {
-     DOUT << "subreg: Eliminated superreg copy\n";
-  }
-#endif
-
-  if (!revCopyOrder && InsReg != DstSubReg) {
-    // Insert sub-register copy
-    const TargetRegisterClass *TRC1 = 0;
-    if (TargetRegisterInfo::isPhysicalRegister(InsReg)) {
-      TRC1 = getPhysicalRegisterRegClass(TRI, InsReg);
-    } else {
-      TRC1 = MF.getRegInfo().getRegClass(InsReg);
+bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
+  MachineOperand &DstMO = MI->getOperand(0);
+  MachineOperand &SrcMO = MI->getOperand(1);
+
+  if (SrcMO.getReg() == DstMO.getReg()) {
+    DEBUG(dbgs() << "identity copy: " << *MI);
+    // No need to insert an identity copy instruction, but replace with a KILL
+    // if liveness is changed.
+    if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
+      // We must make sure the super-register gets killed. Replace the
+      // instruction with KILL.
+      MI->setDesc(TII->get(TargetOpcode::KILL));
+      DEBUG(dbgs() << "replaced by:   " << *MI);
+      return true;
     }
-    TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
-
-#ifndef NDEBUG
-    MachineBasicBlock::iterator dMI = MI;
-    DOUT << "subreg: " << *(--dMI);
-#endif
+    // Vanilla identity copy.
+    MI->eraseFromParent();
+    return true;
   }
 
-  DOUT << "\n";
-  MBB->remove(MI);
-  return true;                    
+  DEBUG(dbgs() << "real copy:   " << *MI);
+  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
+                   DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
+
+  if (DstMO.isDead())
+    TransferDeadFlag(MI, DstMO.getReg(), TRI);
+  if (MI->getNumOperands() > 2)
+    TransferImplicitDefs(MI);
+  DEBUG({
+    MachineBasicBlock::iterator dMI = MI;
+    dbgs() << "replaced by: " << *(--dMI);
+  });
+  MI->eraseFromParent();
+  return true;
 }
 
 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 /// copies.
 ///
 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
-  DOUT << "Machine Function\n";
-  
-  bool MadeChange = false;
+  DEBUG(dbgs() << "Machine Function\n"
+               << "********** LOWERING SUBREG INSTRS **********\n"
+               << "********** Function: "
+               << MF.getFunction()->getName() << '\n');
+  TRI = MF.getTarget().getRegisterInfo();
+  TII = MF.getTarget().getInstrInfo();
 
-  DOUT << "********** LOWERING SUBREG INSTRS **********\n";
-  DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
+  bool MadeChange = false;
 
   for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
        mbbi != mbbe; ++mbbi) {
     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
          mi != me;) {
-      MachineInstr *MI = mi++;
-           
-      if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
-        MadeChange |= LowerExtract(MI);
-      } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
-        MadeChange |= LowerInsert(MI);
+      MachineBasicBlock::iterator nmi = llvm::next(mi);
+      MachineInstr *MI = mi;
+      assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
+      assert(MI->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
+             "EXTRACT_SUBREG should no longer appear");
+      if (MI->isSubregToReg()) {
+        MadeChange |= LowerSubregToReg(MI);
+      } else if (MI->isCopy()) {
+        MadeChange |= LowerCopy(MI);
       }
+      mi = nmi;
     }
   }