X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLowerSubregs.cpp;h=b0348a5b753c185aeb21e888d99a4d60c93b0c25;hb=63e6a488cb6c29983415221719d05fbf99e00193;hp=9c23a5ac15523886a8feaa4eadc465d7ff4daebc;hpb=ded2e3b0d02998b3bb99b5089d05fca1e0097868;p=oota-llvm.git diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index 9c23a5ac155..b0348a5b753 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -25,13 +25,16 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Debug.h" -#include "llvm/Support/Compiler.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { - struct VISIBILITY_HIDDEN LowerSubregsInstructionPass - : public MachineFunctionPass { + struct LowerSubregsInstructionPass : public MachineFunctionPass { + private: + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; + + public: static char ID; // Pass identification, replacement for typeid LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {} @@ -48,15 +51,17 @@ namespace { /// runOnMachineFunction - pass entry point bool runOnMachineFunction(MachineFunction&); - + + private: bool LowerExtract(MachineInstr *MI); bool LowerInsert(MachineInstr *MI); bool LowerSubregToReg(MachineInstr *MI); void TransferDeadFlag(MachineInstr *MI, unsigned DstReg, - const TargetRegisterInfo &TRI); + const TargetRegisterInfo *TRI); void TransferKillFlag(MachineInstr *MI, unsigned SrcReg, - const TargetRegisterInfo &TRI); + const TargetRegisterInfo *TRI, + bool AddIfNotFound = false); }; char LowerSubregsInstructionPass::ID = 0; @@ -72,10 +77,10 @@ FunctionPass *llvm::createLowerSubregsPass() { void LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI, unsigned DstReg, - const TargetRegisterInfo &TRI) { + const TargetRegisterInfo *TRI) { for (MachineBasicBlock::iterator MII = prior(MachineBasicBlock::iterator(MI)); ; --MII) { - if (MII->addRegisterDead(DstReg, &TRI)) + if (MII->addRegisterDead(DstReg, TRI)) break; assert(MII != MI->getParent()->begin() && "copyRegToReg output doesn't reference destination register!"); @@ -88,10 +93,11 @@ LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI, void LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI, unsigned SrcReg, - const TargetRegisterInfo &TRI) { + const TargetRegisterInfo *TRI, + bool AddIfNotFound) { for (MachineBasicBlock::iterator MII = prior(MachineBasicBlock::iterator(MI)); ; --MII) { - if (MII->addRegisterKilled(SrcReg, &TRI)) + if (MII->addRegisterKilled(SrcReg, TRI, AddIfNotFound)) break; assert(MII != MI->getParent()->begin() && "copyRegToReg output doesn't reference source register!"); @@ -100,9 +106,6 @@ LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI, bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); - MachineFunction &MF = *MBB->getParent(); - const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && MI->getOperand(1).isReg() && MI->getOperand(1).isUse() && @@ -111,55 +114,54 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { unsigned DstReg = MI->getOperand(0).getReg(); unsigned SuperReg = MI->getOperand(1).getReg(); unsigned SubIdx = MI->getOperand(2).getImm(); - unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx); + unsigned SrcReg = TRI->getSubReg(SuperReg, SubIdx); assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) && "Extract supperg source must be a physical register"); assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && "Extract destination must be in a physical register"); + assert(SrcReg && "invalid subregister index for register"); - DOUT << "subreg: CONVERTING: " << *MI; + DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); if (SrcReg == DstReg) { // No need to insert an identity copy instruction. if (MI->getOperand(1).isKill()) { - // We must make sure the super-register gets killed.Replace the - // instruction with IMPLICIT_DEF. - MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF)); + // We must make sure the super-register gets killed. Replace the + // instruction with KILL. + MI->setDesc(TII->get(TargetOpcode::KILL)); MI->RemoveOperand(2); // SubIdx - DOUT << "subreg: replace by: " << *MI; + DEBUG(dbgs() << "subreg: replace by: " << *MI); return true; } - DOUT << "subreg: eliminated!"; + + DEBUG(dbgs() << "subreg: eliminated!"); } else { // Insert copy - const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg); - const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg); - bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS); + const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg); + const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg); + bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS, + MI->getDebugLoc()); (void)Emitted; assert(Emitted && "Subreg and Dst must be of compatible register class"); // Transfer the kill/dead flags, if needed. if (MI->getOperand(0).isDead()) TransferDeadFlag(MI, DstReg, TRI); if (MI->getOperand(1).isKill()) - TransferKillFlag(MI, SrcReg, TRI); - -#ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); -#endif + TransferKillFlag(MI, SuperReg, TRI, true); + DEBUG({ + MachineBasicBlock::iterator dMI = MI; + dbgs() << "subreg: " << *(--dMI); + }); } - DOUT << "\n"; + DEBUG(dbgs() << '\n'); MBB->erase(MI); return true; } bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); - MachineFunction &MF = *MBB->getParent(); - const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && MI->getOperand(1).isImm() && (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && @@ -171,14 +173,14 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { unsigned SubIdx = MI->getOperand(3).getImm(); assert(SubIdx != 0 && "Invalid index for insert_subreg"); - unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); + unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && "Insert destination must be in a physical register"); assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && "Inserted value must be in a physical register"); - DOUT << "subreg: CONVERTING: " << *MI; + DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); if (DstSubReg == InsReg && InsSIdx == 0) { // No need to insert an identify copy instruction. @@ -187,34 +189,33 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { // %RAX = SUBREG_TO_REG 0, %EAX:3, 3 // The first def is defining RAX, not EAX so the top bits were not // zero extended. - DOUT << "subreg: eliminated!"; + DEBUG(dbgs() << "subreg: eliminated!"); } else { // Insert sub-register copy - const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); - const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg); + const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg); + bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1, + MI->getDebugLoc()); + (void)Emitted; + assert(Emitted && "Subreg and Dst must be of compatible register class"); // Transfer the kill/dead flags, if needed. if (MI->getOperand(0).isDead()) TransferDeadFlag(MI, DstSubReg, TRI); if (MI->getOperand(2).isKill()) TransferKillFlag(MI, InsReg, TRI); - -#ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); -#endif + DEBUG({ + MachineBasicBlock::iterator dMI = MI; + dbgs() << "subreg: " << *(--dMI); + }); } - DOUT << "\n"; + DEBUG(dbgs() << '\n'); MBB->erase(MI); - return true; + return true; } bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); - MachineFunction &MF = *MBB->getParent(); - const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) && (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && @@ -229,86 +230,101 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?"); assert(SubIdx != 0 && "Invalid index for insert_subreg"); - unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); + unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); assert(DstSubReg && "invalid subregister index for register"); assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && "Insert superreg source must be in a physical register"); assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && "Inserted value must be in a physical register"); - DOUT << "subreg: CONVERTING: " << *MI; + DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); if (DstSubReg == InsReg) { // No need to insert an identity copy instruction. If the SrcReg was - // , we need to make sure it is alive by inserting an IMPLICIT_DEF + // , we need to make sure it is alive by inserting a KILL if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) { - BuildMI(*MBB, MI, MI->getDebugLoc(), - TII.get(TargetInstrInfo::IMPLICIT_DEF), DstReg) - .addReg(InsReg, RegState::ImplicitKill); + MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), + TII->get(TargetOpcode::KILL), DstReg); + if (MI->getOperand(2).isUndef()) + MIB.addReg(InsReg, RegState::Undef); + else + MIB.addReg(InsReg, RegState::Kill); } else { - DOUT << "subreg: eliminated!\n"; + DEBUG(dbgs() << "subreg: eliminated!\n"); MBB->erase(MI); return true; } } else { // Insert sub-register copy - const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); - const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg); + const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg); + if (MI->getOperand(2).isUndef()) + // If the source register being inserted is undef, then this becomes a + // KILL. + BuildMI(*MBB, MI, MI->getDebugLoc(), + TII->get(TargetOpcode::KILL), DstSubReg); + else { + bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1, + MI->getDebugLoc()); + (void)Emitted; + assert(Emitted && "Subreg and Dst must be of compatible register class"); + } MachineBasicBlock::iterator CopyMI = MI; --CopyMI; + // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg. + if (!MI->getOperand(1).isUndef()) + CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true)); + // Transfer the kill/dead flags, if needed. if (MI->getOperand(0).isDead()) { TransferDeadFlag(MI, DstSubReg, TRI); - // Also add a SrcReg of the super register. - CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true)); - } else if (MI->getOperand(1).isUndef()) { - // If SrcReg was marked we must make sure it is alive after this - // replacement. Add a SrcReg operand. + } else { + // Make sure the full DstReg is live after this replacement. CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true)); } // Make sure the inserted register gets killed - if (MI->getOperand(2).isKill()) + if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef()) TransferKillFlag(MI, InsReg, TRI); } -#ifndef NDEBUG - MachineBasicBlock::iterator dMI = MI; - DOUT << "subreg: " << *(--dMI); -#endif + DEBUG({ + MachineBasicBlock::iterator dMI = MI; + dbgs() << "subreg: " << *(--dMI) << "\n"; + }); - DOUT << "\n"; MBB->erase(MI); - return true; + return true; } /// runOnMachineFunction - Reduce subregister inserts and extracts to register /// copies. /// bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) { - DOUT << "Machine Function\n"; - - bool MadeChange = false; + DEBUG(dbgs() << "Machine Function\n" + << "********** LOWERING SUBREG INSTRS **********\n" + << "********** Function: " + << MF.getFunction()->getName() << '\n'); + TRI = MF.getTarget().getRegisterInfo(); + TII = MF.getTarget().getInstrInfo(); - DOUT << "********** LOWERING SUBREG INSTRS **********\n"; - DEBUG(errs() << "********** Function: " - << MF.getFunction()->getName() << '\n'); + bool MadeChange = false; for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); mbbi != mbbe; ++mbbi) { for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); mi != me;) { - MachineInstr *MI = mi++; - - if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { + MachineBasicBlock::iterator nmi = llvm::next(mi); + MachineInstr *MI = mi; + if (MI->isExtractSubreg()) { MadeChange |= LowerExtract(MI); - } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) { + } else if (MI->isInsertSubreg()) { MadeChange |= LowerInsert(MI); - } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) { + } else if (MI->isSubregToReg()) { MadeChange |= LowerSubregToReg(MI); } + mi = nmi; } }