X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMachineCSE.cpp;h=35ba7ff35e6f201a670e11bc2adf2812b86d075d;hb=bf329b3414bbc24efb6d44952a7cbf66c83bcca1;hp=80982bca8ce8dd1fba768c36aac7acdfa93e4db0;hpb=b961a26cec1e7b7b96edc200ef8d09fc12c11088;p=oota-llvm.git

diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp
index 80982bca8ce..35ba7ff35e6 100644
--- a/lib/CodeGen/MachineCSE.cpp
+++ b/lib/CodeGen/MachineCSE.cpp
@@ -133,16 +133,26 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
       continue;
     if (DefMI->getOperand(0).getSubReg())
       continue;
-    unsigned SrcSubReg = DefMI->getOperand(1).getSubReg();
+    // FIXME: We should trivially coalesce subregister copies to expose CSE
+    // opportunities on instructions with truncated operands (see
+    // cse-add-with-overflow.ll). This can be done here as follows:
+    // if (SrcSubReg)
+    //  RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
+    //                                     SrcSubReg);
+    // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+    //
+    // The 2-addr pass has been updated to handle coalesced subregs. However,
+    // some machine-specific code still can't handle it.
+    // To handle it properly we also need a way find a constrained subregister
+    // class given a super-reg class and subreg index.
+    if (DefMI->getOperand(1).getSubReg())
+      continue;
     const TargetRegisterClass *RC = MRI->getRegClass(Reg);
-    if (SrcSubReg)
-      RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
-                                         SrcSubReg);
     if (!MRI->constrainRegClass(SrcReg, RC))
       continue;
     DEBUG(dbgs() << "Coalescing: " << *DefMI);
     DEBUG(dbgs() << "***     to: " << *MI);
-    MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
+    MO.setReg(SrcReg);
     MRI->clearKillFlags(SrcReg);
     DefMI->eraseFromParent();
     ++NumCoalesces;