X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMachineInstr.cpp;h=3dce6fc85deb8f62e6b99b36625c8c107fa91d77;hb=da8d96d1a1769d0614c46d9880ac3c21cbc8e74c;hp=d09813272de0ea834c2b9a92636e3e85028bb83b;hpb=45c171ee25619f6650e90fa5e3102d9969fd82b3;p=oota-llvm.git diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index d09813272de..3dce6fc85de 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -1,332 +1,489 @@ -// $Id$ -//*************************************************************************** -// File: -// MachineInstr.cpp +//===-- MachineInstr.cpp --------------------------------------------------===// // -// Purpose: -// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. // -// Strategy: -// -// History: -// 7/2/01 - Vikram Adve - Created -//**************************************************************************/ +//===----------------------------------------------------------------------===// +// +// Methods common to all machine instructions. +// +// FIXME: Now that MachineInstrs have parent pointers, they should always +// print themselves using their MachineFunction's TargetMachine. +// +//===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/ConstPoolVals.h" -#include "llvm/Instruction.h" -#include - -//************************ Class Implementations **************************/ - -// Constructor for instructions with fixed #operands (nearly all) -MachineInstr::MachineInstr(MachineOpCode _opCode, - OpCodeMask _opCodeMask) - : opCode(_opCode), - opCodeMask(_opCodeMask), - operands(TargetInstrDescriptors[_opCode].numOperands) -{ - assert(TargetInstrDescriptors[_opCode].numOperands >= 0); +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/Value.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Support/LeakDetector.h" +#include + +using namespace llvm; + +// Global variable holding an array of descriptors for machine instructions. +// The actual object needs to be created separately for each target machine. +// This variable is initialized and reset by class TargetInstrInfo. +// +// FIXME: This should be a property of the target so that more than one target +// at a time can be active... +// +namespace llvm { + extern const TargetInstrDescriptor *TargetInstrDescriptors; } // Constructor for instructions with variable #operands -MachineInstr::MachineInstr(MachineOpCode _opCode, - unsigned numOperands, - OpCodeMask _opCodeMask) - : opCode(_opCode), - opCodeMask(_opCodeMask), - operands(numOperands) -{ +MachineInstr::MachineInstr(short opcode, unsigned numOperands) + : Opcode(opcode), + numImplicitRefs(0), + operands(numOperands, MachineOperand()), + parent(0) { + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); } -void -MachineInstr::SetMachineOperand(unsigned int i, - MachineOperand::MachineOperandType operandType, - Value* _val, bool isdef=false) -{ - assert(i < operands.size()); - operands[i].Initialize(operandType, _val); - operands[i].isDef = isdef; +/// MachineInstr ctor - This constructor only does a _reserve_ of the operands, +/// not a resize for them. It is expected that if you use this that you call +/// add* methods below to fill up the operands, instead of the Set methods. +/// Eventually, the "resizing" ctors will be phased out. +/// +MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) + : Opcode(opcode), numImplicitRefs(0), parent(0) { + operands.reserve(numOperands); + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); } -void -MachineInstr::SetMachineOperand(unsigned int i, - MachineOperand::MachineOperandType operandType, - int64_t intValue, bool isdef=false) -{ - assert(i < operands.size()); - operands[i].InitializeConst(operandType, intValue); - operands[i].isDef = isdef; +/// MachineInstr ctor - Work exactly the same as the ctor above, except that the +/// MachineInstr is created and added to the end of the specified basic block. +/// +MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, + unsigned numOperands) + : Opcode(opcode), numImplicitRefs(0), parent(0) { + assert(MBB && "Cannot use inserting ctor with null basic block!"); + operands.reserve(numOperands); + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); + MBB->push_back(this); // Add instruction to end of basic block! } -void -MachineInstr::SetMachineOperand(unsigned int i, - unsigned int regNum, bool isdef=false) -{ - assert(i < operands.size()); - operands[i].InitializeReg(regNum); - operands[i].isDef = isdef; +/// MachineInstr ctor - Copies MachineInstr arg exactly +/// +MachineInstr::MachineInstr(const MachineInstr &MI) { + Opcode = MI.getOpcode(); + numImplicitRefs = MI.getNumImplicitRefs(); + operands.reserve(MI.getNumOperands()); + + // Add operands + for (unsigned i = 0; i < MI.getNumOperands(); ++i) + operands.push_back(MachineOperand(MI.getOperand(i))); + + // Set parent, next, and prev to null + parent = 0; + prev = 0; + next = 0; } -void -MachineInstr::dump(unsigned int indent) -{ - for (unsigned i=0; i < indent; i++) - cout << " "; - - cout << *this; + +MachineInstr::~MachineInstr() { + LeakDetector::removeGarbageObject(this); } -ostream& -operator<< (ostream& os, const MachineInstr& minstr) -{ - os << TargetInstrDescriptors[minstr.opCode].opCodeString; - - for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) - os << "\t" << minstr.getOperand(i); - -#undef DEBUG_VAL_OP_ITERATOR -#ifdef DEBUG_VAL_OP_ITERATOR - os << endl << "\tValue operands are: "; - for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo) - { - const Value* val = *vo; - os << val << (vo.isDef()? "(def), " : ", "); - } - os << endl; -#endif - - return os; +/// clone - Create a copy of 'this' instruction that is identical in all ways +/// except the following: the new instruction has no parent and it has no name +/// +MachineInstr* MachineInstr::clone() const { + return new MachineInstr(*this); } -ostream& -operator<< (ostream& os, const MachineOperand& mop) -{ - strstream regInfo; - if (mop.opType == MachineOperand::MO_VirtualRegister) - regInfo << "(val " << mop.value << ")" << ends; - else if (mop.opType == MachineOperand::MO_MachineRegister) - regInfo << "(" << mop.regNum << ")" << ends; - else if (mop.opType == MachineOperand::MO_CCRegister) - regInfo << "(val " << mop.value << ")" << ends; - - switch(mop.opType) - { - case MachineOperand::MO_VirtualRegister: - case MachineOperand::MO_MachineRegister: - os << "%reg" << regInfo.str(); - free(regInfo.str()); - break; - - case MachineOperand::MO_CCRegister: - os << "%ccreg" << regInfo.str(); - free(regInfo.str()); - break; - - case MachineOperand::MO_SignExtendedImmed: - os << mop.immedVal; - break; - - case MachineOperand::MO_UnextendedImmed: - os << mop.immedVal; - break; - - case MachineOperand::MO_PCRelativeDisp: - os << "%disp(label " << mop.value << ")"; - break; - - default: - assert(0 && "Unrecognized operand type"); - break; - } +/// OperandComplete - Return true if it's illegal to add a new operand +/// +bool MachineInstr::OperandsComplete() const { + int NumOperands = TargetInstrDescriptors[Opcode].numOperands; + if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) + return true; // Broken: we have all the operands of this instruction! + return false; +} - return os; +/// replace - Support for replacing opcode and operands of a MachineInstr in +/// place. This only resets the size of the operand vector and initializes it. +/// The new operands must be set explicitly later. +/// +void MachineInstr::replace(short opcode, unsigned numOperands) { + assert(getNumImplicitRefs() == 0 && + "This is probably broken because implicit refs are going to be lost."); + Opcode = opcode; + operands.clear(); + operands.resize(numOperands, MachineOperand()); } +void MachineInstr::SetMachineOperandVal(unsigned i, + MachineOperand::MachineOperandType opTy, + Value* V) { + assert(i < operands.size()); // may be explicit or implicit op + operands[i].opType = opTy; + operands[i].contents.value = V; + operands[i].extra.regNum = -1; +} -//--------------------------------------------------------------------------- -// Target-independent utility routines for creating machine instructions -//--------------------------------------------------------------------------- +void +MachineInstr::SetMachineOperandConst(unsigned i, + MachineOperand::MachineOperandType opTy, + int intValue) { + assert(i < getNumOperands()); // must be explicit op + assert(TargetInstrDescriptors[Opcode].resultPos != (int) i && + "immed. constant cannot be defined"); + operands[i].opType = opTy; + operands[i].contents.value = NULL; + operands[i].contents.immedVal = intValue; + operands[i].extra.regNum = -1; + operands[i].flags = 0; +} -//------------------------------------------------------------------------ -// Function Set2OperandsFromInstr -// Function Set3OperandsFromInstr -// -// For the common case of 2- and 3-operand arithmetic/logical instructions, -// set the m/c instr. operands directly from the VM instruction's operands. -// Check whether the first or second operand is 0 and can use a dedicated "0" register. -// Check whether the second operand should use an immediate field or register. -// (First and third operands are never immediates for such instructions.) -// -// Arguments: -// canDiscardResult: Specifies that the result operand can be discarded -// by using the dedicated "0" -// -// op1position, op2position and resultPosition: Specify in which position -// in the machine instruction the 3 operands (arg1, arg2 -// and result) should go. -// -// RETURN VALUE: unsigned int flags, where -// flags & 0x01 => operand 1 is constant and needs a register -// flags & 0x02 => operand 2 is constant and needs a register -//------------------------------------------------------------------------ +void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { + assert(i < getNumOperands()); // must be explicit op -void -Set2OperandsFromInstr(MachineInstr* minstr, - InstructionNode* vmInstrNode, - const TargetMachine& target, - bool canDiscardResult, - int op1Position, - int resultPosition) -{ - Set3OperandsFromInstr(minstr, vmInstrNode, target, - canDiscardResult, op1Position, - /*op2Position*/ -1, resultPosition); + operands[i].opType = MachineOperand::MO_MachineRegister; + operands[i].contents.value = NULL; + operands[i].extra.regNum = regNum; +} + +// Used only by the SPARC back-end. +void MachineInstr::SetRegForOperand(unsigned i, int regNum) { + assert(i < getNumOperands()); // must be explicit op + operands[i].setRegForValue(regNum); +} + +// Used only by the SPARC back-end. +void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) { + getImplicitOp(i).setRegForValue(regNum); } -#undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS -#ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS +/// substituteValue - Substitute all occurrences of Value* oldVal with newVal +/// in all operands and all implicit refs. If defsOnly == true, substitute defs +/// only. +/// +/// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865, +/// or make it a static function in that file. +/// unsigned -Set3OperandsFromInstrJUNK(MachineInstr* minstr, - InstructionNode* vmInstrNode, - const TargetMachine& target, - bool canDiscardResult, - int op1Position, - int op2Position, - int resultPosition) +MachineInstr::substituteValue(const Value* oldVal, Value* newVal, + bool defsOnly, bool notDefsAndUses, + bool& someArgsWereIgnored) { - assert(op1Position >= 0); - assert(resultPosition >= 0); + assert((!defsOnly || !notDefsAndUses) && + "notDefsAndUses is irrelevant if defsOnly == true."); - unsigned returnFlags = 0x0; + unsigned numSubst = 0; + + // Substitute operands + for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) + if (*O == oldVal) + if (!defsOnly || + notDefsAndUses && (O.isDef() && !O.isUse()) || + !notDefsAndUses && O.isDef()) + { + O.getMachineOperand().contents.value = newVal; + ++numSubst; + } else + someArgsWereIgnored = true; + + // Substitute implicit refs + for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i) + if (getImplicitRef(i) == oldVal) { + MachineOperand Op = getImplicitOp(i); + if (!defsOnly || + notDefsAndUses && (Op.isDef() && !Op.isUse()) || + !notDefsAndUses && Op.isDef()) + { + Op.contents.value = newVal; + ++numSubst; + } else + someArgsWereIgnored = true; + } + return numSubst; +} + +void MachineInstr::dump() const { + std::cerr << " " << *this; +} + +static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { + os << "(val "; + os << (void*) val; // print address always + if (val && val->hasName()) + os << " " << val->getName(); // print name also, if available + os << ")"; + return os; +} + +static inline void OutputReg(std::ostream &os, unsigned RegNo, + const MRegisterInfo *MRI = 0) { + if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { + if (MRI) + os << "%" << MRI->get(RegNo).Name; + else + os << "%mreg(" << RegNo << ")"; + } else + os << "%reg" << RegNo; +} + +static void print(const MachineOperand &MO, std::ostream &OS, + const TargetMachine *TM) { + const MRegisterInfo *MRI = 0; - // Check if operand 1 is 0 and if so, try to use the register that gives 0, if any. - Value* op1Value = vmInstrNode->leftChild()->getValue(); - bool isValidConstant; - int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant); - if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0) - minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum); + if (TM) MRI = TM->getRegisterInfo(); + + bool CloseParen = true; + if (MO.isHiBits32()) + OS << "%lm("; + else if (MO.isLoBits32()) + OS << "%lo("; + else if (MO.isHiBits64()) + OS << "%hh("; + else if (MO.isLoBits64()) + OS << "%hm("; else - { - if (op1Value->getValueType() == Value::ConstantVal) - {// value is constant and must be loaded from constant pool - returnFlags = returnFlags | (1 << op1Position); - } - minstr->SetMachineOperand(op1Position,MachineOperand::MO_VirtualRegister, - op1Value); - } + CloseParen = false; - // Check if operand 2 (if any) fits in the immediate field of the instruction, - // of if it is 0 and can use a dedicated machine register - if (op2Position >= 0) - { - Value* op2Value = vmInstrNode->rightChild()->getValue(); - int64_t immedValue; - unsigned int machineRegNum; - - MachineOperand::MachineOperandType - op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target, - /*canUseImmed*/ true, - machineRegNum, immedValue); - - if (op2type == MachineOperand::MO_MachineRegister) - minstr->SetMachineOperand(op2Position, machineRegNum); - else if (op2type == MachineOperand::MO_VirtualRegister) - { - if (op2Value->getValueType() == Value::ConstantVal) - {// value is constant and must be loaded from constant pool - returnFlags = returnFlags | (1 << op2Position); - } - minstr->SetMachineOperand(op2Position, op2type, op2Value); - } - else - { - assert(op2type != MO_CCRegister); - minstr->SetMachineOperand(op2Position, op2type, immedValue); - } + switch (MO.getType()) { + case MachineOperand::MO_VirtualRegister: + if (MO.getVRegValue()) { + OS << "%reg"; + OutputValue(OS, MO.getVRegValue()); + if (MO.hasAllocatedReg()) + OS << "=="; } - - // If operand 3 (result) can be discarded, use a dead register if one exists - if (canDiscardResult && target.zeroRegNum >= 0) - minstr->SetMachineOperand(resultPosition, target.zeroRegNum); - else - minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); + if (MO.hasAllocatedReg()) + OutputReg(OS, MO.getReg(), MRI); + break; + case MachineOperand::MO_CCRegister: + OS << "%ccreg"; + OutputValue(OS, MO.getVRegValue()); + if (MO.hasAllocatedReg()) { + OS << "=="; + OutputReg(OS, MO.getReg(), MRI); + } + break; + case MachineOperand::MO_MachineRegister: + OutputReg(OS, MO.getMachineRegNum(), MRI); + break; + case MachineOperand::MO_SignExtendedImmed: + OS << (long)MO.getImmedValue(); + break; + case MachineOperand::MO_UnextendedImmed: + OS << (long)MO.getImmedValue(); + break; + case MachineOperand::MO_PCRelativeDisp: { + const Value* opVal = MO.getVRegValue(); + bool isLabel = isa(opVal) || isa(opVal); + OS << "%disp(" << (isLabel? "label " : "addr-of-val "); + if (opVal->hasName()) + OS << opVal->getName(); + else + OS << (const void*) opVal; + OS << ")"; + break; + } + case MachineOperand::MO_MachineBasicBlock: + OS << "mbb<" + << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() + << "," << (void*)MO.getMachineBasicBlock() << ">"; + break; + case MachineOperand::MO_FrameIndex: + OS << ""; + break; + case MachineOperand::MO_ConstantPoolIndex: + OS << ""; + break; + case MachineOperand::MO_GlobalAddress: + OS << "getName(); + if (MO.getOffset()) OS << "+" << MO.getOffset(); + OS << ">"; + break; + case MachineOperand::MO_ExternalSymbol: + OS << ""; + break; + default: + assert(0 && "Unrecognized operand type"); + } - return returnFlags; + if (CloseParen) + OS << ")"; } -#endif +void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { + unsigned StartOp = 0; -void -Set3OperandsFromInstr(MachineInstr* minstr, - InstructionNode* vmInstrNode, - const TargetMachine& target, - bool canDiscardResult, - int op1Position, - int op2Position, - int resultPosition) -{ - assert(op1Position >= 0); - assert(resultPosition >= 0); - - // operand 1 - minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister, - vmInstrNode->leftChild()->getValue()); + // Specialize printing if op#0 is definition + if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { + ::print(getOperand(0), OS, TM); + OS << " = "; + ++StartOp; // Don't print this operand again! + } + + // Must check if Target machine is not null because machine BB could not + // be attached to a Machine function yet + if (TM) + OS << TM->getInstrInfo()->getName(getOpcode()); - // operand 2 (if any) - if (op2Position >= 0) - minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister, - vmInstrNode->rightChild()->getValue()); + for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { + const MachineOperand& mop = getOperand(i); + if (i != StartOp) + OS << ","; + OS << " "; + ::print(mop, OS, TM); + + if (mop.isDef()) + if (mop.isUse()) + OS << ""; + else + OS << ""; + } + + // code for printing implicit references + if (getNumImplicitRefs()) { + OS << "\tImplicitRefs: "; + for (unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { + OS << "\t"; + OutputValue(OS, getImplicitRef(i)); + if (getImplicitOp(i).isDef()) + if (getImplicitOp(i).isUse()) + OS << ""; + else + OS << ""; + } + } - // result operand: if it can be discarded, use a dead register if one exists - if (canDiscardResult && target.zeroRegNum >= 0) - minstr->SetMachineOperand(resultPosition, target.zeroRegNum); - else - minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); + OS << "\n"; } +namespace llvm { +std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) { + // If the instruction is embedded into a basic block, we can find the target + // info for the instruction. + if (const MachineBasicBlock *MBB = MI.getParent()) { + const MachineFunction *MF = MBB->getParent(); + if (MF) + MI.print(os, &MF->getTarget()); + else + MI.print(os, 0); + return os; + } -MachineOperand::MachineOperandType -ChooseRegOrImmed(Value* val, - MachineOpCode opCode, - const TargetMachine& target, - bool canUseImmed, - unsigned int& getMachineRegNum, - int64_t& getImmedValue) -{ - MachineOperand::MachineOperandType opType = - MachineOperand::MO_VirtualRegister; - getMachineRegNum = 0; - getImmedValue = 0; + // Otherwise, print it out in the "raw" format without symbolic register names + // and such. + os << TargetInstrDescriptors[MI.getOpcode()].Name; - // Check for the common case first: argument is not constant - // - if (val->getValueType() != Value::ConstantVal) - return opType; + for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) { + os << "\t" << MI.getOperand(i); + if (MI.getOperand(i).isDef()) + if (MI.getOperand(i).isUse()) + os << ""; + else + os << ""; + } - // Now get the constant value and check if it fits in the IMMED field. - // Take advantage of the fact that the max unsigned value will rarely - // fit into any IMMED field and ignore that case (i.e., cast smaller - // unsigned constants to signed). - // - bool isValidConstant; - int64_t intValue = GetConstantValueAsSignedInt(val, isValidConstant); + // code for printing implicit references + unsigned NumOfImpRefs = MI.getNumImplicitRefs(); + if (NumOfImpRefs > 0) { + os << "\tImplicit: "; + for (unsigned z = 0; z < NumOfImpRefs; z++) { + OutputValue(os, MI.getImplicitRef(z)); + if (MI.getImplicitOp(z).isDef()) + if (MI.getImplicitOp(z).isUse()) + os << ""; + else + os << ""; + os << "\t"; + } + } - if (isValidConstant) - { - if (intValue == 0 && target.zeroRegNum >= 0) - { - opType = MachineOperand::MO_MachineRegister; - getMachineRegNum = target.zeroRegNum; - } - else if (canUseImmed && - target.getInstrInfo().constantFitsInImmedField(opCode,intValue)) - { - opType = MachineOperand::MO_SignExtendedImmed; - getImmedValue = intValue; - } + return os << "\n"; +} + +std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { + if (MO.isHiBits32()) + OS << "%lm("; + else if (MO.isLoBits32()) + OS << "%lo("; + else if (MO.isHiBits64()) + OS << "%hh("; + else if (MO.isLoBits64()) + OS << "%hm("; + + switch (MO.getType()) { + case MachineOperand::MO_VirtualRegister: + if (MO.hasAllocatedReg()) + OutputReg(OS, MO.getReg()); + + if (MO.getVRegValue()) { + if (MO.hasAllocatedReg()) OS << "=="; + OS << "%vreg"; + OutputValue(OS, MO.getVRegValue()); } + break; + case MachineOperand::MO_CCRegister: + OS << "%ccreg"; + OutputValue(OS, MO.getVRegValue()); + if (MO.hasAllocatedReg()) { + OS << "=="; + OutputReg(OS, MO.getReg()); + } + break; + case MachineOperand::MO_MachineRegister: + OutputReg(OS, MO.getMachineRegNum()); + break; + case MachineOperand::MO_SignExtendedImmed: + OS << (long)MO.getImmedValue(); + break; + case MachineOperand::MO_UnextendedImmed: + OS << (long)MO.getImmedValue(); + break; + case MachineOperand::MO_PCRelativeDisp: { + const Value* opVal = MO.getVRegValue(); + bool isLabel = isa(opVal) || isa(opVal); + OS << "%disp(" << (isLabel? "label " : "addr-of-val "); + if (opVal->hasName()) + OS << opVal->getName(); + else + OS << (const void*) opVal; + OS << ")"; + break; + } + case MachineOperand::MO_MachineBasicBlock: + OS << "getBasicBlock())->getName() + << "@" << (void*)MO.getMachineBasicBlock() << ">"; + break; + case MachineOperand::MO_FrameIndex: + OS << ""; + break; + case MachineOperand::MO_ConstantPoolIndex: + OS << ""; + break; + case MachineOperand::MO_GlobalAddress: + OS << "getName() << ">"; + break; + case MachineOperand::MO_ExternalSymbol: + OS << ""; + break; + default: + assert(0 && "Unrecognized operand type"); + break; + } + + if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64()) + OS << ")"; - return opType; + return OS; +} + }