X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMachineInstr.cpp;h=7d1f15c487b4d0b1195feedabd221b4738c1ab6c;hb=86cba32bb4858f988b5026b62a66c4dba473f08b;hp=d54e7613f3b696680bc83b7b42cdaef138aaeaf8;hpb=014278e6a11fa0767853b831e5bf51b95bf541c5;p=oota-llvm.git diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index d54e7613f3b..7d1f15c487b 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -11,8 +11,9 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Constants.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/Constants.h" +#include "llvm/InlineAsm.h" #include "llvm/Value.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -21,12 +22,13 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrDesc.h" #include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Analysis/DebugInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/LeakDetector.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Streams.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/FoldingSet.h" -#include using namespace llvm; //===----------------------------------------------------------------------===// @@ -37,7 +39,7 @@ using namespace llvm; /// MachineRegisterInfo. If it is null, then the next/prev fields should be /// explicitly nulled out. void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { - assert(isRegister() && "Can only add reg operand to use lists"); + assert(isReg() && "Can only add reg operand to use lists"); // If the reginfo pointer is null, just explicitly null out or next/prev // pointers, to ensure they are not garbage. @@ -67,6 +69,21 @@ void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { *Head = this; } +/// RemoveRegOperandFromRegInfo - Remove this register operand from the +/// MachineRegisterInfo it is linked with. +void MachineOperand::RemoveRegOperandFromRegInfo() { + assert(isOnRegUseList() && "Reg operand is not on a use list"); + // Unlink this from the doubly linked list of operands. + MachineOperand *NextOp = Contents.Reg.Next; + *Contents.Reg.Prev = NextOp; + if (NextOp) { + assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); + NextOp->Contents.Reg.Prev = Contents.Reg.Prev; + } + Contents.Reg.Prev = 0; + Contents.Reg.Next = 0; +} + void MachineOperand::setReg(unsigned Reg) { if (getReg() == Reg) return; // No change. @@ -92,7 +109,7 @@ void MachineOperand::setReg(unsigned Reg) { void MachineOperand::ChangeToImmediate(int64_t ImmVal) { // If this operand is currently a register operand, and if this is in a // function, deregister the operand from the register's use/def list. - if (isRegister() && getParent() && getParent()->getParent() && + if (isReg() && getParent() && getParent()->getParent() && getParent()->getParent()->getParent()) RemoveRegOperandFromRegInfo(); @@ -104,11 +121,11 @@ void MachineOperand::ChangeToImmediate(int64_t ImmVal) { /// the specified value. If an operand is known to be an register already, /// the setReg method should be used. void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, - bool isKill, bool isDead, - bool isEarlyClobber) { + bool isKill, bool isDead, bool isUndef) { // If this operand is already a register operand, use setReg to update the // register's use/def lists. - if (isRegister()) { + if (isReg()) { + assert(!isEarlyClobber()); setReg(Reg); } else { // Otherwise, change this to a register and set the reg#. @@ -127,17 +144,20 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, IsImp = isImp; IsKill = isKill; IsDead = isDead; - IsEarlyClobber = isEarlyClobber; + IsUndef = isUndef; + IsEarlyClobber = false; SubReg = 0; } /// isIdenticalTo - Return true if this operand is identical to the specified /// operand. bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { - if (getType() != Other.getType()) return false; + if (getType() != Other.getType() || + getTargetFlags() != Other.getTargetFlags()) + return false; switch (getType()) { - default: assert(0 && "Unrecognized operand type"); + default: llvm_unreachable("Unrecognized operand type"); case MachineOperand::MO_Register: return getReg() == Other.getReg() && isDef() == Other.isDef() && getSubReg() == Other.getSubReg(); @@ -164,6 +184,11 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { /// print - Print the specified machine operand. /// void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { + raw_os_ostream RawOS(OS); + print(RawOS, TM); +} + +void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { switch (getType()) { case MachineOperand::MO_Register: if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { @@ -182,66 +207,79 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { else OS << "%mreg" << getReg(); } - - if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) { - OS << "<"; + + if (getSubReg() != 0) + OS << ':' << getSubReg(); + + if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || + isEarlyClobber()) { + OS << '<'; bool NeedComma = false; if (isImplicit()) { + if (NeedComma) OS << ','; OS << (isDef() ? "imp-def" : "imp-use"); NeedComma = true; } else if (isDef()) { + if (NeedComma) OS << ','; if (isEarlyClobber()) OS << "earlyclobber,"; OS << "def"; NeedComma = true; } - if (isKill() || isDead()) { - if (NeedComma) OS << ","; + if (isKill() || isDead() || isUndef()) { + if (NeedComma) OS << ','; if (isKill()) OS << "kill"; if (isDead()) OS << "dead"; + if (isUndef()) { + if (isKill() || isDead()) + OS << ','; + OS << "undef"; + } } - OS << ">"; + OS << '>'; } break; case MachineOperand::MO_Immediate: OS << getImm(); break; case MachineOperand::MO_FPImmediate: - if (getFPImm()->getType() == Type::FloatTy) { + if (getFPImm()->getType() == Type::getFloatTy(getFPImm()->getContext())) OS << getFPImm()->getValueAPF().convertToFloat(); - } else { + else OS << getFPImm()->getValueAPF().convertToDouble(); - } break; case MachineOperand::MO_MachineBasicBlock: OS << "mbb<" << ((Value*)getMBB()->getBasicBlock())->getName() - << "," << (void*)getMBB() << ">"; + << "," << (void*)getMBB() << '>'; break; case MachineOperand::MO_FrameIndex: - OS << ""; + OS << "'; break; case MachineOperand::MO_ConstantPoolIndex: OS << ""; + OS << '>'; break; case MachineOperand::MO_JumpTableIndex: - OS << ""; + OS << "'; break; case MachineOperand::MO_GlobalAddress: OS << "getName(); if (getOffset()) OS << "+" << getOffset(); - OS << ">"; + OS << '>'; break; case MachineOperand::MO_ExternalSymbol: OS << ""; + OS << '>'; break; default: - assert(0 && "Unrecognized operand type"); + llvm_unreachable("Unrecognized operand type"); } + + if (unsigned TF = getTargetFlags()) + OS << "[TF=" << TF << ']'; } //===----------------------------------------------------------------------===// @@ -272,7 +310,7 @@ void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { /// MachineInstr ctor - This constructor creates a dummy MachineInstr with /// TID NULL and no operands. MachineInstr::MachineInstr() - : TID(0), NumImplicitOps(0), Parent(0) { + : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); } @@ -291,7 +329,8 @@ void MachineInstr::addImplicitDefUseOperands() { /// TargetInstrDesc or the numOperands if it is not zero. (for /// instructions with variable number of operands). MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) - : TID(&tid), NumImplicitOps(0), Parent(0) { + : TID(&tid), NumImplicitOps(0), Parent(0), + debugLoc(DebugLoc::getUnknownLoc()) { if (!NoImp && TID->getImplicitDefs()) for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) NumImplicitOps++; @@ -305,12 +344,49 @@ MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) LeakDetector::addGarbageObject(this); } -/// MachineInstr ctor - Work exactly the same as the ctor above, except that the -/// MachineInstr is created and added to the end of the specified basic block. +/// MachineInstr ctor - As above, but with a DebugLoc. +MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, + bool NoImp) + : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) { + if (!NoImp && TID->getImplicitDefs()) + for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) + NumImplicitOps++; + if (!NoImp && TID->getImplicitUses()) + for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) + NumImplicitOps++; + Operands.reserve(NumImplicitOps + TID->getNumOperands()); + if (!NoImp) + addImplicitDefUseOperands(); + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); +} + +/// MachineInstr ctor - Work exactly the same as the ctor two above, except +/// that the MachineInstr is created and added to the end of the specified +/// basic block. +/// +MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) + : TID(&tid), NumImplicitOps(0), Parent(0), + debugLoc(DebugLoc::getUnknownLoc()) { + assert(MBB && "Cannot use inserting ctor with null basic block!"); + if (TID->ImplicitDefs) + for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) + NumImplicitOps++; + if (TID->ImplicitUses) + for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) + NumImplicitOps++; + Operands.reserve(NumImplicitOps + TID->getNumOperands()); + addImplicitDefUseOperands(); + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); + MBB->push_back(this); // Add instruction to end of basic block! +} + +/// MachineInstr ctor - As above, but with a DebugLoc. /// -MachineInstr::MachineInstr(MachineBasicBlock *MBB, +MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, const TargetInstrDesc &tid) - : TID(&tid), NumImplicitOps(0), Parent(0) { + : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) { assert(MBB && "Cannot use inserting ctor with null basic block!"); if (TID->ImplicitDefs) for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) @@ -328,7 +404,8 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, /// MachineInstr ctor - Copies MachineInstr arg exactly /// MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) - : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) { + : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0), + debugLoc(MI.getDebugLoc()) { Operands.reserve(MI.getNumOperands()); // Add operands @@ -354,7 +431,7 @@ MachineInstr::~MachineInstr() { #ifndef NDEBUG for (unsigned i = 0, e = Operands.size(); i != e; ++i) { assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); - assert((!Operands[i].isRegister() || !Operands[i].isOnRegUseList()) && + assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && "Reg operand def/use list corrupted"); } #endif @@ -374,7 +451,7 @@ MachineRegisterInfo *MachineInstr::getRegInfo() { /// operands already be on their use lists. void MachineInstr::RemoveRegOperandsFromUseLists() { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i].isRegister()) + if (Operands[i].isReg()) Operands[i].RemoveRegOperandFromRegInfo(); } } @@ -384,7 +461,7 @@ void MachineInstr::RemoveRegOperandsFromUseLists() { /// operands not be on their use lists yet. void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i].isRegister()) + if (Operands[i].isReg()) Operands[i].AddRegOperandToRegInfo(&RegInfo); } } @@ -395,10 +472,12 @@ void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { /// an explicit operand it is added at the end of the explicit operand list /// (before the first implicit operand). void MachineInstr::addOperand(const MachineOperand &Op) { - bool isImpReg = Op.isRegister() && Op.isImplicit(); + bool isImpReg = Op.isReg() && Op.isImplicit(); assert((isImpReg || !OperandsComplete()) && "Trying to add an operand to a machine instr that is already done!"); + MachineRegisterInfo *RegInfo = getRegInfo(); + // If we are adding the operand to the end of the list, our job is simpler. // This is true most of the time, so this is a reasonable optimization. if (isImpReg || NumImplicitOps == 0) { @@ -411,8 +490,8 @@ void MachineInstr::addOperand(const MachineOperand &Op) { Operands.back().ParentMI = this; // If the operand is a register, update the operand's use list. - if (Op.isRegister()) - Operands.back().AddRegOperandToRegInfo(getRegInfo()); + if (Op.isReg()) + Operands.back().AddRegOperandToRegInfo(RegInfo); return; } } @@ -420,8 +499,6 @@ void MachineInstr::addOperand(const MachineOperand &Op) { // Otherwise, we have to insert a real operand before any implicit ones. unsigned OpNo = Operands.size()-NumImplicitOps; - MachineRegisterInfo *RegInfo = getRegInfo(); - // If this instruction isn't embedded into a function, then we don't need to // update any operand lists. if (RegInfo == 0) { @@ -431,7 +508,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) { // Do explicitly set the reginfo for this operand though, to ensure the // next/prev fields are properly nulled out. - if (Operands[OpNo].isRegister()) + if (Operands[OpNo].isReg()) Operands[OpNo].AddRegOperandToRegInfo(0); } else if (Operands.size()+1 <= Operands.capacity()) { @@ -444,7 +521,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) { // list, just remove the implicit operands, add the operand, then re-add all // the rest of the operands. for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { - assert(Operands[i].isRegister() && "Should only be an implicit reg!"); + assert(Operands[i].isReg() && "Should only be an implicit reg!"); Operands[i].RemoveRegOperandFromRegInfo(); } @@ -452,12 +529,12 @@ void MachineInstr::addOperand(const MachineOperand &Op) { Operands.insert(Operands.begin()+OpNo, Op); Operands[OpNo].ParentMI = this; - if (Operands[OpNo].isRegister()) + if (Operands[OpNo].isReg()) Operands[OpNo].AddRegOperandToRegInfo(RegInfo); // Re-add all the implicit ops. for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { - assert(Operands[i].isRegister() && "Should only be an implicit reg!"); + assert(Operands[i].isReg() && "Should only be an implicit reg!"); Operands[i].AddRegOperandToRegInfo(RegInfo); } } else { @@ -483,7 +560,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) { // Special case removing the last one. if (OpNo == Operands.size()-1) { // If needed, remove from the reg def/use list. - if (Operands.back().isRegister() && Operands.back().isOnRegUseList()) + if (Operands.back().isReg() && Operands.back().isOnRegUseList()) Operands.back().RemoveRegOperandFromRegInfo(); Operands.pop_back(); @@ -496,7 +573,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) { MachineRegisterInfo *RegInfo = getRegInfo(); if (RegInfo) { for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { - if (Operands[i].isRegister()) + if (Operands[i].isReg()) Operands[i].RemoveRegOperandFromRegInfo(); } } @@ -505,7 +582,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) { if (RegInfo) { for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { - if (Operands[i].isRegister()) + if (Operands[i].isReg()) Operands[i].AddRegOperandToRegInfo(RegInfo); } } @@ -557,9 +634,9 @@ unsigned MachineInstr::getNumExplicitOperands() const { if (!TID->isVariadic()) return NumOperands; - for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { - const MachineOperand &MO = getOperand(NumOperands); - if (!MO.isRegister() || !MO.isImplicit()) + for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { + const MachineOperand &MO = getOperand(i); + if (!MO.isReg() || !MO.isImplicit()) NumOperands++; } return NumOperands; @@ -587,7 +664,7 @@ int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned MOReg = MO.getReg(); if (!MOReg) @@ -611,7 +688,7 @@ int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, const TargetRegisterInfo *TRI) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned MOReg = MO.getReg(); if (MOReg == Reg || @@ -639,25 +716,132 @@ int MachineInstr::findFirstPredOperandIdx() const { return -1; } -/// isRegReDefinedByTwoAddr - Given the defined register and the operand index, -/// check if the register def is a re-definition due to two addr elimination. -bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{ +/// isRegTiedToUseOperand - Given the index of a register def operand, +/// check if the register def is tied to a source operand, due to either +/// two-address elimination or inline assembly constraints. Returns the +/// first tied use operand index by reference is UseOpIdx is not null. +bool MachineInstr:: +isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { + if (getOpcode() == TargetInstrInfo::INLINEASM) { + assert(DefOpIdx >= 2); + const MachineOperand &MO = getOperand(DefOpIdx); + if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) + return false; + // Determine the actual operand index that corresponds to this index. + unsigned DefNo = 0; + unsigned DefPart = 0; + for (unsigned i = 1, e = getNumOperands(); i < e; ) { + const MachineOperand &FMO = getOperand(i); + // After the normal asm operands there may be additional imp-def regs. + if (!FMO.isImm()) + return false; + // Skip over this def. + unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm()); + unsigned PrevDef = i + 1; + i = PrevDef + NumOps; + if (i > DefOpIdx) { + DefPart = DefOpIdx - PrevDef; + break; + } + ++DefNo; + } + for (unsigned i = 1, e = getNumOperands(); i != e; ++i) { + const MachineOperand &FMO = getOperand(i); + if (!FMO.isImm()) + continue; + if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) + continue; + unsigned Idx; + if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && + Idx == DefNo) { + if (UseOpIdx) + *UseOpIdx = (unsigned)i + 1 + DefPart; + return true; + } + } + return false; + } + + assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); const TargetInstrDesc &TID = getDesc(); for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg && - TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx) + if (MO.isReg() && MO.isUse() && + TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) { + if (UseOpIdx) + *UseOpIdx = (unsigned)i; return true; + } } return false; } +/// isRegTiedToDefOperand - Return true if the operand of the specified index +/// is a register use and it is tied to an def operand. It also returns the def +/// operand index by reference. +bool MachineInstr:: +isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { + if (getOpcode() == TargetInstrInfo::INLINEASM) { + const MachineOperand &MO = getOperand(UseOpIdx); + if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) + return false; + + // Find the flag operand corresponding to UseOpIdx + unsigned FlagIdx, NumOps=0; + for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) { + const MachineOperand &UFMO = getOperand(FlagIdx); + // After the normal asm operands there may be additional imp-def regs. + if (!UFMO.isImm()) + return false; + NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm()); + assert(NumOps < getNumOperands() && "Invalid inline asm flag"); + if (UseOpIdx < FlagIdx+NumOps+1) + break; + } + if (FlagIdx >= UseOpIdx) + return false; + const MachineOperand &UFMO = getOperand(FlagIdx); + unsigned DefNo; + if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { + if (!DefOpIdx) + return true; + + unsigned DefIdx = 1; + // Remember to adjust the index. First operand is asm string, then there + // is a flag for each. + while (DefNo) { + const MachineOperand &FMO = getOperand(DefIdx); + assert(FMO.isImm()); + // Skip over this def. + DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; + --DefNo; + } + *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; + return true; + } + return false; + } + + const TargetInstrDesc &TID = getDesc(); + if (UseOpIdx >= TID.getNumOperands()) + return false; + const MachineOperand &MO = getOperand(UseOpIdx); + if (!MO.isReg() || !MO.isUse()) + return false; + int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO); + if (DefIdx == -1) + return false; + if (DefOpIdx) + *DefOpIdx = (unsigned)DefIdx; + return true; +} + /// copyKillDeadInfo - Copies kill / dead operand properties from MI. /// void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || (!MO.isKill() && !MO.isDead())) + if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) continue; for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { MachineOperand &MOp = getOperand(j); @@ -688,13 +872,14 @@ void MachineInstr::copyPredicates(const MachineInstr *MI) { /// isSafeToMove - Return true if it is safe to move this instruction. If /// SawStore is set to true, it means that there is a store (or call) between /// the instruction's location and its intended destination. -bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) { +bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, + bool &SawStore) const { // Ignore stuff that we obviously can't move. if (TID->mayStore() || TID->isCall()) { SawStore = true; return false; } - if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects()) + if (TID->isTerminator() || TID->hasUnmodeledSideEffects()) return false; // See if this instruction does a load. If so, we have to guarantee that the @@ -702,30 +887,26 @@ bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) { // destination. The check for isInvariantLoad gives the targe the chance to // classify the load as always returning a constant, e.g. a constant pool // load. - if (TID->mayLoad() && !TII->isInvariantLoad(this)) { + if (TID->mayLoad() && !TII->isInvariantLoad(this)) // Otherwise, this is a real load. If there is a store between the load and - // end of block, we can't sink the load. - // - // FIXME: we can't do this transformation until we know that the load is - // not volatile, and machineinstrs don't keep this info. :( - // - //if (SawStore) - return false; - } + // end of block, or if the load is volatile, we can't move it. + return !SawStore && !hasVolatileMemoryRef(); + return true; } /// isSafeToReMat - Return true if it's safe to rematerialize the specified /// instruction which defined the specified register instead of copying it. -bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) { +bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, + unsigned DstReg) const { bool SawStore = false; if (!getDesc().isRematerializable() || !TII->isTriviallyReMaterializable(this) || !isSafeToMove(TII, SawStore)) return false; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { - MachineOperand &MO = getOperand(i); - if (!MO.isRegister()) + const MachineOperand &MO = getOperand(i); + if (!MO.isReg()) continue; // FIXME: For now, do not remat any instruction with register operands. // Later on, we can loosen the restriction is the register operands have @@ -740,14 +921,45 @@ bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg) { return true; } +/// hasVolatileMemoryRef - Return true if this instruction may have a +/// volatile memory reference, or if the information describing the +/// memory reference is not available. Return false if it is known to +/// have no volatile memory references. +bool MachineInstr::hasVolatileMemoryRef() const { + // An instruction known never to access memory won't have a volatile access. + if (!TID->mayStore() && + !TID->mayLoad() && + !TID->isCall() && + !TID->hasUnmodeledSideEffects()) + return false; + + // Otherwise, if the instruction has no memory reference information, + // conservatively assume it wasn't preserved. + if (memoperands_empty()) + return true; + + // Check the memory reference information for volatile references. + for (std::list::const_iterator I = memoperands_begin(), + E = memoperands_end(); I != E; ++I) + if (I->isVolatile()) + return true; + + return false; +} + void MachineInstr::dump() const { cerr << " " << *this; } void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { + raw_os_ostream RawOS(OS); + print(RawOS, TM); +} + +void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { // Specialize printing if op#0 is definition unsigned StartOp = 0; - if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) { + if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) { getOperand(0).print(OS, TM); OS << " = "; ++StartOp; // Don't print this operand again! @@ -787,8 +999,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { else if (!V->getName().empty()) OS << V->getName(); else if (const PseudoSourceValue *PSV = dyn_cast(V)) { - raw_os_ostream OSS(OS); - PSV->print(OSS); + PSV->print(OS); } else OS << V; @@ -796,6 +1007,17 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { } } + if (!debugLoc.isUnknown()) { + const MachineFunction *MF = getParent()->getParent(); + DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc); + DICompileUnit CU(DLT.CompileUnit); + std::string Dir, Fn; + OS << " [dbg: " + << CU.getDirectory(Dir) << '/' << CU.getFilename(Fn) << "," + << DLT.Line << "," + << DLT.Col << "]"; + } + OS << "\n"; } @@ -808,7 +1030,7 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, SmallVector DeadOps; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue; unsigned Reg = MO.getReg(); if (!Reg) @@ -819,6 +1041,9 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, if (MO.isKill()) // The register is already marked kill. return true; + if (isPhysReg && isRegTiedToDefOperand(i)) + // Two-address uses of physregs must not be marked kill. + return true; MO.setIsKill(); Found = true; } @@ -863,7 +1088,7 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg, SmallVector DeadOps; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); if (!Reg) @@ -901,13 +1126,13 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg, // If not found, this means an alias of one of the operands is dead. Add a // new implicit operand if required. - if (!Found && AddIfNotFound) { - addOperand(MachineOperand::CreateReg(IncomingReg, - true /*IsDef*/, - true /*IsImp*/, - false /*IsKill*/, - true /*IsDead*/)); - return true; - } - return Found; + if (Found || !AddIfNotFound) + return Found; + + addOperand(MachineOperand::CreateReg(IncomingReg, + true /*IsDef*/, + true /*IsImp*/, + false /*IsKill*/, + true /*IsDead*/)); + return true; }