X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMachineInstr.cpp;h=ca2c2db4a8480ea467bb105d51b8a12b0d141ca9;hb=be766c72464116a445a02b542a450c4274bab5d0;hp=bbe2144f237852feeae4822aa8e675dd2c076257;hpb=ed8f674b9a18312886355288ac49f9a2dd5e4e94;p=oota-llvm.git diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index bbe2144f237..ca2c2db4a84 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -1,392 +1,430 @@ -// $Id$ -//*************************************************************************** -// File: -// MachineInstr.cpp +//===-- MachineInstr.cpp --------------------------------------------------===// // -// Purpose: -// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. // -// Strategy: -// -// History: -// 7/2/01 - Vikram Adve - Created -//**************************************************************************/ - +//===----------------------------------------------------------------------===// +// +// Methods common to all machine instructions. +// +// FIXME: Now that MachineInstrs have parent pointers, they should always +// print themselves using their MachineFunction's TargetMachine. +// +//===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Method.h" -#include "llvm/ConstPoolVals.h" -#include "llvm/Instruction.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/Value.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/MRegisterInfo.h" +namespace llvm { -//************************ Class Implementations **************************/ - -// Constructor for instructions with fixed #operands (nearly all) -MachineInstr::MachineInstr(MachineOpCode _opCode, - OpCodeMask _opCodeMask) - : opCode(_opCode), - opCodeMask(_opCodeMask), - operands(TargetInstrDescriptors[_opCode].numOperands) -{ - assert(TargetInstrDescriptors[_opCode].numOperands >= 0); -} +// Global variable holding an array of descriptors for machine instructions. +// The actual object needs to be created separately for each target machine. +// This variable is initialized and reset by class TargetInstrInfo. +// +// FIXME: This should be a property of the target so that more than one target +// at a time can be active... +// +extern const TargetInstrDescriptor *TargetInstrDescriptors; // Constructor for instructions with variable #operands -MachineInstr::MachineInstr(MachineOpCode _opCode, - unsigned numOperands, - OpCodeMask _opCodeMask) - : opCode(_opCode), - opCodeMask(_opCodeMask), - operands(numOperands) -{ +MachineInstr::MachineInstr(short opcode, unsigned numOperands) + : Opcode(opcode), + numImplicitRefs(0), + operands(numOperands, MachineOperand()), + parent(0) { } -void -MachineInstr::SetMachineOperand(unsigned int i, - MachineOperand::MachineOperandType operandType, - Value* _val, bool isdef=false) -{ - assert(i < operands.size()); - operands[i].Initialize(operandType, _val); - operands[i].isDef = isdef || - TargetInstrDescriptors[opCode].resultPos == (int) i; +/// MachineInstr ctor - This constructor only does a _reserve_ of the operands, +/// not a resize for them. It is expected that if you use this that you call +/// add* methods below to fill up the operands, instead of the Set methods. +/// Eventually, the "resizing" ctors will be phased out. +/// +MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) + : Opcode(opcode), numImplicitRefs(0), parent(0) { + operands.reserve(numOperands); } -void -MachineInstr::SetMachineOperand(unsigned int i, - MachineOperand::MachineOperandType operandType, - int64_t intValue, bool isdef=false) -{ - assert(i < operands.size()); - operands[i].InitializeConst(operandType, intValue); - operands[i].isDef = isdef || - TargetInstrDescriptors[opCode].resultPos == (int) i; +/// MachineInstr ctor - Work exactly the same as the ctor above, except that the +/// MachineInstr is created and added to the end of the specified basic block. +/// +MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, + unsigned numOperands) + : Opcode(opcode), numImplicitRefs(0), parent(0) { + assert(MBB && "Cannot use inserting ctor with null basic block!"); + operands.reserve(numOperands); + MBB->push_back(this); // Add instruction to end of basic block! } -void -MachineInstr::SetMachineOperand(unsigned int i, - unsigned int regNum, bool isdef=false) -{ - assert(i < operands.size()); - operands[i].InitializeReg(regNum); - operands[i].isDef = isdef || - TargetInstrDescriptors[opCode].resultPos == (int) i; +/// OperandComplete - Return true if it's illegal to add a new operand +/// +bool MachineInstr::OperandsComplete() const { + int NumOperands = TargetInstrDescriptors[Opcode].numOperands; + if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) + return true; // Broken: we have all the operands of this instruction! + return false; } -void -MachineInstr::dump(unsigned int indent) const -{ - for (unsigned i=0; i < indent; i++) - cout << " "; - - cout << *this; +/// replace - Support for replacing opcode and operands of a MachineInstr in +/// place. This only resets the size of the operand vector and initializes it. +/// The new operands must be set explicitly later. +/// +void MachineInstr::replace(short opcode, unsigned numOperands) { + assert(getNumImplicitRefs() == 0 && + "This is probably broken because implicit refs are going to be lost."); + Opcode = opcode; + operands.clear(); + operands.resize(numOperands, MachineOperand()); } -ostream& -operator<< (ostream& os, const MachineInstr& minstr) -{ - os << TargetInstrDescriptors[minstr.opCode].opCodeString; - - for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) - os << "\t" << minstr.getOperand(i); - -#undef DEBUG_VAL_OP_ITERATOR -#ifdef DEBUG_VAL_OP_ITERATOR - os << endl << "\tValue operands are: "; - for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo) - { - const Value* val = *vo; - os << val << (vo.isDef()? "(def), " : ", "); - } - os << endl; -#endif - - return os; +void MachineInstr::SetMachineOperandVal(unsigned i, + MachineOperand::MachineOperandType opTy, + Value* V) { + assert(i < operands.size()); // may be explicit or implicit op + operands[i].opType = opTy; + operands[i].value = V; + operands[i].regNum = -1; } -static inline ostream &OutputOperand(ostream &os, const MachineOperand &mop) { - switch (mop.getOperandType()) { - case MachineOperand::MO_CCRegister: - case MachineOperand::MO_VirtualRegister: - return os << "(val " << mop.getVRegValue() << ")"; - case MachineOperand::MO_MachineRegister: - return os << "(" << mop.getMachineRegNum() << ")"; - default: - assert(0 && "Unknown operand type"); - return os; - } +void +MachineInstr::SetMachineOperandConst(unsigned i, + MachineOperand::MachineOperandType opTy, + int64_t intValue) { + assert(i < getNumOperands()); // must be explicit op + assert(TargetInstrDescriptors[Opcode].resultPos != (int) i && + "immed. constant cannot be defined"); + + operands[i].opType = opTy; + operands[i].value = NULL; + operands[i].immedVal = intValue; + operands[i].regNum = -1; + operands[i].flags = 0; } +void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { + assert(i < getNumOperands()); // must be explicit op -ostream &operator<<(ostream &os, const MachineOperand &mop) { - switch(mop.opType) { - case MachineOperand::MO_VirtualRegister: - case MachineOperand::MO_MachineRegister: - os << "%reg"; - return OutputOperand(os, mop); - case MachineOperand::MO_CCRegister: - os << "%ccreg"; - return OutputOperand(os, mop); - case MachineOperand::MO_SignExtendedImmed: - return os << mop.immedVal; - case MachineOperand::MO_UnextendedImmed: - return os << mop.immedVal; - case MachineOperand::MO_PCRelativeDisp: - return os << "%disp(label " << mop.getVRegValue() << ")"; - default: - assert(0 && "Unrecognized operand type"); - break; - } - - return os; + operands[i].opType = MachineOperand::MO_MachineRegister; + operands[i].value = NULL; + operands[i].regNum = regNum; } +// Used only by the SPARC back-end. +void MachineInstr::SetRegForOperand(unsigned i, int regNum) { + assert(i < getNumOperands()); // must be explicit op + operands[i].setRegForValue(regNum); +} -//--------------------------------------------------------------------------- -// Target-independent utility routines for creating machine instructions -//--------------------------------------------------------------------------- - - -//------------------------------------------------------------------------ -// Function Set2OperandsFromInstr -// Function Set3OperandsFromInstr -// -// For the common case of 2- and 3-operand arithmetic/logical instructions, -// set the m/c instr. operands directly from the VM instruction's operands. -// Check whether the first or second operand is 0 and can use a dedicated "0" -// register. -// Check whether the second operand should use an immediate field or register. -// (First and third operands are never immediates for such instructions.) -// -// Arguments: -// canDiscardResult: Specifies that the result operand can be discarded -// by using the dedicated "0" -// -// op1position, op2position and resultPosition: Specify in which position -// in the machine instruction the 3 operands (arg1, arg2 -// and result) should go. -// -// RETURN VALUE: unsigned int flags, where -// flags & 0x01 => operand 1 is constant and needs a register -// flags & 0x02 => operand 2 is constant and needs a register -//------------------------------------------------------------------------ - -void -Set2OperandsFromInstr(MachineInstr* minstr, - InstructionNode* vmInstrNode, - const TargetMachine& target, - bool canDiscardResult, - int op1Position, - int resultPosition) -{ - Set3OperandsFromInstr(minstr, vmInstrNode, target, - canDiscardResult, op1Position, - /*op2Position*/ -1, resultPosition); +// Used only by the SPARC back-end. +void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) { + getImplicitOp(i).setRegForValue(regNum); } -#undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS -#ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS +/// substituteValue - Substitute all occurrences of Value* oldVal with newVal +/// in all operands and all implicit refs. If defsOnly == true, substitute defs +/// only. +/// +/// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865, +/// or make it a static function in that file. +/// unsigned -Set3OperandsFromInstrJUNK(MachineInstr* minstr, - InstructionNode* vmInstrNode, - const TargetMachine& target, - bool canDiscardResult, - int op1Position, - int op2Position, - int resultPosition) +MachineInstr::substituteValue(const Value* oldVal, Value* newVal, + bool defsOnly, bool notDefsAndUses, + bool& someArgsWereIgnored) { - assert(op1Position >= 0); - assert(resultPosition >= 0); + assert((!defsOnly || !notDefsAndUses) && + "notDefsAndUses is irrelevant if defsOnly == true."); - unsigned returnFlags = 0x0; - - // Check if operand 1 is 0. If so, try to use a hardwired 0 register. - Value* op1Value = vmInstrNode->leftChild()->getValue(); - bool isValidConstant; - int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant); - if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0) - minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum); - else - { - if (op1Value->isConstant()) { - // value is constant and must be loaded from constant pool - returnFlags = returnFlags | (1 << op1Position); - } - minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister, - op1Value); - } - - // Check if operand 2 (if any) fits in the immed. field of the instruction, - // or if it is 0 and can use a dedicated machine register - if (op2Position >= 0) - { - Value* op2Value = vmInstrNode->rightChild()->getValue(); - int64_t immedValue; - unsigned int machineRegNum; - - MachineOperand::MachineOperandType - op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target, - /*canUseImmed*/ true, - machineRegNum, immedValue); - - if (op2type == MachineOperand::MO_MachineRegister) - minstr->SetMachineOperand(op2Position, machineRegNum); - else if (op2type == MachineOperand::MO_VirtualRegister) - { - if (op2Value->isConstant()) { - // value is constant and must be loaded from constant pool - returnFlags = returnFlags | (1 << op2Position); - } - minstr->SetMachineOperand(op2Position, op2type, op2Value); - } + unsigned numSubst = 0; + + // Substitute operands + for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) + if (*O == oldVal) + if (!defsOnly || + notDefsAndUses && (O.isDef() && !O.isUse()) || + !notDefsAndUses && O.isDef()) + { + O.getMachineOperand().value = newVal; + ++numSubst; + } else - { - assert(op2type != MO_CCRegister); - minstr->SetMachineOperand(op2Position, op2type, immedValue); - } - } - - // If operand 3 (result) can be discarded, use a dead register if one exists - if (canDiscardResult && target.zeroRegNum >= 0) - minstr->SetMachineOperand(resultPosition, target.zeroRegNum); - else - minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); + someArgsWereIgnored = true; + + // Substitute implicit refs + for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) + if (getImplicitRef(i) == oldVal) + if (!defsOnly || + notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) || + !notDefsAndUses && getImplicitOp(i).isDef()) + { + getImplicitOp(i).value = newVal; + ++numSubst; + } + else + someArgsWereIgnored = true; - return returnFlags; + return numSubst; } -#endif +void MachineInstr::dump() const { + std::cerr << " " << *this; +} -void -Set3OperandsFromInstr(MachineInstr* minstr, - InstructionNode* vmInstrNode, - const TargetMachine& target, - bool canDiscardResult, - int op1Position, - int op2Position, - int resultPosition) -{ - assert(op1Position >= 0); - assert(resultPosition >= 0); - - // operand 1 - minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister, - vmInstrNode->leftChild()->getValue()); - - // operand 2 (if any) - if (op2Position >= 0) - minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister, - vmInstrNode->rightChild()->getValue()); - - // result operand: if it can be discarded, use a dead register if one exists - if (canDiscardResult && target.zeroRegNum >= 0) - minstr->SetMachineOperand(resultPosition, target.zeroRegNum); - else - minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue()); +static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { + os << "(val "; + os << (void*) val; // print address always + if (val && val->hasName()) + os << " " << val->getName(); // print name also, if available + os << ")"; + return os; } +static inline void OutputReg(std::ostream &os, unsigned RegNo, + const MRegisterInfo *MRI = 0) { + if (MRI) { + if (MRegisterInfo::isPhysicalRegister(RegNo)) + os << "%" << MRI->get(RegNo).Name; + else + os << "%reg" << RegNo; + } else + os << "%mreg(" << RegNo << ")"; +} -MachineOperand::MachineOperandType -ChooseRegOrImmed(Value* val, - MachineOpCode opCode, - const TargetMachine& target, - bool canUseImmed, - unsigned int& getMachineRegNum, - int64_t& getImmedValue) -{ - MachineOperand::MachineOperandType opType = - MachineOperand::MO_VirtualRegister; - getMachineRegNum = 0; - getImmedValue = 0; +static void print(const MachineOperand &MO, std::ostream &OS, + const TargetMachine &TM) { + const MRegisterInfo *MRI = TM.getRegisterInfo(); + bool CloseParen = true; + if (MO.isHiBits32()) + OS << "%lm("; + else if (MO.isLoBits32()) + OS << "%lo("; + else if (MO.isHiBits64()) + OS << "%hh("; + else if (MO.isLoBits64()) + OS << "%hm("; + else + CloseParen = false; - // Check for the common case first: argument is not constant - // - ConstPoolVal *CPV = val->castConstant(); - if (!CPV) return opType; - - if (CPV->getType() == Type::BoolTy) { - ConstPoolBool *CPB = (ConstPoolBool*)CPV; - if (!CPB->getValue() && target.zeroRegNum >= 0) { - getMachineRegNum = target.zeroRegNum; - return MachineOperand::MO_MachineRegister; + switch (MO.getType()) { + case MachineOperand::MO_VirtualRegister: + if (MO.getVRegValue()) { + OS << "%reg"; + OutputValue(OS, MO.getVRegValue()); + if (MO.hasAllocatedReg()) + OS << "=="; + } + if (MO.hasAllocatedReg()) + OutputReg(OS, MO.getReg(), MRI); + break; + case MachineOperand::MO_CCRegister: + OS << "%ccreg"; + OutputValue(OS, MO.getVRegValue()); + if (MO.hasAllocatedReg()) { + OS << "=="; + OutputReg(OS, MO.getReg(), MRI); } + break; + case MachineOperand::MO_MachineRegister: + OutputReg(OS, MO.getMachineRegNum(), MRI); + break; + case MachineOperand::MO_SignExtendedImmed: + OS << (long)MO.getImmedValue(); + break; + case MachineOperand::MO_UnextendedImmed: + OS << (long)MO.getImmedValue(); + break; + case MachineOperand::MO_PCRelativeDisp: { + const Value* opVal = MO.getVRegValue(); + bool isLabel = isa(opVal) || isa(opVal); + OS << "%disp(" << (isLabel? "label " : "addr-of-val "); + if (opVal->hasName()) + OS << opVal->getName(); + else + OS << (const void*) opVal; + OS << ")"; + break; + } + case MachineOperand::MO_MachineBasicBlock: + OS << "bb<" + << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() + << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; + break; + case MachineOperand::MO_FrameIndex: + OS << ""; + break; + case MachineOperand::MO_ConstantPoolIndex: + OS << ""; + break; + case MachineOperand::MO_GlobalAddress: + OS << "getName() << ">"; + break; + case MachineOperand::MO_ExternalSymbol: + OS << ""; + break; + default: + assert(0 && "Unrecognized operand type"); + } + + if (CloseParen) + OS << ")"; +} + +void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { + unsigned StartOp = 0; - getImmedValue = 1; - return MachineOperand::MO_SignExtendedImmed; + // Specialize printing if op#0 is definition + if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { + llvm::print(getOperand(0), OS, TM); + OS << " = "; + ++StartOp; // Don't print this operand again! } + OS << TM.getInstrInfo().getName(getOpcode()); - if (!CPV->getType()->isIntegral()) return opType; - - // Now get the constant value and check if it fits in the IMMED field. - // Take advantage of the fact that the max unsigned value will rarely - // fit into any IMMED field and ignore that case (i.e., cast smaller - // unsigned constants to signed). - // - int64_t intValue; - if (CPV->getType()->isSigned()) { - intValue = ((ConstPoolSInt*)CPV)->getValue(); - } else { - uint64_t V = ((ConstPoolUInt*)CPV)->getValue(); - if (V >= INT64_MAX) return opType; - intValue = (int64_t)V; + for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { + const MachineOperand& mop = getOperand(i); + if (i != StartOp) + OS << ","; + OS << " "; + llvm::print(mop, OS, TM); + + if (mop.isDef()) + if (mop.isUse()) + OS << ""; + else + OS << ""; } - - if (intValue == 0 && target.zeroRegNum >= 0){ - opType = MachineOperand::MO_MachineRegister; - getMachineRegNum = target.zeroRegNum; - } else if (canUseImmed && - target.getInstrInfo().constantFitsInImmedField(opCode, intValue)) { - opType = MachineOperand::MO_SignExtendedImmed; - getImmedValue = intValue; + + // code for printing implicit references + if (getNumImplicitRefs()) { + OS << "\tImplicitRefs: "; + for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { + OS << "\t"; + OutputValue(OS, getImplicitRef(i)); + if (getImplicitOp(i).isDef()) + if (getImplicitOp(i).isUse()) + OS << ""; + else + OS << ""; + } } - return opType; + OS << "\n"; } - -void -PrintMachineInstructions(const Method *const method) -{ - cout << "\n" << method->getReturnType() - << " \"" << method->getName() << "\"" << endl; +std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) { + os << TargetInstrDescriptors[MI.getOpcode()].Name; - for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI) - { - BasicBlock* bb = *BI; - cout << "\n" - << (bb->hasName()? bb->getName() : "Label") - << " (" << bb << ")" << ":" - << endl; - - MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec(); - for (unsigned i=0; i < mvec.size(); i++) - cout << "\t" << *mvec[i] << endl; - } - cout << endl << "End method \"" << method->getName() << "\"" - << endl << endl; + for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) { + os << "\t" << MI.getOperand(i); + if (MI.getOperand(i).isDef()) + if (MI.getOperand(i).isUse()) + os << ""; + else + os << ""; + } + + // code for printing implicit references + unsigned NumOfImpRefs = MI.getNumImplicitRefs(); + if (NumOfImpRefs > 0) { + os << "\tImplicit: "; + for (unsigned z=0; z < NumOfImpRefs; z++) { + OutputValue(os, MI.getImplicitRef(z)); + if (MI.getImplicitOp(z).isDef()) + if (MI.getImplicitOp(z).isUse()) + os << ""; + else + os << ""; + os << "\t"; + } + } + + return os << "\n"; } -#if 0 - -void PrintMachineInstructions(Method * method) - -{ - cout << "\n" << method->getReturnType() - << " \"" << method->getName() << "\"" << endl; +std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { + if (MO.isHiBits32()) + OS << "%lm("; + else if (MO.isLoBits32()) + OS << "%lo("; + else if (MO.isHiBits64()) + OS << "%hh("; + else if (MO.isLoBits64()) + OS << "%hm("; - for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI) + switch (MO.getType()) { - const BasicBlock* bb = *BI; - cout << "\n" - << (bb->hasName()? bb->getName() : "Label") - << " (" << bb << ")" << ":" - << endl; - - const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec(); - for (unsigned i=0; i < mvec.size(); i++) - cout << "\t" << *mvec[i] << endl; - } - cout << endl << "End method \"" << method->getName() << "\"" - << endl << endl; + case MachineOperand::MO_VirtualRegister: + if (MO.hasAllocatedReg()) + OutputReg(OS, MO.getReg()); + + if (MO.getVRegValue()) { + if (MO.hasAllocatedReg()) OS << "=="; + OS << "%vreg"; + OutputValue(OS, MO.getVRegValue()); + } + break; + case MachineOperand::MO_CCRegister: + OS << "%ccreg"; + OutputValue(OS, MO.getVRegValue()); + if (MO.hasAllocatedReg()) { + OS << "=="; + OutputReg(OS, MO.getReg()); + } + break; + case MachineOperand::MO_MachineRegister: + OutputReg(OS, MO.getMachineRegNum()); + break; + case MachineOperand::MO_SignExtendedImmed: + OS << (long)MO.getImmedValue(); + break; + case MachineOperand::MO_UnextendedImmed: + OS << (long)MO.getImmedValue(); + break; + case MachineOperand::MO_PCRelativeDisp: + { + const Value* opVal = MO.getVRegValue(); + bool isLabel = isa(opVal) || isa(opVal); + OS << "%disp(" << (isLabel? "label " : "addr-of-val "); + if (opVal->hasName()) + OS << opVal->getName(); + else + OS << (const void*) opVal; + OS << ")"; + break; + } + case MachineOperand::MO_MachineBasicBlock: + OS << "bb<" + << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() + << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; + break; + case MachineOperand::MO_FrameIndex: + OS << ""; + break; + case MachineOperand::MO_ConstantPoolIndex: + OS << ""; + break; + case MachineOperand::MO_GlobalAddress: + OS << "getName() << ">"; + break; + case MachineOperand::MO_ExternalSymbol: + OS << ""; + break; + default: + assert(0 && "Unrecognized operand type"); + break; + } + + if (MO.flags & + (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 | + MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64)) + OS << ")"; + + return OS; } -#endif + +} // End llvm namespace