X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMachineInstr.cpp;h=cc85b80a1789add6222cbe2a94936bb448364946;hb=b169426272b85ce28a9a56d13154e61b158fc47a;hp=b396382cf6c7a2458f42b25553bbfb74fd069a93;hpb=6130f66eaae89f8878590796977678afa8448926;p=oota-llvm.git diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index b396382cf6c..cc85b80a178 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -17,13 +17,15 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" -#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrDesc.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/LeakDetector.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/Streams.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/ADT/FoldingSet.h" #include using namespace llvm; @@ -106,6 +108,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, // If this operand is already a register operand, use setReg to update the // register's use/def lists. if (isReg()) { + assert(!isEarlyClobber()); setReg(Reg); } else { // Otherwise, change this to a register and set the reg#. @@ -124,6 +127,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, IsImp = isImp; IsKill = isKill; IsDead = isDead; + IsEarlyClobber = false; SubReg = 0; } @@ -160,6 +164,11 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { /// print - Print the specified machine operand. /// void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { + raw_os_ostream RawOS(OS); + print(RawOS, TM); +} + +void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { switch (getType()) { case MachineOperand::MO_Register: if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { @@ -178,14 +187,22 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { else OS << "%mreg" << getReg(); } - - if (isDef() || isKill() || isDead() || isImplicit()) { + + if (getSubReg() != 0) { + OS << ":" << getSubReg(); + } + + if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) { OS << "<"; bool NeedComma = false; if (isImplicit()) { + if (NeedComma) OS << ","; OS << (isDef() ? "imp-def" : "imp-use"); NeedComma = true; } else if (isDef()) { + if (NeedComma) OS << ","; + if (isEarlyClobber()) + OS << "earlyclobber,"; OS << "def"; NeedComma = true; } @@ -238,6 +255,27 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { } } +//===----------------------------------------------------------------------===// +// MachineMemOperand Implementation +//===----------------------------------------------------------------------===// + +MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, + int64_t o, uint64_t s, unsigned int a) + : Offset(o), Size(s), V(v), + Flags((f & 7) | ((Log2_32(a) + 1) << 3)) { + assert(isPowerOf2_32(a) && "Alignment is not a power of 2!"); + assert((isLoad() || isStore()) && "Not a load/store!"); +} + +/// Profile - Gather unique data for the object. +/// +void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { + ID.AddInteger(Offset); + ID.AddInteger(Size); + ID.AddPointer(V); + ID.AddInteger(Flags); +} + //===----------------------------------------------------------------------===// // MachineInstr Implementation //===----------------------------------------------------------------------===// @@ -245,7 +283,7 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { /// MachineInstr ctor - This constructor creates a dummy MachineInstr with /// TID NULL and no operands. MachineInstr::MachineInstr() - : TID(0), NumImplicitOps(0), Parent(0) { + : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) { // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); } @@ -264,7 +302,25 @@ void MachineInstr::addImplicitDefUseOperands() { /// TargetInstrDesc or the numOperands if it is not zero. (for /// instructions with variable number of operands). MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) - : TID(&tid), NumImplicitOps(0), Parent(0) { + : TID(&tid), NumImplicitOps(0), Parent(0), + debugLoc(DebugLoc::getUnknownLoc()) { + if (!NoImp && TID->getImplicitDefs()) + for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) + NumImplicitOps++; + if (!NoImp && TID->getImplicitUses()) + for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) + NumImplicitOps++; + Operands.reserve(NumImplicitOps + TID->getNumOperands()); + if (!NoImp) + addImplicitDefUseOperands(); + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); +} + +/// MachineInstr ctor - As above, but with a DebugLoc. +MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, + bool NoImp) + : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) { if (!NoImp && TID->getImplicitDefs()) for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) NumImplicitOps++; @@ -278,12 +334,32 @@ MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) LeakDetector::addGarbageObject(this); } -/// MachineInstr ctor - Work exactly the same as the ctor above, except that the -/// MachineInstr is created and added to the end of the specified basic block. +/// MachineInstr ctor - Work exactly the same as the ctor two above, except +/// that the MachineInstr is created and added to the end of the specified +/// basic block. /// -MachineInstr::MachineInstr(MachineBasicBlock *MBB, +MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) + : TID(&tid), NumImplicitOps(0), Parent(0), + debugLoc(DebugLoc::getUnknownLoc()) { + assert(MBB && "Cannot use inserting ctor with null basic block!"); + if (TID->ImplicitDefs) + for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) + NumImplicitOps++; + if (TID->ImplicitUses) + for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) + NumImplicitOps++; + Operands.reserve(NumImplicitOps + TID->getNumOperands()); + addImplicitDefUseOperands(); + // Make sure that we get added to a machine basicblock + LeakDetector::addGarbageObject(this); + MBB->push_back(this); // Add instruction to end of basic block! +} + +/// MachineInstr ctor - As above, but with a DebugLoc. +/// +MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, const TargetInstrDesc &tid) - : TID(&tid), NumImplicitOps(0), Parent(0) { + : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) { assert(MBB && "Cannot use inserting ctor with null basic block!"); if (TID->ImplicitDefs) for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) @@ -300,27 +376,31 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, /// MachineInstr ctor - Copies MachineInstr arg exactly /// -MachineInstr::MachineInstr(const MachineInstr &MI) { - TID = &MI.getDesc(); - NumImplicitOps = MI.NumImplicitOps; +MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) + : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0), + debugLoc(MI.getDebugLoc()) { Operands.reserve(MI.getNumOperands()); - MemOperands = MI.MemOperands; // Add operands - for (unsigned i = 0; i != MI.getNumOperands(); ++i) { - Operands.push_back(MI.getOperand(i)); - Operands.back().ParentMI = this; - } + for (unsigned i = 0; i != MI.getNumOperands(); ++i) + addOperand(MI.getOperand(i)); + NumImplicitOps = MI.NumImplicitOps; + + // Add memory operands. + for (std::list::const_iterator i = MI.memoperands_begin(), + j = MI.memoperands_end(); i != j; ++i) + addMemOperand(MF, *i); - // Set parent, next, and prev to null + // Set parent to null. Parent = 0; - Prev = 0; - Next = 0; -} + LeakDetector::addGarbageObject(this); +} MachineInstr::~MachineInstr() { LeakDetector::removeGarbageObject(this); + assert(MemOperands.empty() && + "MachineInstr being deleted with live memoperands!"); #ifndef NDEBUG for (unsigned i = 0, e = Operands.size(); i != e; ++i) { assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); @@ -330,19 +410,12 @@ MachineInstr::~MachineInstr() { #endif } -/// getOpcode - Returns the opcode of this MachineInstr. -/// -int MachineInstr::getOpcode() const { - return TID->Opcode; -} - /// getRegInfo - If this instruction is embedded into a MachineFunction, /// return the MachineRegisterInfo object for the current function, otherwise /// return null. MachineRegisterInfo *MachineInstr::getRegInfo() { if (MachineBasicBlock *MBB = getParent()) - if (MachineFunction *MF = MBB->getParent()) - return &MF->getRegInfo(); + return &MBB->getParent()->getRegInfo(); return 0; } @@ -376,6 +449,8 @@ void MachineInstr::addOperand(const MachineOperand &Op) { assert((isImpReg || !OperandsComplete()) && "Trying to add an operand to a machine instr that is already done!"); + MachineRegisterInfo *RegInfo = getRegInfo(); + // If we are adding the operand to the end of the list, our job is simpler. // This is true most of the time, so this is a reasonable optimization. if (isImpReg || NumImplicitOps == 0) { @@ -389,7 +464,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) { // If the operand is a register, update the operand's use list. if (Op.isReg()) - Operands.back().AddRegOperandToRegInfo(getRegInfo()); + Operands.back().AddRegOperandToRegInfo(RegInfo); return; } } @@ -397,8 +472,6 @@ void MachineInstr::addOperand(const MachineOperand &Op) { // Otherwise, we have to insert a real operand before any implicit ones. unsigned OpNo = Operands.size()-NumImplicitOps; - MachineRegisterInfo *RegInfo = getRegInfo(); - // If this instruction isn't embedded into a function, then we don't need to // update any operand lists. if (RegInfo == 0) { @@ -488,6 +561,18 @@ void MachineInstr::RemoveOperand(unsigned OpNo) { } } +/// addMemOperand - Add a MachineMemOperand to the machine instruction, +/// referencing arbitrary storage. +void MachineInstr::addMemOperand(MachineFunction &MF, + const MachineMemOperand &MO) { + MemOperands.push_back(MO); +} + +/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands. +void MachineInstr::clearMemOperands(MachineFunction &MF) { + MemOperands.clear(); +} + /// removeFromParent - This method unlinks 'this' from the containing basic /// block, and returns it, but does not delete it. @@ -498,6 +583,14 @@ MachineInstr *MachineInstr::removeFromParent() { } +/// eraseFromParent - This method unlinks 'this' from the containing basic +/// block, and deletes it. +void MachineInstr::eraseFromParent() { + assert(getParent() && "Not embedded in a basic block!"); + getParent()->erase(this); +} + + /// OperandComplete - Return true if it's illegal to add a new operand /// bool MachineInstr::OperandsComplete() const { @@ -516,17 +609,25 @@ unsigned MachineInstr::getNumExplicitOperands() const { for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { const MachineOperand &MO = getOperand(NumOperands); - if (!MO.isRegister() || !MO.isImplicit()) + if (!MO.isReg() || !MO.isImplicit()) NumOperands++; } return NumOperands; } +/// isLabel - Returns true if the MachineInstr represents a label. +/// +bool MachineInstr::isLabel() const { + return getOpcode() == TargetInstrInfo::DBG_LABEL || + getOpcode() == TargetInstrInfo::EH_LABEL || + getOpcode() == TargetInstrInfo::GC_LABEL; +} + /// isDebugLabel - Returns true if the MachineInstr represents a debug label. /// bool MachineInstr::isDebugLabel() const { - return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0; + return getOpcode() == TargetInstrInfo::DBG_LABEL; } /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of @@ -536,7 +637,7 @@ int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned MOReg = MO.getReg(); if (!MOReg) @@ -553,13 +654,14 @@ int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, } /// findRegisterDefOperandIdx() - Returns the operand index that is a def of -/// the specific register or -1 if it is not found. It further tightening - /// the search criteria to a def that is dead the register if isDead is true. +/// the specified register or -1 if it is not found. If isDead is true, defs +/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it +/// also checks if there is a def of a super-register. int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, const TargetRegisterInfo *TRI) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned MOReg = MO.getReg(); if (MOReg == Reg || @@ -587,30 +689,44 @@ int MachineInstr::findFirstPredOperandIdx() const { return -1; } -/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due -/// to two addr elimination. -bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const { +/// isRegReDefinedByTwoAddr - Given the index of a register operand, +/// check if the register def is a re-definition due to two addr elimination. +bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{ + assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!"); const TargetInstrDesc &TID = getDesc(); - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { - const MachineOperand &MO1 = getOperand(i); - if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) { - for (unsigned j = i+1; j < e; ++j) { - const MachineOperand &MO2 = getOperand(j); - if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg && - TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i) - return true; - } - } + for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = getOperand(i); + if (MO.isReg() && MO.isUse() && + TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx) + return true; } return false; } +/// isRegTiedToDefOperand - Return true if the operand of the specified index +/// is a register use and it is tied to an def operand. It also returns the def +/// operand index by reference. +bool MachineInstr::isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx){ + const TargetInstrDesc &TID = getDesc(); + if (UseOpIdx >= TID.getNumOperands()) + return false; + const MachineOperand &MO = getOperand(UseOpIdx); + if (!MO.isReg() || !MO.isUse()) + return false; + int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO); + if (DefIdx == -1) + return false; + if (DefOpIdx) + *DefOpIdx = (unsigned)DefIdx; + return true; +} + /// copyKillDeadInfo - Copies kill / dead operand properties from MI. /// void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || (!MO.isKill() && !MO.isDead())) + if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) continue; for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { MachineOperand &MOp = getOperand(j); @@ -628,24 +744,107 @@ void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { /// copyPredicates - Copies predicate operand(s) from MI. void MachineInstr::copyPredicates(const MachineInstr *MI) { const TargetInstrDesc &TID = MI->getDesc(); - if (TID.isPredicable()) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - if (TID.OpInfo[i].isPredicate()) { - // Predicated operands must be last operands. - addOperand(MI->getOperand(i)); - } + if (!TID.isPredicable()) + return; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + if (TID.OpInfo[i].isPredicate()) { + // Predicated operands must be last operands. + addOperand(MI->getOperand(i)); } } } +/// isSafeToMove - Return true if it is safe to move this instruction. If +/// SawStore is set to true, it means that there is a store (or call) between +/// the instruction's location and its intended destination. +bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, + bool &SawStore) const { + // Ignore stuff that we obviously can't move. + if (TID->mayStore() || TID->isCall()) { + SawStore = true; + return false; + } + if (TID->isTerminator() || TID->hasUnmodeledSideEffects()) + return false; + + // See if this instruction does a load. If so, we have to guarantee that the + // loaded value doesn't change between the load and the its intended + // destination. The check for isInvariantLoad gives the targe the chance to + // classify the load as always returning a constant, e.g. a constant pool + // load. + if (TID->mayLoad() && !TII->isInvariantLoad(this)) + // Otherwise, this is a real load. If there is a store between the load and + // end of block, or if the laod is volatile, we can't move it. + return !SawStore && !hasVolatileMemoryRef(); + + return true; +} + +/// isSafeToReMat - Return true if it's safe to rematerialize the specified +/// instruction which defined the specified register instead of copying it. +bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, + unsigned DstReg) const { + bool SawStore = false; + if (!getDesc().isRematerializable() || + !TII->isTriviallyReMaterializable(this) || + !isSafeToMove(TII, SawStore)) + return false; + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + const MachineOperand &MO = getOperand(i); + if (!MO.isReg()) + continue; + // FIXME: For now, do not remat any instruction with register operands. + // Later on, we can loosen the restriction is the register operands have + // not been modified between the def and use. Note, this is different from + // MachineSink because the code is no longer in two-address form (at least + // partially). + if (MO.isUse()) + return false; + else if (!MO.isDead() && MO.getReg() != DstReg) + return false; + } + return true; +} + +/// hasVolatileMemoryRef - Return true if this instruction may have a +/// volatile memory reference, or if the information describing the +/// memory reference is not available. Return false if it is known to +/// have no volatile memory references. +bool MachineInstr::hasVolatileMemoryRef() const { + // An instruction known never to access memory won't have a volatile access. + if (!TID->mayStore() && + !TID->mayLoad() && + !TID->isCall() && + !TID->hasUnmodeledSideEffects()) + return false; + + // Otherwise, if the instruction has no memory reference information, + // conservatively assume it wasn't preserved. + if (memoperands_empty()) + return true; + + // Check the memory reference information for volatile references. + for (std::list::const_iterator I = memoperands_begin(), + E = memoperands_end(); I != E; ++I) + if (I->isVolatile()) + return true; + + return false; +} + void MachineInstr::dump() const { cerr << " " << *this; } void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { + raw_os_ostream RawOS(OS); + print(RawOS, TM); +} + +void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { // Specialize printing if op#0 is definition unsigned StartOp = 0; - if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) { + if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) { getOperand(0).print(OS, TM); OS << " = "; ++StartOp; // Don't print this operand again! @@ -660,10 +859,11 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { getOperand(i).print(OS, TM); } - if (getNumMemOperands() > 0) { + if (!memoperands_empty()) { OS << ", Mem:"; - for (unsigned i = 0; i < getNumMemOperands(); i++) { - const MemOperand &MRO = getMemOperand(i); + for (std::list::const_iterator i = memoperands_begin(), + e = memoperands_end(); i != e; ++i) { + const MachineMemOperand &MRO = *i; const Value *V = MRO.getValue(); assert((MRO.isLoad() || MRO.isStore()) && @@ -683,149 +883,136 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { OS << ""; else if (!V->getName().empty()) OS << V->getName(); - else if (isa(V)) - OS << *V; - else + else if (const PseudoSourceValue *PSV = dyn_cast(V)) { + PSV->print(OS); + } else OS << V; OS << " + " << MRO.getOffset() << "]"; } } + if (!debugLoc.isUnknown()) { + const MachineFunction *MF = getParent()->getParent(); + DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc); + OS << " [dbg: " + << DLT.Src << "," + << DLT.Line << "," + << DLT.Col << "]"; + } + OS << "\n"; } bool MachineInstr::addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound) { - // Go through the machine instruction's operands to eliminate any potentially - // illegal conditions. I.e., a super- and sub-register both marked "kill". - for (unsigned i = 0, e = getNumOperands(); i < e;) { - MachineOperand &MO = getOperand(i); - if (MO.isRegister() && MO.isUse()) { - unsigned Reg = MO.getReg(); - - if (!Reg || IncomingReg == Reg || - !TargetRegisterInfo::isPhysicalRegister(Reg) || - !TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { - ++i; - continue; - } - - if (RegInfo->isSuperRegister(IncomingReg, Reg) && MO.isKill()) - // The kill information is already handled by a super-register. Don't - // add this sub-register as a kill. - return true; - - if (RegInfo->isSubRegister(IncomingReg, Reg) && MO.isKill()) { - if (MO.isImplicit()) { - // Remove this implicit use that marks the sub-register - // "kill". Let the super-register take care of this - // information. - RemoveOperand(i); - --e; - continue; - } else { - // The super-register is going to take care of this kill - // information. - MO.setIsKill(false); - } - } - } - - ++i; - } - - // If the register already exists, then make sure it or its super-register is - // marked "kill". + bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); + bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); + bool Found = false; + SmallVector DeadOps; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { MachineOperand &MO = getOperand(i); + if (!MO.isReg() || !MO.isUse()) + continue; + unsigned Reg = MO.getReg(); + if (!Reg) + continue; - if (MO.isRegister() && MO.isUse()) { - unsigned Reg = MO.getReg(); - if (!Reg) continue; - - if (Reg == IncomingReg) { + if (Reg == IncomingReg) { + if (!Found) { + if (MO.isKill()) + // The register is already marked kill. + return true; MO.setIsKill(); - return true; + Found = true; } - - if (TargetRegisterInfo::isPhysicalRegister(Reg) && - TargetRegisterInfo::isPhysicalRegister(IncomingReg) && - RegInfo->isSuperRegister(IncomingReg, Reg) && - MO.isKill()) - // A super-register kill already exists. + } else if (hasAliases && MO.isKill() && + TargetRegisterInfo::isPhysicalRegister(Reg)) { + // A super-register kill already exists. + if (RegInfo->isSuperRegister(IncomingReg, Reg)) return true; + if (RegInfo->isSubRegister(IncomingReg, Reg)) + DeadOps.push_back(i); } } + // Trim unneeded kill operands. + while (!DeadOps.empty()) { + unsigned OpIdx = DeadOps.back(); + if (getOperand(OpIdx).isImplicit()) + RemoveOperand(OpIdx); + else + getOperand(OpIdx).setIsKill(false); + DeadOps.pop_back(); + } + // If not found, this means an alias of one of the operands is killed. Add a // new implicit operand if required. - if (AddIfNotFound) { + if (!Found && AddIfNotFound) { addOperand(MachineOperand::CreateReg(IncomingReg, false /*IsDef*/, true /*IsImp*/, true /*IsKill*/)); return true; } - - return false; + return Found; } bool MachineInstr::addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound) { + bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); + bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); bool Found = false; + SmallVector DeadOps; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { MachineOperand &MO = getOperand(i); - if (MO.isRegister() && MO.isDef()) { - unsigned Reg = MO.getReg(); - if (!Reg) - continue; - if (Reg == IncomingReg) { + if (!MO.isReg() || !MO.isDef()) + continue; + unsigned Reg = MO.getReg(); + if (!Reg) + continue; + + if (Reg == IncomingReg) { + if (!Found) { + if (MO.isDead()) + // The register is already marked dead. + return true; MO.setIsDead(); Found = true; - break; - } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && - TargetRegisterInfo::isPhysicalRegister(IncomingReg) && - RegInfo->isSuperRegister(IncomingReg, Reg) && - MO.isDead()) - // There exists a super-register that's marked dead. + } + } else if (hasAliases && MO.isDead() && + TargetRegisterInfo::isPhysicalRegister(Reg)) { + // There exists a super-register that's marked dead. + if (RegInfo->isSuperRegister(IncomingReg, Reg)) return true; + if (RegInfo->getSubRegisters(IncomingReg) && + RegInfo->getSuperRegisters(Reg) && + RegInfo->isSubRegister(IncomingReg, Reg)) + DeadOps.push_back(i); } } - // If not found, this means an alias of one of the operand is dead. Add a - // new implicit operand. + // Trim unneeded dead operands. + while (!DeadOps.empty()) { + unsigned OpIdx = DeadOps.back(); + if (getOperand(OpIdx).isImplicit()) + RemoveOperand(OpIdx); + else + getOperand(OpIdx).setIsDead(false); + DeadOps.pop_back(); + } + + // If not found, this means an alias of one of the operands is dead. Add a + // new implicit operand if required. if (!Found && AddIfNotFound) { - addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/, - true/*IsImp*/,false/*IsKill*/, - true/*IsDead*/)); + addOperand(MachineOperand::CreateReg(IncomingReg, + true /*IsDef*/, + true /*IsImp*/, + false /*IsKill*/, + true /*IsDead*/)); return true; } return Found; } - -/// copyKillDeadInfo - copies killed/dead information from one instr to another -void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI, - const TargetRegisterInfo *RegInfo) { - // If the instruction defines any virtual registers, update the VarInfo, - // kill and dead information for the instruction. - for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = OldMI->getOperand(i); - if (MO.isRegister() && MO.getReg() && - TargetRegisterInfo::isVirtualRegister(MO.getReg())) { - unsigned Reg = MO.getReg(); - if (MO.isDef()) { - if (MO.isDead()) { - MO.setIsDead(false); - addRegisterDead(Reg, RegInfo); - } - } - if (MO.isKill()) { - MO.setIsKill(false); - addRegisterKilled(Reg, RegInfo); - } - } - } -}