X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMachineRegisterInfo.cpp;h=c247a22d23e70a00059b0d274820a0c08570de73;hb=ef5b199905cee0b78eb30cd44836e5b6ca5cbd09;hp=f217c042be2ef0810c1fe4b9665c1f8f75c25e42;hpb=62ed6b9ade63bf01717ce5274fa11e93e873d245;p=oota-llvm.git diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp index f217c042be2..c247a22d23e 100644 --- a/lib/CodeGen/MachineRegisterInfo.cpp +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -14,19 +14,22 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" using namespace llvm; -MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) { +MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { VRegInfo.reserve(256); - UsedPhysRegs.resize(MRI.getNumRegs()); + UsedPhysRegs.resize(TRI.getNumRegs()); // Create the physreg use/def lists. - PhysRegUseDefLists = new MachineOperand*[MRI.getNumRegs()]; - memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*MRI.getNumRegs()); + PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; + memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); } MachineRegisterInfo::~MachineRegisterInfo() { #ifndef NDEBUG for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); + for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) + assert(!PhysRegUseDefLists[i] && + "PhysRegUseDefLists has entries after all instructions are deleted"); #endif delete [] PhysRegUseDefLists; } @@ -44,3 +47,40 @@ void MachineRegisterInfo::HandleVRegListReallocation() { List->Contents.Reg.Prev = &VRegInfo[i].second; } } + +/// replaceRegWith - Replace all instances of FromReg with ToReg in the +/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), +/// except that it also changes any definitions of the register as well. +void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { + assert(FromReg != ToReg && "Cannot replace a reg with itself"); + + // TODO: This could be more efficient by bulk changing the operands. + for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { + MachineOperand &O = I.getOperand(); + ++I; + O.setReg(ToReg); + } +} + + +/// getVRegDef - Return the machine instr that defines the specified virtual +/// register or null if none is found. This assumes that the code is in SSA +/// form, so there should only be one definition. +MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { + assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && + "Invalid vreg!"); + for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) { + // Since we are in SSA form, we can stop at the first definition. + if (I.getOperand().isDef()) + return &*I; + } + return 0; +} + + +#ifndef NDEBUG +void MachineRegisterInfo::dumpUses(unsigned Reg) const { + for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) + I.getOperand().getParent()->dump(); +} +#endif