X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMachineSink.cpp;h=d158c481ee18ba1dbc5528314904f4562afa144a;hb=d443ee68847c9af65b7c387c40e9e4038e660fdf;hp=b83d844a16234e665bd6948f2e2f075e6e8a745c;hpb=244588820867ab4e42f72c266196b848919bfebb;p=oota-llvm.git diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp index b83d844a162..d158c481ee1 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -7,7 +7,12 @@ // //===----------------------------------------------------------------------===// // -// This pass +// This pass moves instructions into successor blocks, when possible, so that +// they aren't executed on paths where their results aren't needed. +// +// This pass is not intended to be a replacement or a complete alternative +// for an LLVM-IR-level sinking pass. It is only designed to sink simple +// constructs that are not exposed before lowering and instruction selection. // //===----------------------------------------------------------------------===// @@ -15,10 +20,9 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineDominators.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" @@ -32,28 +36,30 @@ namespace { const TargetInstrInfo *TII; MachineFunction *CurMF; // Current MachineFunction MachineRegisterInfo *RegInfo; // Machine register information - MachineDominatorTree *DT; // Machine dominator tree for the current Loop + MachineDominatorTree *DT; // Machine dominator tree public: static char ID; // Pass identification - MachineSinking() : MachineFunctionPass((intptr_t)&ID) {} + MachineSinking() : MachineFunctionPass(&ID) {} virtual bool runOnMachineFunction(MachineFunction &MF); virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); AU.addRequired(); AU.addPreserved(); } private: bool ProcessBlock(MachineBasicBlock &MBB); - bool SinkInstruction(MachineInstr *MI); + bool SinkInstruction(MachineInstr *MI, bool &SawStore); bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const; }; - - char MachineSinking::ID = 0; - RegisterPass X("machine-sink", "Machine code sinking"); } // end anonymous namespace + +char MachineSinking::ID = 0; +static RegisterPass +X("machine-sink", "Machine code sinking"); FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); } @@ -61,7 +67,8 @@ FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); } /// occur in blocks dominated by the specified block. bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs"); + assert(TargetRegisterInfo::isVirtualRegister(Reg) && + "Only makes sense for vregs"); for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg), E = RegInfo->reg_end(); I != E; ++I) { if (I.getOperand().isDef()) continue; // ignore def. @@ -110,50 +117,47 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) { } bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) { - bool MadeChange = false; - // Can't sink anything out of a block that has less than two successors. - if (MBB.succ_size() <= 1) return false; - - // Walk the basic block bottom-up - for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ){ - MachineBasicBlock::iterator LastIt = I; - if (SinkInstruction(--I)) { - I = LastIt; - ++NumSunk; - } - } + if (MBB.succ_size() <= 1 || MBB.empty()) return false; + + bool MadeChange = false; + + // Walk the basic block bottom-up. Remember if we saw a store. + MachineBasicBlock::iterator I = MBB.end(); + --I; + bool ProcessedBegin, SawStore = false; + do { + MachineInstr *MI = I; // The instruction to sink. + + // Predecrement I (if it's not begin) so that it isn't invalidated by + // sinking. + ProcessedBegin = I == MBB.begin(); + if (!ProcessedBegin) + --I; + + if (SinkInstruction(MI, SawStore)) + ++NumSunk, MadeChange = true; + + // If we just processed the first instruction in the block, we're done. + } while (!ProcessedBegin); return MadeChange; } /// SinkInstruction - Determine whether it is safe to sink the specified machine /// instruction out of its current block into a successor. -bool MachineSinking::SinkInstruction(MachineInstr *MI) { - const TargetInstrDesc &TID = MI->getDesc(); - - // Ignore stuff that we obviously can't sink. - if (TID.mayStore() || TID.isCall() || TID.isReturn() || TID.isBranch()) - return false; - - if (TID.mayLoad()) +bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { + // Check if it's safe to move the instruction. + if (!MI->isSafeToMove(TII, SawStore)) return false; - // Don't sink things with side-effects we don't understand. - if (TII->hasUnmodelledSideEffects(MI)) - return false; - - // FIXME: we should be able to sink loads with no other side effects if there - // is nothing that can change memory from here until the end of block. This - // is a trivial form of alias analysis. - // FIXME: This should include support for sinking instructions within the // block they are currently in to shorten the live ranges. We often get // instructions sunk into the top of a large block, but it would be better to // also sink them down before their first use in the block. This xform has to // be careful not to *increase* register pressure though, e.g. sinking // "x = y + z" down if it kills y and z would increase the live ranges of y - // and z only the shrink the live range of x. + // and z and only shrink the live range of x. // Loop over all the operands of the specified instruction. If there is // anything we can't handle, bail out. @@ -170,7 +174,7 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI) { unsigned Reg = MO.getReg(); if (Reg == 0) continue; - if (MRegisterInfo::isPhysicalRegister(Reg)) { + if (TargetRegisterInfo::isPhysicalRegister(Reg)) { // If this is a physical register use, we can't move it. If it is a def, // we can move it, but only if the def is dead. if (MO.isUse() || !MO.isDead()) @@ -178,6 +182,10 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI) { } else { // Virtual register uses are always safe to sink. if (MO.isUse()) continue; + + // If it's not safe to move defs of the register class, then abort. + if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg))) + return false; // FIXME: This picks a successor to sink into based on having one // successor that dominates all the uses. However, there are cases where @@ -219,6 +227,16 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI) { // If there are no outputs, it must have side-effects. if (SuccToSinkTo == 0) return false; + + // It's not safe to sink instructions to EH landing pad. Control flow into + // landing pad is implicitly defined. + if (SuccToSinkTo->isLandingPad()) + return false; + + // If is not possible to sink an instruction into its own block. This can + // happen with loops. + if (MI->getParent() == SuccToSinkTo) + return false; DEBUG(cerr << "Sink instr " << *MI); DEBUG(cerr << "to block " << *SuccToSinkTo);