X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FPHIElimination.cpp;h=ceba842970d3005e474a3bec805546065b7643c9;hb=ac6cecec189ba9689c42543c3106c02b96d788da;hp=601bfd65d752fd0d8ac278106662f069c4979aa8;hpb=ae94dda61a045cb77681940ecc25aba0d2763f74;p=oota-llvm.git diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index 601bfd65d75..ceba842970d 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -73,13 +73,13 @@ namespace { // Defs of PHI sources which are implicit_def. SmallPtrSet ImpDefs; }; - - char PNE::ID = 0; - RegisterPass X("phi-node-elimination", - "Eliminate PHI nodes for register allocation"); } -const PassInfo *llvm::PHIEliminationID = X.getPassInfo(); +char PNE::ID = 0; +static RegisterPass +X("phi-node-elimination", "Eliminate PHI nodes for register allocation"); + +const PassInfo *const llvm::PHIEliminationID = &X; bool PNE::runOnMachineFunction(MachineFunction &Fn) { MRI = &Fn.getRegInfo(); @@ -97,7 +97,7 @@ bool PNE::runOnMachineFunction(MachineFunction &Fn) { E = ImpDefs.end(); I != E; ++I) { MachineInstr *DefMI = *I; unsigned DefReg = DefMI->getOperand(0).getReg(); - if (MRI->use_begin(DefReg) == MRI->use_end()) + if (MRI->use_empty(DefReg)) DefMI->eraseFromParent(); } @@ -127,8 +127,10 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) { return true; } +/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node +/// are implicit_def's. static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, - const MachineRegisterInfo *MRI) { + const MachineRegisterInfo *MRI) { for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) { unsigned SrcReg = MPhi->getOperand(i).getReg(); const MachineInstr *DefMI = MRI->getVRegDef(SrcReg); @@ -150,36 +152,44 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; unsigned DestReg = MPhi->getOperand(0).getReg(); + bool isDead = MPhi->getOperand(0).isDead(); // Create a new register for the incoming PHI arguments. MachineFunction &MF = *MBB.getParent(); const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); - unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC); + unsigned IncomingReg = 0; // Insert a register to register copy at the top of the current block (but // after any remaining phi nodes) which copies the new incoming register // into the phi node destination. const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); if (isSourceDefinedByImplicitDef(MPhi, MRI)) - // If all sources of a PHI node are implicit_def, just emit an implicit_def - // instead of a copy. - BuildMI(MBB, AfterPHIsIt, TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg); - else + // If all sources of a PHI node are implicit_def, just emit an + // implicit_def instead of a copy. + BuildMI(MBB, AfterPHIsIt, + TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg); + else { + IncomingReg = MF.getRegInfo().createVirtualRegister(RC); TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); + } // Update live variable information if there is any. LiveVariables *LV = getAnalysisToUpdate(); if (LV) { MachineInstr *PHICopy = prior(AfterPHIsIt); - // Increment use count of the newly created virtual register. - LV->getVarInfo(IncomingReg).NumUses++; + if (IncomingReg) { + // Increment use count of the newly created virtual register. + LV->getVarInfo(IncomingReg).NumUses++; + + // Add information to LiveVariables to know that the incoming value is + // killed. Note that because the value is defined in several places (once + // each for each incoming block), the "def" block and instruction fields + // for the VarInfo is not filled in. + LV->addVirtualRegisterKilled(IncomingReg, PHICopy); - // Add information to LiveVariables to know that the incoming value is - // killed. Note that because the value is defined in several places (once - // each for each incoming block), the "def" block and instruction fields for - // the VarInfo is not filled in. - LV->addVirtualRegisterKilled(IncomingReg, PHICopy); + LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true; + } // Since we are going to be deleting the PHI node, if it is the last use of // any registers, or if the value itself is dead, we need to move this @@ -187,12 +197,10 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, LV->removeVirtualRegistersKilled(MPhi); // If the result is dead, update LV. - if (MPhi->registerDefIsDead(DestReg)) { + if (isDead) { LV->addVirtualRegisterDead(DestReg, PHICopy); - LV->removeVirtualRegistersDead(MPhi); + LV->removeVirtualRegisterDead(DestReg, MPhi); } - - LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true; } // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. @@ -209,7 +217,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, "Machine PHI Operands must all be virtual registers!"); // If source is defined by an implicit def, there is no need to insert a - // copy unless it's the only source. + // copy. MachineInstr *DefMI = MRI->getVRegDef(SrcReg); if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { ImpDefs.insert(DefMI); @@ -229,7 +237,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, // Find a safe location to insert the copy, this may be the first terminator // in the block (or end()). MachineBasicBlock::iterator InsertPos = opBlock.getFirstTerminator(); - + // Insert the copy. TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC); @@ -346,7 +354,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, } // Really delete the PHI instruction now! - delete MPhi; + MF.DeleteMachineInstr(MPhi); ++NumAtomic; }