X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocBasic.cpp;h=5496d69fd3df1aa381faee2de9cdb4a3b9911100;hb=cccfd194ecf8e1c6fb203ec3f96aca8cfe9e0484;hp=545a6bd5bc7e3ded4d8951db1842dcd44e3cd473;hpb=18c57a8a09a7c79fbcf4348b0ad8135246ab984f;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp index 545a6bd5bc7..5496d69fd3d 100644 --- a/lib/CodeGen/RegAllocBasic.cpp +++ b/lib/CodeGen/RegAllocBasic.cpp @@ -13,12 +13,15 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "regalloc" -#include "LiveIntervalUnion.h" #include "RegAllocBase.h" +#include "LiveDebugVariables.h" +#include "LiveIntervalUnion.h" +#include "LiveRangeEdit.h" #include "RenderMachineFunction.h" #include "Spiller.h" #include "VirtRegMap.h" -#include "VirtRegRewriter.h" +#include "llvm/ADT/OwningPtr.h" +#include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Function.h" #include "llvm/PassAnalysisSupport.h" @@ -31,7 +34,6 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" -#include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" @@ -41,30 +43,38 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Support/Timer.h" -#include +#include #include using namespace llvm; +STATISTIC(NumAssigned , "Number of registers assigned"); +STATISTIC(NumUnassigned , "Number of registers unassigned"); +STATISTIC(NumNewQueued , "Number of new live ranges queued"); + static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", createBasicRegisterAllocator); // Temporary verification option until we can put verification inside // MachineVerifier. -static cl::opt -VerifyRegAlloc("verify-regalloc", - cl::desc("Verify live intervals before renaming")); +static cl::opt +VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled), + cl::desc("Verify during register allocation")); -namespace { +const char *RegAllocBase::TimerGroupName = "Register Allocation"; +bool RegAllocBase::VerifyEnabled = false; -class PhysicalRegisterDescription : public AbstractRegisterDescription { - const TargetRegisterInfo *TRI; -public: - PhysicalRegisterDescription(const TargetRegisterInfo *T): TRI(T) {} - virtual const char *getName(unsigned Reg) const { return TRI->getName(Reg); } -}; +namespace { + struct CompSpillWeight { + bool operator()(LiveInterval *A, LiveInterval *B) const { + return A->weight < B->weight; + } + }; +} +namespace { /// RABasic provides a minimal implementation of the basic register allocation /// algorithm. It prioritizes live virtual registers by spill weight and spills /// whenever a register is unavailable. This is not practical in production but @@ -74,10 +84,6 @@ class RABasic : public MachineFunctionPass, public RegAllocBase { // context MachineFunction *MF; - const TargetMachine *TM; - MachineRegisterInfo *MRI; - - BitVector ReservedRegs; // analyses LiveStacks *LS; @@ -85,7 +91,8 @@ class RABasic : public MachineFunctionPass, public RegAllocBase // state std::auto_ptr SpillerInstance; - + std::priority_queue, + CompSpillWeight> Queue; public: RABasic(); @@ -101,6 +108,20 @@ public: virtual Spiller &spiller() { return *SpillerInstance; } + virtual float getPriority(LiveInterval *LI) { return LI->weight; } + + virtual void enqueue(LiveInterval *LI) { + Queue.push(LI); + } + + virtual LiveInterval *dequeue() { + if (Queue.empty()) + return 0; + LiveInterval *LI = Queue.top(); + Queue.pop(); + return LI; + } + virtual unsigned selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl &SplitVRegs); @@ -108,9 +129,6 @@ public: virtual bool runOnMachineFunction(MachineFunction &mf); static char ID; - -private: - void addMBBLiveIns(); }; char RABasic::ID = 0; @@ -118,10 +136,11 @@ char RABasic::ID = 0; } // end anonymous namespace RABasic::RABasic(): MachineFunctionPass(ID) { + initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry()); initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry()); - initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry()); + initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry()); initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); initializeLiveStacksPass(*PassRegistry::getPassRegistry()); initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); @@ -136,9 +155,11 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); AU.addRequired(); AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); if (StrongPHIElim) AU.addRequiredID(StrongPHIEliminationID); - AU.addRequiredTransitive(); + AU.addRequiredTransitiveID(RegisterCoalescerPassID); AU.addRequired(); AU.addRequired(); AU.addPreserved(); @@ -166,8 +187,7 @@ void RegAllocBase::verify() { // Verify disjoint unions. for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { - DEBUG(PhysicalRegisterDescription PRD(TRI); - PhysReg2LiveUnion[PhysReg].dump(&PRD)); + DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI)); LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg]; PhysReg2LiveUnion[PhysReg].verify(VRegs); // Union + intersection test could be done efficiently in one pass, but @@ -198,114 +218,145 @@ void RegAllocBase::verify() { //===----------------------------------------------------------------------===// // Instantiate a LiveIntervalUnion for each physical register. -void RegAllocBase::LiveUnionArray::init(unsigned NRegs) { - Array.reset(new LiveIntervalUnion[NRegs]); +void RegAllocBase::LiveUnionArray::init(LiveIntervalUnion::Allocator &allocator, + unsigned NRegs) { NumRegs = NRegs; - for (unsigned RegNum = 0; RegNum < NRegs; ++RegNum) { - Array[RegNum].init(RegNum); - } + Array = + static_cast(malloc(sizeof(LiveIntervalUnion)*NRegs)); + for (unsigned r = 0; r != NRegs; ++r) + new(Array + r) LiveIntervalUnion(r, allocator); } -void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm, - LiveIntervals &lis) { - TRI = &tri; +void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) { + NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled); + TRI = &vrm.getTargetRegInfo(); + MRI = &vrm.getRegInfo(); VRM = &vrm; LIS = &lis; - PhysReg2LiveUnion.init(TRI->getNumRegs()); - // Cache an interferece query for each physical reg - Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]); + RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); + + const unsigned NumRegs = TRI->getNumRegs(); + if (NumRegs != PhysReg2LiveUnion.numRegs()) { + PhysReg2LiveUnion.init(UnionAllocator, NumRegs); + // Cache an interferece query for each physical reg + Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]); + } } void RegAllocBase::LiveUnionArray::clear() { + if (!Array) + return; + for (unsigned r = 0; r != NumRegs; ++r) + Array[r].~LiveIntervalUnion(); + free(Array); NumRegs = 0; - Array.reset(0); + Array = 0; } void RegAllocBase::releaseMemory() { - PhysReg2LiveUnion.clear(); + for (unsigned r = 0, e = PhysReg2LiveUnion.numRegs(); r != e; ++r) + PhysReg2LiveUnion[r].clear(); } -namespace llvm { -/// This class defines a queue of live virtual registers prioritized by spill -/// weight. The heaviest vreg is popped first. -/// -/// Currently, this is trivial wrapper that gives us an opaque type in the -/// header, but we may later give it a virtual interface for register allocators -/// to override the priority queue comparator. -class LiveVirtRegQueue { - typedef std::priority_queue - , LessSpillWeightPriority> - PriorityQ; - PriorityQ PQ; - -public: - // Is the queue empty? - bool empty() { return PQ.empty(); } - - // Get the highest priority lvr (top + pop) - LiveInterval *get() { - LiveInterval *VirtReg = PQ.top(); - PQ.pop(); - return VirtReg; - } - // Add this lvr to the queue - void push(LiveInterval *VirtReg) { - PQ.push(VirtReg); - } -}; -} // end namespace llvm - -// Visit all the live virtual registers. If they are already assigned to a -// physical register, unify them with the corresponding LiveIntervalUnion, -// otherwise push them on the priority queue for later assignment. -void RegAllocBase::seedLiveVirtRegs(LiveVirtRegQueue &VirtRegQ) { +// Visit all the live registers. If they are already assigned to a physical +// register, unify them with the corresponding LiveIntervalUnion, otherwise push +// them on the priority queue for later assignment. +void RegAllocBase::seedLiveRegs() { + NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled); for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) { unsigned RegNum = I->first; LiveInterval &VirtReg = *I->second; - if (TargetRegisterInfo::isPhysicalRegister(RegNum)) { + if (TargetRegisterInfo::isPhysicalRegister(RegNum)) PhysReg2LiveUnion[RegNum].unify(VirtReg); - } - else { - VirtRegQ.push(&VirtReg); - } + else + enqueue(&VirtReg); } } +void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) { + DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) + << " to " << PrintReg(PhysReg, TRI) << '\n'); + assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); + VRM->assignVirt2Phys(VirtReg.reg, PhysReg); + MRI->setPhysRegUsed(PhysReg); + PhysReg2LiveUnion[PhysReg].unify(VirtReg); + ++NumAssigned; +} + +void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) { + DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) + << " from " << PrintReg(PhysReg, TRI) << '\n'); + assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign"); + PhysReg2LiveUnion[PhysReg].extract(VirtReg); + VRM->clearVirt(VirtReg.reg); + ++NumUnassigned; +} + // Top-level driver to manage the queue of unassigned VirtRegs and call the // selectOrSplit implementation. void RegAllocBase::allocatePhysRegs() { - - // Push each vreg onto a queue or "precolor" by adding it to a physreg union. - LiveVirtRegQueue VirtRegQ; - seedLiveVirtRegs(VirtRegQ); + seedLiveRegs(); // Continue assigning vregs one at a time to available physical registers. - while (!VirtRegQ.empty()) { - // Pop the highest priority vreg. - LiveInterval *VirtReg = VirtRegQ.get(); + while (LiveInterval *VirtReg = dequeue()) { + assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); + + // Unused registers can appear when the spiller coalesces snippets. + if (MRI->reg_nodbg_empty(VirtReg->reg)) { + DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); + LIS->removeInterval(VirtReg->reg); + continue; + } + + // Invalidate all interference queries, live ranges could have changed. + invalidateVirtRegs(); // selectOrSplit requests the allocator to return an available physical // register if possible and populate a list of new live intervals that // result from splitting. + DEBUG(dbgs() << "\nselectOrSplit " + << MRI->getRegClass(VirtReg->reg)->getName() + << ':' << *VirtReg << '\n'); typedef SmallVector VirtRegVec; VirtRegVec SplitVRegs; unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); - if (AvailablePhysReg) { - DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg) << - " " << *VirtReg << '\n'); - assert(!VRM->hasPhys(VirtReg->reg) && "duplicate vreg in union"); - VRM->assignVirt2Phys(VirtReg->reg, AvailablePhysReg); - PhysReg2LiveUnion[AvailablePhysReg].unify(*VirtReg); + if (AvailablePhysReg == ~0u) { + // selectOrSplit failed to find a register! + const char *Msg = "ran out of registers during register allocation"; + // Probably caused by an inline asm. + MachineInstr *MI; + for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg); + (MI = I.skipInstruction());) + if (MI->isInlineAsm()) + break; + if (MI) + MI->emitError(Msg); + else + report_fatal_error(Msg); + // Keep going after reporting the error. + VRM->assignVirt2Phys(VirtReg->reg, + RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); + continue; } + + if (AvailablePhysReg) + assign(*VirtReg, AvailablePhysReg); + for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end(); I != E; ++I) { - LiveInterval* SplitVirtReg = *I; - if (SplitVirtReg->empty()) continue; + LiveInterval *SplitVirtReg = *I; + assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned"); + if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) { + DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n'); + LIS->removeInterval(SplitVirtReg->reg); + continue; + } DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n"); assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) && "expect split value in virtual register"); - VirtRegQ.push(SplitVirtReg); + enqueue(SplitVirtReg); + ++NumNewQueued; } } } @@ -315,12 +366,9 @@ void RegAllocBase::allocatePhysRegs() { // physical register. Return the interfering register. unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg, unsigned PhysReg) { - if (query(VirtReg, PhysReg).checkInterference()) - return PhysReg; - for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) { + for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) if (query(VirtReg, *AliasI).checkInterference()) return *AliasI; - } return 0; } @@ -340,13 +388,11 @@ void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg, // Deallocate the interfering vreg by removing it from the union. // A LiveInterval instance may not be in a union during modification! - PhysReg2LiveUnion[PhysReg].extract(SpilledVReg); - - // Clear the vreg assignment. - VRM->clearVirt(SpilledVReg.reg); + unassign(SpilledVReg, PhysReg); // Spill the extracted interval. - spiller().spill(&SpilledVReg, SplitVRegs, PendingSpills); + LiveRangeEdit LRE(SpilledVReg, SplitVRegs, 0, &PendingSpills); + spiller().spill(LRE); } // After extracting segments, the query's results are invalid. But keep the // contents valid until we're done accessing pendingSpills. @@ -361,15 +407,9 @@ RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, SmallVectorImpl &SplitVRegs) { // Record each interference and determine if all are spillable before mutating // either the union or live intervals. - - // Collect interferences assigned to the requested physical register. - LiveIntervalUnion::Query &QPreg = query(VirtReg, PhysReg); - unsigned NumInterferences = QPreg.collectInterferingVRegs(); - if (QPreg.seenUnspillableVReg()) { - return false; - } + unsigned NumInterferences = 0; // Collect interferences assigned to any alias of the physical register. - for (const unsigned *asI = TRI->getAliasSet(PhysReg); *asI; ++asI) { + for (const unsigned *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) { LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI); NumInterferences += QAlias.collectInterferingVRegs(); if (QAlias.seenUnspillableVReg()) { @@ -381,12 +421,48 @@ RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, assert(NumInterferences > 0 && "expect interference"); // Spill each interfering vreg allocated to PhysReg or an alias. - spillReg(VirtReg, PhysReg, SplitVRegs); - for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) + for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) spillReg(VirtReg, *AliasI, SplitVRegs); return true; } +// Add newly allocated physical registers to the MBB live in sets. +void RegAllocBase::addMBBLiveIns(MachineFunction *MF) { + NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled); + SlotIndexes *Indexes = LIS->getSlotIndexes(); + if (MF->size() <= 1) + return; + + LiveIntervalUnion::SegmentIter SI; + for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { + LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg]; + if (LiveUnion.empty()) + continue; + DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " live-in:"); + MachineFunction::iterator MBB = llvm::next(MF->begin()); + MachineFunction::iterator MFE = MF->end(); + SlotIndex Start, Stop; + tie(Start, Stop) = Indexes->getMBBRange(MBB); + SI.setMap(LiveUnion.getMap()); + SI.find(Start); + while (SI.valid()) { + if (SI.start() <= Start) { + if (!MBB->isLiveIn(PhysReg)) + MBB->addLiveIn(PhysReg); + DEBUG(dbgs() << "\tBB#" << MBB->getNumber() << ':' + << PrintReg(SI.value()->reg, TRI)); + } else if (SI.start() > Stop) + MBB = Indexes->getMBBFromIndex(SI.start().getPrevIndex()); + if (++MBB == MFE) + break; + tie(Start, Stop) = Indexes->getMBBRange(MBB); + SI.advanceTo(Start); + } + DEBUG(dbgs() << '\n'); + } +} + + //===----------------------------------------------------------------------===// // RABasic Implementation //===----------------------------------------------------------------------===// @@ -409,15 +485,11 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, SmallVector PhysRegSpillCands; // Check for an available register in this class. - const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg); - DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' '); - - for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF), - E = TRC->allocation_order_end(*MF); - I != E; ++I) { - + ArrayRef Order = + RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg)); + for (ArrayRef::iterator I = Order.begin(), E = Order.end(); I != E; + ++I) { unsigned PhysReg = *I; - if (ReservedRegs.test(PhysReg)) continue; // Check interference and as a side effect, intialize queries for this // VirtReg and its aliases. @@ -426,97 +498,54 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, // Found an available register. return PhysReg; } + Queries[interfReg].collectInterferingVRegs(1); LiveInterval *interferingVirtReg = - Queries[interfReg].firstInterference().liveUnionPos()->VirtReg; + Queries[interfReg].interferingVRegs().front(); - // The current VirtReg must either spillable, or one of its interferences + // The current VirtReg must either be spillable, or one of its interferences // must have less spill weight. if (interferingVirtReg->weight < VirtReg.weight ) { PhysRegSpillCands.push_back(PhysReg); } } // Try to spill another interfering reg with less spill weight. - // - // FIXME: RAGreedy will sort this list by spill weight. for (SmallVectorImpl::iterator PhysRegI = PhysRegSpillCands.begin(), PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) { if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue; - unsigned InterferingReg = checkPhysRegInterference(VirtReg, *PhysRegI); - if (InterferingReg != 0) { - const LiveSegment &seg = - *Queries[InterferingReg].firstInterference().liveUnionPos(); - - dbgs() << "spilling cannot free " << TRI->getName(*PhysRegI) << - " for " << VirtReg.reg << " with interference " << *seg.VirtReg << "\n"; - llvm_unreachable("Interference after spill."); - } + assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 && + "Interference after spill."); // Tell the caller to allocate to this newly freed physical register. return *PhysRegI; } + // No other spill candidates were found, so spill the current VirtReg. DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); - SmallVector pendingSpills; - - spiller().spill(&VirtReg, SplitVRegs, pendingSpills); + if (!VirtReg.isSpillable()) + return ~0u; + LiveRangeEdit LRE(VirtReg, SplitVRegs); + spiller().spill(LRE); // The live virtual register requesting allocation was spilled, so tell // the caller not to allocate anything during this round. return 0; } -// Add newly allocated physical registers to the MBB live in sets. -void RABasic::addMBBLiveIns() { - typedef SmallVector MBBVec; - MBBVec liveInMBBs; - MachineBasicBlock &entryMBB = *MF->begin(); - - for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { - LiveIntervalUnion &LiveUnion = PhysReg2LiveUnion[PhysReg]; - - for (LiveIntervalUnion::SegmentIter SI = LiveUnion.begin(), - SegEnd = LiveUnion.end(); - SI != SegEnd; ++SI) { - - // Find the set of basic blocks which this range is live into... - liveInMBBs.clear(); - if (!LIS->findLiveInMBBs(SI->Start, SI->End, liveInMBBs)) continue; - - // And add the physreg for this interval to their live-in sets. - for (MBBVec::iterator I = liveInMBBs.begin(), E = liveInMBBs.end(); - I != E; ++I) { - MachineBasicBlock *MBB = *I; - if (MBB == &entryMBB) continue; - if (MBB->isLiveIn(PhysReg)) continue; - MBB->addLiveIn(PhysReg); - } - } - } -} - bool RABasic::runOnMachineFunction(MachineFunction &mf) { DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n" << "********** Function: " << ((Value*)mf.getFunction())->getName() << '\n'); MF = &mf; - TM = &mf.getTarget(); - MRI = &mf.getRegInfo(); - DEBUG(RMF = &getAnalysis()); - const TargetRegisterInfo *TRI = TM->getRegisterInfo(); - RegAllocBase::init(*TRI, getAnalysis(), - getAnalysis()); - - ReservedRegs = TRI->getReservedRegs(*MF); - - SpillerInstance.reset(createSpiller(*this, *MF, *VRM)); + RegAllocBase::init(getAnalysis(), getAnalysis()); + SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); allocatePhysRegs(); - addMBBLiveIns(); + addMBBLiveIns(MF); // Diagnostic output before rewriting DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n"); @@ -528,7 +557,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) { // make the rewriter a separate pass and override verifyAnalysis instead. When // that happens, verification naturally falls under VerifyMachineCode. #ifndef NDEBUG - if (VerifyRegAlloc) { + if (VerifyEnabled) { // Verify accuracy of LiveIntervals. The standard machine code verifier // ensures that each LiveIntervals covers all uses of the virtual reg. @@ -536,7 +565,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) { // spiller. Always use -spiller=inline with -verify-regalloc. Even with the // inline spiller, some tests fail to verify because the coalescer does not // always generate verifiable code. - MF->verify(this); + MF->verify(this, "In RABasic::verify"); // Verify that LiveIntervals are partitioned into unions and disjoint within // the unions. @@ -545,8 +574,10 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) { #endif // !NDEBUG // Run rewriter - std::auto_ptr rewriter(createVirtRegRewriter()); - rewriter->runOnMachineFunction(*MF, *VRM, LIS); + VRM->rewrite(LIS->getSlotIndexes()); + + // Write out new DBG_VALUE instructions. + getAnalysis().emitDebugValues(VRM); // The pass output is in VirtRegMap. Release all the transient data. releaseMemory();