X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocBigBlock.cpp;h=83c9ceb37b0770ff9c3757770bc80bd2e1077e53;hb=ee888132754c709de8d2e2c5ef85531a15ed44f2;hp=e2f160f39eaabf60a594e246f0353b313d298824;hpb=669f7382be6a45d619873dcc46094c7b23fe89f3;p=oota-llvm.git

diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp
index e2f160f39ea..83c9ceb37b0 100644
--- a/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/lib/CodeGen/RegAllocBigBlock.cpp
@@ -47,7 +47,6 @@
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/Statistic.h"
 #include <algorithm>
-#include <iostream>
 using namespace llvm;
 
 STATISTIC(NumStores, "Number of stores added");
@@ -64,6 +63,7 @@ namespace {
   struct VRegKeyInfo {
     static inline unsigned getEmptyKey() { return -1U; }
     static inline unsigned getTombstoneKey() { return -2U; }
+    static bool isEqual(unsigned LHS, unsigned RHS) { return LHS == RHS; }
     static unsigned getHashValue(const unsigned &Key) { return Key; }
   };
 
@@ -329,7 +329,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
     const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
     int FrameIndex = getStackSpaceFor(VirtReg, RC);
     DOUT << " to stack slot #" << FrameIndex;
-    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
+    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
     ++NumStores;   // Update statistics
   }
 
@@ -461,8 +461,22 @@ unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I,
       }
     }
 
-    assert(PhysReg && "couldn't assign a physical register :( ");
-    // TODO: assert that RC->contains(PhysReg) / handle aliased registers
+    if(PhysReg == 0) { // ok, now we're desperate. We couldn't choose
+                       // a register to spill by looking through the
+                       // read timetable, so now we just spill the
+                       // first allocatable register we find.
+                       
+      // for all physical regs in the RC,
+      for(TargetRegisterClass::iterator pReg = RC->begin(); 
+                                        pReg != RC->end();  ++pReg) {
+        // if we find a register we can spill
+        if(PhysRegsUsed[*pReg]>=-1)
+          PhysReg = *pReg; // choose it to be spilled
+      }
+    }
+    
+    assert(PhysReg && "couldn't choose a register to spill :( ");
+    // TODO: assert that RC->contains(PhysReg) / handle aliased registers?
 
     // since we needed to look in the table we need to spill this register.
     spillPhysReg(MBB, I, PhysReg);
@@ -506,7 +520,9 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
     assignVirtToPhysReg(VirtReg, PhysReg);
   } else {  // no free registers available.
     // try to fold the spill into the instruction
-    if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, OpNum, FrameIndex)) {
+    SmallVector<unsigned, 2> Ops;
+    Ops.push_back(OpNum);
+    if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, Ops, FrameIndex)) {
       ++NumFolded;
       // Since we changed the address of MI, make sure to update live variables
       // to know that the new instruction has the properties of the old one.
@@ -596,6 +612,7 @@ static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) {
   return false;
 }
 
+
 void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
   // loop over each instruction
   MachineBasicBlock::iterator MII = MBB.begin();
@@ -623,10 +640,12 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
   }
   
   // Otherwise, sequentially allocate each instruction in the MBB.
+  MBBCurTime = -1;
   while (MII != MBB.end()) {
     MachineInstr *MI = MII++;
+    MBBCurTime++;
     const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
-    DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
+    DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI;
           DOUT << "  Regs have values: ";
           for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
             if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
@@ -634,16 +653,6 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
                     << ",%reg" << PhysRegsUsed[i] << "] ";
           DOUT << "\n");
 
-/* XXX : 
-    // Loop over the implicit uses, making sure that they are at the head of the
-    // use order list, so they don't get reallocated.
-    if (TID.ImplicitUses) {
-      for (const unsigned *ImplicitUses = TID.ImplicitUses;
-           *ImplicitUses; ++ImplicitUses)
-        MarkPhysRegRecentlyUsed(*ImplicitUses);
-    }
- XXX */
-
     SmallVector<unsigned, 8> Kills;
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand& MO = MI->getOperand(i);
@@ -725,12 +734,11 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
         MF->setPhysRegUsed(Reg);
         spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
         PhysRegsUsed[Reg] = 0;            // It is free and reserved now
-
         for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
              *AliasSet; ++AliasSet) {
           if (PhysRegsUsed[*AliasSet] != -2) {
-            MF->setPhysRegUsed(*AliasSet);
             PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
+            MF->setPhysRegUsed(*AliasSet);
           }
         }
       }