X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocBigBlock.cpp;h=f29b45eb142ec8be56c353bc4e4b4a3fbd1b6abc;hb=63e3cd4e0f3731d6801ac24199652e4d7b4b3729;hp=5c894729a7e88fbdb58b7b7fd3c01d46efb2122c;hpb=84bc5427d6883f73cfeae3da640acd011d35c006;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp index 5c894729a7e..f29b45eb142 100644 --- a/lib/CodeGen/RegAllocBigBlock.cpp +++ b/lib/CodeGen/RegAllocBigBlock.cpp @@ -44,7 +44,6 @@ #include "llvm/ADT/IndexedMap.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/Statistic.h" #include using namespace llvm; @@ -95,11 +94,7 @@ namespace { /// RegInfo - For dealing with machine register info (aliases, folds /// etc) - const MRegisterInfo *RegInfo; - - /// LV - Our generic LiveVariables pointer - /// - LiveVariables *LV; + const TargetRegisterInfo *RegInfo; typedef SmallVector VRegTimes; @@ -156,8 +151,8 @@ namespace { /// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset /// void markVirtRegModified(unsigned Reg, bool Val = true) { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - Reg -= MRegisterInfo::FirstVirtualRegister; + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + Reg -= TargetRegisterInfo::FirstVirtualRegister; if (VirtRegModified.size() <= Reg) VirtRegModified.resize(Reg+1); VirtRegModified[Reg] = Val; @@ -166,10 +161,10 @@ namespace { /// isVirtRegModified - Lets us query the VirtRegModified bitset /// bool isVirtRegModified(unsigned Reg) const { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size() + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size() && "Illegal virtual register!"); - return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; + return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister]; } public: @@ -182,7 +177,6 @@ namespace { /// getAnalaysisUsage - declares the required analyses /// virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); AU.addRequiredID(PHIEliminationID); AU.addRequiredID(TwoAddressInstructionPassID); MachineFunctionPass::getAnalysisUsage(AU); @@ -319,6 +313,9 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB, " the intended one."); DOUT << " Spilling register " << RegInfo->getName(PhysReg) << " containing %reg" << VirtReg; + + const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo(); + if (!isVirtRegModified(VirtReg)) DOUT << " which has not been modified, so no store necessary!"; @@ -329,7 +326,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB, const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); DOUT << " to stack slot #" << FrameIndex; - RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC); + TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC); ++NumStores; // Update statistics } @@ -502,6 +499,7 @@ unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I, MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, unsigned OpNum) { unsigned VirtReg = MI->getOperand(OpNum).getReg(); + const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo(); // If the virtual register is already available in a physical register, // just update the instruction and return. @@ -522,11 +520,9 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI // try to fold the spill into the instruction SmallVector Ops; Ops.push_back(OpNum); - if(MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, Ops, FrameIndex)) { + if(MachineInstr* FMI = TII->foldMemoryOperand(*MF, MI, Ops, FrameIndex)) { ++NumFolded; - // Since we changed the address of MI, make sure to update live variables - // to know that the new instruction has the properties of the old one. - LV->instructionChanged(MI, FMI); + FMI->copyKillDeadInfo(MI); return MBB.insert(MBB.erase(MI), FMI); } @@ -542,7 +538,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI << RegInfo->getName(PhysReg) << "\n"; // Add move instruction(s) - RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); + TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); ++NumLoads; // Update statistics MF->getRegInfo().setPhysRegUsed(PhysReg); @@ -565,7 +561,7 @@ void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) { MachineOperand& MO = MI->getOperand(i); // look for vreg reads.. if (MO.isRegister() && !MO.isDef() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { // ..and add them to the read table. VRegTimes* &Times = VRegReadTable[MO.getReg()]; if(!VRegReadTable[MO.getReg()]) { @@ -645,7 +641,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { while (MII != MBB.end()) { MachineInstr *MI = MII++; MBBCurTime++; - const TargetInstrDescriptor &TID = TII.get(MI->getOpcode()); + const TargetInstrDesc &TID = MI->getDesc(); DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI; DOUT << " Regs have values: "; for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) @@ -678,7 +674,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { MachineOperand& MO = MI->getOperand(i); // here we are looking for only used operands (never def&use) if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && - MRegisterInfo::isVirtualRegister(MO.getReg())) + TargetRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); } @@ -689,7 +685,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = Kills.size(); i != e; ++i) { unsigned VirtReg = Kills[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { // If the virtual register was never materialized into a register, it // might not be in the map, but it won't hurt to zero it out anyway. unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); @@ -724,7 +720,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && - MRegisterInfo::isPhysicalRegister(MO.getReg())) { + TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. // These are extra physical register defs when a sub-register @@ -746,8 +742,8 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { } // Loop over the implicit defs, spilling them as well. - if (TID.ImplicitDefs) { - for (const unsigned *ImplicitDefs = TID.ImplicitDefs; + if (TID.getImplicitDefs()) { + for (const unsigned *ImplicitDefs = TID.getImplicitDefs(); *ImplicitDefs; ++ImplicitDefs) { unsigned Reg = *ImplicitDefs; if (PhysRegsUsed[Reg] != -2) { @@ -780,7 +776,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); unsigned DestPhysReg; @@ -799,7 +795,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { unsigned VirtReg = DeadDefs[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); PhysReg = PhysRegSlot; assert(PhysReg != 0); @@ -828,11 +824,8 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { // Finally, if this is a noop copy instruction, zap it. unsigned SrcReg, DstReg; - if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) { - LV->removeVirtualRegistersKilled(MI); - LV->removeVirtualRegistersDead(MI); + if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) MBB.erase(MI); - } } MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); @@ -853,7 +846,6 @@ bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) { MF = &Fn; TM = &Fn.getTarget(); RegInfo = TM->getRegisterInfo(); - LV = &getAnalysis(); PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); @@ -872,7 +864,7 @@ bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) { Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg()); StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg()); VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() - - MRegisterInfo::FirstVirtualRegister + 1, 0); + TargetRegisterInfo::FirstVirtualRegister + 1, 0); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();