X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocLinearScan.cpp;h=c70ff9524328d237e0eb48f85cc097c3446c1c22;hb=420cdebbcb95f3881ab3518fd3bb670837669e43;hp=025de81aa934a7e1f22f8315cbb67f886542f2fd;hpb=10136e7c7f599a559917e04f04e6dfbf025e451b;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 025de81aa93..c70ff952432 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -18,12 +18,14 @@ #include "llvm/Function.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegisterCoalescer.h" -#include "llvm/CodeGen/SSARegMap.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/ADT/EquivalenceClasses.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" @@ -38,15 +40,13 @@ using namespace llvm; STATISTIC(NumIters , "Number of iterations performed"); STATISTIC(NumBacktracks, "Number of times we had to backtrack"); +STATISTIC(NumCoalesce, "Number of copies coalesced"); static RegisterRegAlloc linearscanRegAlloc("linearscan", " linear scan register allocator", createLinearScanRegisterAllocator); namespace { - static unsigned numIterations = 0; - static unsigned numIntervals = 0; - struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass { static char ID; RALinScan() : MachineFunctionPass((intptr_t)&ID) {} @@ -62,8 +62,12 @@ namespace { MachineFunction* mf_; const TargetMachine* tm_; - const MRegisterInfo* mri_; + const TargetRegisterInfo* tri_; + const TargetInstrInfo* tii_; + MachineRegisterInfo *reginfo_; + BitVector allocatableRegs_; LiveIntervals* li_; + const MachineLoopInfo *loopInfo; /// handled_ - Intervals are added to the handled_ set in the order of their /// start value. This is uses for backtracking. @@ -99,6 +103,9 @@ namespace { // Make sure PassManager knows which analyses to make available // to coalescing and which analyses coalescing invalidates. AU.addRequiredTransitive(); + AU.addRequired(); + AU.addPreserved(); + AU.addPreservedID(MachineDominatorsID); MachineFunctionPass::getAnalysisUsage(AU); } @@ -125,6 +132,15 @@ namespace { /// is available, or spill. void assignRegOrStackSlotAtInterval(LiveInterval* cur); + /// attemptTrivialCoalescing - If a simple interval is defined by a copy, + /// try allocate the definition the same register as the source register + /// if the register is not defined during live time of the interval. This + /// eliminate a copy. This is used to coalesce copies which were not + /// coalesced away before allocation either due to dest and src being in + /// different register classes or because the coalescer was overly + /// conservative. + unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg); + /// /// register handling helpers /// @@ -145,10 +161,10 @@ namespace { for (; i != e; ++i) { DOUT << "\t" << *i->first << " -> "; unsigned reg = i->first->reg; - if (MRegisterInfo::isVirtualRegister(reg)) { + if (TargetRegisterInfo::isVirtualRegister(reg)) { reg = vrm_->getPhys(reg); } - DOUT << mri_->getName(reg) << '\n'; + DOUT << tri_->getName(reg) << '\n'; } } }; @@ -156,17 +172,17 @@ namespace { } void RALinScan::ComputeRelatedRegClasses() { - const MRegisterInfo &MRI = *mri_; + const TargetRegisterInfo &TRI = *tri_; // First pass, add all reg classes to the union, and determine at least one // reg class that each register is in. bool HasAliases = false; - for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(), - E = MRI.regclass_end(); RCI != E; ++RCI) { + for (TargetRegisterInfo::regclass_iterator RCI = TRI.regclass_begin(), + E = TRI.regclass_end(); RCI != E; ++RCI) { RelatedRegClasses.insert(*RCI); for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end(); I != E; ++I) { - HasAliases = HasAliases || *MRI.getAliasSet(*I) != 0; + HasAliases = HasAliases || *TRI.getAliasSet(*I) != 0; const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I]; if (PRC) { @@ -186,15 +202,61 @@ void RALinScan::ComputeRelatedRegClasses() { for (std::map::iterator I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end(); I != E; ++I) - for (const unsigned *AS = MRI.getAliasSet(I->first); *AS; ++AS) + for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS) RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]); } +/// attemptTrivialCoalescing - If a simple interval is defined by a copy, +/// try allocate the definition the same register as the source register +/// if the register is not defined during live time of the interval. This +/// eliminate a copy. This is used to coalesce copies which were not +/// coalesced away before allocation either due to dest and src being in +/// different register classes or because the coalescer was overly +/// conservative. +unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { + if ((cur.preference && cur.preference == Reg) || !cur.containsOneValue()) + return Reg; + + VNInfo *vni = cur.getValNumInfo(0); + if (!vni->def || vni->def == ~1U || vni->def == ~0U) + return Reg; + MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); + unsigned SrcReg, DstReg; + if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) + return Reg; + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) + if (!vrm_->isAssignedReg(SrcReg)) + return Reg; + else + SrcReg = vrm_->getPhys(SrcReg); + if (Reg == SrcReg) + return Reg; + + const TargetRegisterClass *RC = reginfo_->getRegClass(cur.reg); + if (!RC->contains(SrcReg)) + return Reg; + + // Try to coalesce. + if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) { + DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg) << '\n'; + vrm_->clearVirt(cur.reg); + vrm_->assignVirt2Phys(cur.reg, SrcReg); + ++NumCoalesce; + return SrcReg; + } + + return Reg; +} + bool RALinScan::runOnMachineFunction(MachineFunction &fn) { mf_ = &fn; tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); + tri_ = tm_->getRegisterInfo(); + tii_ = tm_->getInstrInfo(); + reginfo_ = &mf_->getRegInfo(); + allocatableRegs_ = tri_->getAllocatableSet(fn); li_ = &getAnalysis(); + loopInfo = &getAnalysis(); // We don't run the coalescer here because we have no reason to // interact with it. If the coalescer requires interaction, it @@ -205,7 +267,7 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) { if (RelatedRegClasses.empty()) ComputeRelatedRegClasses(); - if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_)); + if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_)); vrm_.reset(new VirtRegMap(*mf_)); if (!spiller_.get()) spiller_.reset(createSpiller()); @@ -235,8 +297,8 @@ void RALinScan::initIntervalSets() "interval sets should be empty on initialization"); for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) { - if (MRegisterInfo::isPhysicalRegister(i->second.reg)) { - mf_->setPhysRegUsed(i->second.reg); + if (TargetRegisterInfo::isPhysicalRegister(i->second.reg)) { + reginfo_->setPhysRegUsed(i->second.reg); fixed_.push_back(std::make_pair(&i->second, i->second.begin())); } else unhandled_.push(&i->second); @@ -249,22 +311,19 @@ void RALinScan::linearScan() DOUT << "********** LINEAR SCAN **********\n"; DOUT << "********** Function: " << mf_->getFunction()->getName() << '\n'; - // DEBUG(printIntervals("unhandled", unhandled_.begin(), unhandled_.end())); DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end())); - DEBUG(printIntervals("active", active_.begin(), active_.end())); - DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end())); while (!unhandled_.empty()) { // pick the interval with the earliest start point LiveInterval* cur = unhandled_.top(); unhandled_.pop(); - ++numIterations; + ++NumIters; DOUT << "\n*** CURRENT ***: " << *cur << '\n'; processActiveIntervals(cur->beginNumber()); processInactiveIntervals(cur->beginNumber()); - assert(MRegisterInfo::isVirtualRegister(cur->reg) && + assert(TargetRegisterInfo::isVirtualRegister(cur->reg) && "Can only allocate virtual registers!"); // Allocating a virtual register. try to find a free @@ -275,45 +334,49 @@ void RALinScan::linearScan() DEBUG(printIntervals("active", active_.begin(), active_.end())); DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end())); } - numIntervals += li_->getNumIntervals(); - NumIters += numIterations; // expire any remaining active intervals - for (IntervalPtrs::reverse_iterator - i = active_.rbegin(); i != active_.rend(); ) { - unsigned reg = i->first->reg; - DOUT << "\tinterval " << *i->first << " expired\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + while (!active_.empty()) { + IntervalPtr &IP = active_.back(); + unsigned reg = IP.first->reg; + DOUT << "\tinterval " << *IP.first << " expired\n"; + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); - i = IntervalPtrs::reverse_iterator(active_.erase(i.base()-1)); + active_.pop_back(); } // expire any remaining inactive intervals - for (IntervalPtrs::reverse_iterator - i = inactive_.rbegin(); i != inactive_.rend(); ) { - DOUT << "\tinterval " << *i->first << " expired\n"; - i = IntervalPtrs::reverse_iterator(inactive_.erase(i.base()-1)); - } + DEBUG(for (IntervalPtrs::reverse_iterator + i = inactive_.rbegin(); i != inactive_.rend(); ++i) + DOUT << "\tinterval " << *i->first << " expired\n"); + inactive_.clear(); - // A brute force way of adding live-ins to every BB. - MachineFunction::iterator MBB = mf_->begin(); - ++MBB; // Skip entry MBB. - for (MachineFunction::iterator E = mf_->end(); MBB != E; ++MBB) { - unsigned StartIdx = li_->getMBBStartIdx(MBB->getNumber()); - for (IntervalPtrs::iterator i = fixed_.begin(), e = fixed_.end(); - i != e; ++i) - if (i->first->liveAt(StartIdx)) - MBB->addLiveIn(i->first->reg); - - for (unsigned i = 0, e = handled_.size(); i != e; ++i) { - LiveInterval *HI = handled_[i]; - unsigned Reg = HI->reg; - if (vrm_->isAssignedReg(Reg) && HI->liveAt(StartIdx)) { - assert(MRegisterInfo::isVirtualRegister(Reg)); - Reg = vrm_->getPhys(Reg); - MBB->addLiveIn(Reg); + // Add live-ins to every BB except for entry. Also perform trivial coalescing. + MachineFunction::iterator EntryMBB = mf_->begin(); + SmallVector LiveInMBBs; + for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) { + LiveInterval &cur = i->second; + unsigned Reg = 0; + bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg); + if (isPhys) + Reg = i->second.reg; + else if (vrm_->isAssignedReg(cur.reg)) + Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg)); + if (!Reg) + continue; + // Ignore splited live intervals. + if (!isPhys && vrm_->getPreSplitReg(cur.reg)) + continue; + for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end(); + I != E; ++I) { + const LiveRange &LR = *I; + if (li_->findLiveInMBBs(LR, LiveInMBBs)) { + for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i) + if (LiveInMBBs[i] != EntryMBB) + LiveInMBBs[i]->addLiveIn(Reg); + LiveInMBBs.clear(); } } } @@ -336,7 +399,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint) if (IntervalPos == Interval->end()) { // Remove expired intervals. DOUT << "\t\tinterval " << *Interval << " expired\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); @@ -349,7 +412,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint) } else if (IntervalPos->start > CurPoint) { // Move inactive intervals to inactive list. DOUT << "\t\tinterval " << *Interval << " inactive\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); @@ -390,7 +453,7 @@ void RALinScan::processInactiveIntervals(unsigned CurPoint) } else if (IntervalPos->start <= CurPoint) { // move re-activated intervals in active list DOUT << "\t\tinterval " << *Interval << " active\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->addRegUse(reg); @@ -412,9 +475,9 @@ void RALinScan::processInactiveIntervals(unsigned CurPoint) /// register and its weight. static void updateSpillWeights(std::vector &Weights, unsigned reg, float weight, - const MRegisterInfo *MRI) { + const TargetRegisterInfo *TRI) { Weights[reg] += weight; - for (const unsigned* as = MRI->getAliasSet(reg); *as; ++as) + for (const unsigned* as = TRI->getAliasSet(reg); *as; ++as) Weights[*as] += weight; } @@ -447,17 +510,39 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) std::vector > SpillWeightsToAdd; unsigned StartPosition = cur->beginNumber(); - const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(cur->reg); + const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg); const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC); - + + // If this live interval is defined by a move instruction and its source is + // assigned a physical register that is compatible with the target register + // class, then we should try to assign it the same register. + // This can happen when the move is from a larger register class to a smaller + // one, e.g. X86::mov32to32_. These move instructions are not coalescable. + if (!cur->preference && cur->containsOneValue()) { + VNInfo *vni = cur->getValNumInfo(0); + if (vni->def && vni->def != ~1U && vni->def != ~0U) { + MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); + unsigned SrcReg, DstReg; + if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { + unsigned Reg = 0; + if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) + Reg = SrcReg; + else if (vrm_->isAssignedReg(SrcReg)) + Reg = vrm_->getPhys(SrcReg); + if (Reg && allocatableRegs_[Reg] && RC->contains(Reg)) + cur->preference = Reg; + } + } + } + // for every interval in inactive we overlap with, mark the // register as not free and update spill weights. for (IntervalPtrs::const_iterator i = inactive_.begin(), e = inactive_.end(); i != e; ++i) { unsigned Reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(Reg) && + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Can only allocate virtual registers!"); - const TargetRegisterClass *RegRC = mf_->getSSARegMap()->getRegClass(Reg); + const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg); // If this is not in a related reg class to the register we're allocating, // don't check it. if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader && @@ -478,8 +563,8 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) // We got a register. However, if it's in the fixed_ list, we might // conflict with it. Check to see if we conflict with it or any of its // aliases. - std::set RegAliases; - for (const unsigned *AS = mri_->getAliasSet(physReg); *AS; ++AS) + SmallSet RegAliases; + for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS) RegAliases.insert(*AS); bool ConflictsWithFixed = false; @@ -541,7 +626,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) // the free physical register and add this interval to the active // list. if (physReg) { - DOUT << mri_->getName(physReg) << '\n'; + DOUT << tri_->getName(physReg) << '\n'; vrm_->assignVirt2Phys(cur->reg, physReg); prt_->addRegUse(physReg); active_.push_back(std::make_pair(cur, cur->begin())); @@ -551,19 +636,19 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) DOUT << "no free registers\n"; // Compile the spill weights into an array that is better for scanning. - std::vector SpillWeights(mri_->getNumRegs(), 0.0); + std::vector SpillWeights(tri_->getNumRegs(), 0.0); for (std::vector >::iterator I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I) - updateSpillWeights(SpillWeights, I->first, I->second, mri_); + updateSpillWeights(SpillWeights, I->first, I->second, tri_); // for each interval in active, update spill weights. for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end(); i != e; ++i) { unsigned reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); - updateSpillWeights(SpillWeights, reg, i->first->weight, mri_); + updateSpillWeights(SpillWeights, reg, i->first->weight, tri_); } DOUT << "\tassigning stack slot at interval "<< *cur << ":\n"; @@ -589,7 +674,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) unsigned reg = *i; // No need to worry about if the alias register size < regsize of RC. // We are going to spill all registers that alias it anyway. - for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as) { + for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) { if (minWeight > SpillWeights[*as]) { minWeight = SpillWeights[*as]; minReg = *as; @@ -603,7 +688,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) } DOUT << "\t\tregister with min weight: " - << mri_->getName(minReg) << " (" << minWeight << ")\n"; + << tri_->getName(minReg) << " (" << minWeight << ")\n"; // if the current has the minimum weight, we need to spill it and // add any added intervals back to unhandled, and restart @@ -611,7 +696,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) if (cur->weight != HUGE_VALF && cur->weight <= minWeight) { DOUT << "\t\t\tspilling(c): " << *cur << '\n'; std::vector added = - li_->addIntervalsForSpills(*cur, *vrm_, cur->reg); + li_->addIntervalsForSpills(*cur, loopInfo, *vrm_); if (added.empty()) return; // Early exit if all spills were folded. @@ -634,13 +719,13 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) // minimum weight, rollback to the interval with the earliest // start point and let the linear scan algorithm run again std::vector added; - assert(MRegisterInfo::isPhysicalRegister(minReg) && + assert(TargetRegisterInfo::isPhysicalRegister(minReg) && "did not choose a register to spill?"); - BitVector toSpill(mri_->getNumRegs()); + BitVector toSpill(tri_->getNumRegs()); // We are going to spill minReg and all its aliases. toSpill[minReg] = true; - for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as) + for (const unsigned* as = tri_->getAliasSet(minReg); *as; ++as) toSpill[*as] = true; // the earliest start of a spilled interval indicates up to where @@ -648,7 +733,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) unsigned earliestStart = cur->beginNumber(); // set of spilled vregs (used later to rollback properly) - std::set spilled; + SmallSet spilled; // spill live intervals of virtual regs mapped to the physical register we // want to clear (and its aliases). We only spill those that overlap with the @@ -657,26 +742,26 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) // mark our rollback point. for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) { unsigned reg = i->first->reg; - if (//MRegisterInfo::isVirtualRegister(reg) && + if (//TargetRegisterInfo::isVirtualRegister(reg) && toSpill[vrm_->getPhys(reg)] && cur->overlapsFrom(*i->first, i->second)) { DOUT << "\t\t\tspilling(a): " << *i->first << '\n'; earliestStart = std::min(earliestStart, i->first->beginNumber()); std::vector newIs = - li_->addIntervalsForSpills(*i->first, *vrm_, reg); + li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(reg); } } for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){ unsigned reg = i->first->reg; - if (//MRegisterInfo::isVirtualRegister(reg) && + if (//TargetRegisterInfo::isVirtualRegister(reg) && toSpill[vrm_->getPhys(reg)] && cur->overlapsFrom(*i->first, i->second-1)) { DOUT << "\t\t\tspilling(i): " << *i->first << '\n'; earliestStart = std::min(earliestStart, i->first->beginNumber()); std::vector newIs = - li_->addIntervalsForSpills(*i->first, *vrm_, reg); + li_->addIntervalsForSpills(*i->first, loopInfo, *vrm_); std::copy(newIs.begin(), newIs.end(), std::back_inserter(added)); spilled.insert(reg); } @@ -700,23 +785,28 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) IntervalPtrs::iterator it; if ((it = FindIntervalInVector(active_, i)) != active_.end()) { active_.erase(it); - assert(!MRegisterInfo::isPhysicalRegister(i->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(i->reg)); if (!spilled.count(i->reg)) unhandled_.push(i); prt_->delRegUse(vrm_->getPhys(i->reg)); vrm_->clearVirt(i->reg); } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) { inactive_.erase(it); - assert(!MRegisterInfo::isPhysicalRegister(i->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(i->reg)); if (!spilled.count(i->reg)) unhandled_.push(i); vrm_->clearVirt(i->reg); } else { - assert(MRegisterInfo::isVirtualRegister(i->reg) && + assert(TargetRegisterInfo::isVirtualRegister(i->reg) && "Can only allocate virtual registers!"); vrm_->clearVirt(i->reg); unhandled_.push(i); } + + // It interval has a preference, it must be defined by a copy. Clear the + // preference now since the source interval allocation may have been undone + // as well. + i->preference = 0; } // Rewind the iterators in the active, inactive, and fixed lists back to the @@ -734,7 +824,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) HI->expiredAt(cur->beginNumber())) { DOUT << "\t\t\tundo changes for: " << *HI << '\n'; active_.push_back(std::make_pair(HI, HI->begin())); - assert(!MRegisterInfo::isPhysicalRegister(HI->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg)); prt_->addRegUse(vrm_->getPhys(HI->reg)); } } @@ -747,21 +837,21 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) /// getFreePhysReg - return a free physical register for this virtual register /// interval if we have one, otherwise return 0. unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { - std::vector inactiveCounts(mri_->getNumRegs(), 0); + std::vector inactiveCounts(tri_->getNumRegs(), 0); unsigned MaxInactiveCount = 0; - const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(cur->reg); + const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg); const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC); for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end(); i != e; ++i) { unsigned reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); // If this is not in a related reg class to the register we're allocating, // don't check it. - const TargetRegisterClass *RegRC = mf_->getSSARegMap()->getRegClass(reg); + const TargetRegisterClass *RegRC = reginfo_->getRegClass(reg); if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) { reg = vrm_->getPhys(reg); ++inactiveCounts[reg]; @@ -777,11 +867,11 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { if (cur->preference) if (prt_->isRegAvail(cur->preference)) { DOUT << "\t\tassigned the preferred register: " - << mri_->getName(cur->preference) << "\n"; + << tri_->getName(cur->preference) << "\n"; return cur->preference; } else DOUT << "\t\tunable to assign the preferred register: " - << mri_->getName(cur->preference) << "\n"; + << tri_->getName(cur->preference) << "\n"; // Scan for the first available register. TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_);