X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocLocal.cpp;h=d3c3277cbbf35cbcc1fc0b63b6a4d1ad789dee18;hb=ef9531efedd2233269f670227fb0e6aae7480d53;hp=2cf8e6327e44a44a718baf919890d204a658652a;hpb=551ccae044b0ff658fe629dd67edd5ffe75d10e8;p=oota-llvm.git

diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 2cf8e6327e4..d3c3277cbbf 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -25,6 +25,7 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Statistic.h"
+#include <algorithm>
 using namespace llvm;
 
 namespace {
@@ -37,6 +38,7 @@ namespace {
     MachineFunction *MF;
     const MRegisterInfo *RegInfo;
     LiveVariables *LV;
+    bool *PhysRegsEverUsed;
 
     // StackSlotForVirtReg - Maps virtual regs to the frame index where these
     // values are spilled.
@@ -477,6 +479,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
   RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
   ++NumLoads;    // Update statistics
 
+  PhysRegsEverUsed[PhysReg] = true;
   MI->SetMachineOperandReg(OpNum, PhysReg);  // Assign the input register
   return MI;
 }
@@ -546,6 +549,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
       if (MO.isDef() && MO.isRegister() && MO.getReg() &&
           MRegisterInfo::isPhysicalRegister(MO.getReg())) {
         unsigned Reg = MO.getReg();
+        PhysRegsEverUsed[Reg] = true;
         spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
         PhysRegsUsed[Reg] = 0;            // It is free and reserved now
         PhysRegsUseOrder.push_back(Reg);
@@ -553,6 +557,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
              *AliasSet; ++AliasSet) {
           PhysRegsUseOrder.push_back(*AliasSet);
           PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
+          PhysRegsEverUsed[*AliasSet] = true;
         }
       }
     }
@@ -564,16 +569,19 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
       spillPhysReg(MBB, MI, Reg, true);
       PhysRegsUseOrder.push_back(Reg);
       PhysRegsUsed[Reg] = 0;            // It is free and reserved now
+      PhysRegsEverUsed[Reg] = true;
+
       for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
            *AliasSet; ++AliasSet) {
         PhysRegsUseOrder.push_back(*AliasSet);
         PhysRegsUsed[*AliasSet] = 0;  // It is free and reserved now
+        PhysRegsEverUsed[*AliasSet] = true;
       }
     }
 
     // Okay, we have allocated all of the source operands and spilled any values
     // that would be destroyed by defs of this instruction.  Loop over the
-    // implicit defs and assign them to a register, spilling incoming values if
+    // explicit defs and assign them to a register, spilling incoming values if
     // we need to scavenge a register.
     //
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@@ -586,6 +594,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
         // If DestVirtReg already has a value, use it.
         if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
           DestPhysReg = getReg(MBB, MI, DestVirtReg);
+        PhysRegsEverUsed[DestPhysReg] = true;
         markVirtRegModified(DestVirtReg);
         MI->SetMachineOperandReg(i, DestPhysReg);  // Assign the output register
       }
@@ -651,6 +660,10 @@ bool RA::runOnMachineFunction(MachineFunction &Fn) {
   RegInfo = TM->getRegisterInfo();
   LV = &getAnalysis<LiveVariables>();
 
+  PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
+  std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
+  Fn.setUsedPhysRegs(PhysRegsEverUsed);
+
   PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
 
   // initialize the virtual->physical register map to have a 'null'