X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocSimple.cpp;h=5e5290ce3e30181fffcfc0c64c86a7e8679d9c39;hb=b0000c376cf13ed63306622ab9642cfae49f074a;hp=0daab42c3eb2f46d5e40b1e65b0d4f50f6964f45;hpb=dc2ec004f1f29e0f61c60c71ef8bc94ae96694b8;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 0daab42c3eb..5e5290ce3e3 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -1,260 +1,257 @@ -//===-- RegAllocSimple.cpp - A simple generic register allocator --- ------===// +//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===// // -// This file implements a simple register allocator. *Very* simple. +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements a simple register allocator. *Very* simple: It immediate +// spills every value right after it is computed, and it reloads all used +// operands from the spill area to temporary registers before each instruction. +// It does not keep values in registers across instructions. // //===----------------------------------------------------------------------===// -#include "llvm/Function.h" -#include "llvm/iTerminators.h" -#include "llvm/Type.h" -#include "llvm/Constants.h" -#include "llvm/Pass.h" +#define DEBUG_TYPE "regalloc" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/Target/MRegisterInfo.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegAllocRegistry.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Support/InstVisitor.h" -#include "Support/Statistic.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/Compiler.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include +using namespace llvm; + +STATISTIC(NumStores, "Number of stores added"); +STATISTIC(NumLoads , "Number of loads added"); namespace { - struct RegAllocSimple : public FunctionPass { - TargetMachine &TM; - MachineBasicBlock *CurrMBB; + static RegisterRegAlloc + simpleRegAlloc("simple", "simple register allocator", + createSimpleRegisterAllocator); + + class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass { + public: + static char ID; + RegAllocSimple() : MachineFunctionPass(&ID) {} + private: MachineFunction *MF; - unsigned maxOffset; - const MRegisterInfo *RegInfo; - unsigned NumBytesAllocated, ByteAlignment; - - // Maps SSA Regs => offsets on the stack where these values are stored - std::map RegMap; // FIXME: change name to VirtReg2OffsetMap - - // Maps SSA Regs => physical regs - std::map SSA2PhysRegMap; - - // Maps physical register to their register classes - std::map PhysReg2RegClassMap; - - // Maps RegClass => which index we can take a register from. Since this is a - // simple register allocator, when we need a register of a certain class, we - // just take the next available one. - std::map RegsUsed; - std::map RegClassIdx; + const TargetMachine *TM; + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; + + // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where + // these values are spilled + std::map StackSlotForVirtReg; - RegAllocSimple(TargetMachine &tm) : TM(tm), CurrMBB(0), maxOffset(0), - RegInfo(tm.getRegisterInfo()), - NumBytesAllocated(0), ByteAlignment(4) - { - // build reverse mapping for physReg -> register class - RegInfo->buildReg2RegClassMap(PhysReg2RegClassMap); + // RegsUsed - Keep track of what registers are currently in use. This is a + // bitset. + std::vector RegsUsed; - RegsUsed[RegInfo->getFramePointer()] = 1; - RegsUsed[RegInfo->getStackPointer()] = 1; + // RegClassIdx - Maps RegClass => which index we can take a register + // from. Since this is a simple register allocator, when we need a register + // of a certain class, we just take the next available one. + std::map RegClassIdx; + + public: + virtual const char *getPassName() const { + return "Simple Register Allocator"; } - bool isAvailableReg(unsigned Reg) { - // assert(Reg < MRegisterInfo::FirstVirtualReg && "..."); - return RegsUsed.find(Reg) == RegsUsed.end(); + /// runOnMachineFunction - Register allocate the whole function + bool runOnMachineFunction(MachineFunction &Fn); + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequiredID(PHIEliminationID); // Eliminate PHI nodes + MachineFunctionPass::getAnalysisUsage(AU); } + private: + /// AllocateBasicBlock - Register allocate the specified basic block. + void AllocateBasicBlock(MachineBasicBlock &MBB); - /// - unsigned allocateStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass); + /// getStackSpaceFor - This returns the offset of the specified virtual + /// register on the stack, allocating space if necessary. + int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); - /// Given size (in bytes), returns a register that is currently unused + /// Given a virtual register, return a compatible physical register that is + /// currently unused. + /// /// Side effect: marks that register as being used until manually cleared + /// unsigned getFreeReg(unsigned virtualReg); - /// Returns all `borrowed' registers back to the free pool - void clearAllRegs() { - RegClassIdx.clear(); - } - /// Moves value from memory into that register - MachineBasicBlock::iterator - moveUseToReg (MachineBasicBlock::iterator I, unsigned VirtReg, - unsigned &PhysReg); + unsigned reloadVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, unsigned VirtReg); /// Saves reg value on the stack (maps virtual register to stack value) - MachineBasicBlock::iterator - saveVirtRegToStack (MachineBasicBlock::iterator I, unsigned VirtReg, - unsigned PhysReg); + void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned VirtReg, unsigned PhysReg); + }; + char RegAllocSimple::ID = 0; +} - MachineBasicBlock::iterator - savePhysRegToStack (MachineBasicBlock::iterator I, unsigned PhysReg); +/// getStackSpaceFor - This allocates space for the specified virtual +/// register to be held on the stack. +int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, + const TargetRegisterClass *RC) { + // Find the location VirtReg would belong... + std::map::iterator I = StackSlotForVirtReg.find(VirtReg); - /// runOnFunction - Top level implementation of instruction selection for - /// the entire function. - /// - bool runOnMachineFunction(MachineFunction &Fn); + if (I != StackSlotForVirtReg.end()) + return I->second; // Already has space allocated? - bool runOnFunction(Function &Fn) { - return runOnMachineFunction(MachineFunction::get(&Fn)); - } - }; + // Allocate a new stack object for this spill location... + int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment()); -} + // Assign the slot... + StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); -unsigned RegAllocSimple::allocateStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass) -{ - if (RegMap.find(VirtReg) == RegMap.end()) { - unsigned size = regClass->getDataSize(); - unsigned over = NumBytesAllocated - (NumBytesAllocated % ByteAlignment); - if (size >= ByteAlignment - over) { - // need to pad by (ByteAlignment - over) - NumBytesAllocated += ByteAlignment - over; - } - RegMap[VirtReg] = NumBytesAllocated; - NumBytesAllocated += size; - } - return RegMap[VirtReg]; + return FrameIdx; } unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { - const TargetRegisterClass* regClass = MF->getRegClass(virtualReg); - unsigned physReg; - assert(regClass); - if (RegClassIdx.find(regClass) != RegClassIdx.end()) { - unsigned regIdx = RegClassIdx[regClass]++; - assert(regIdx < regClass->getNumRegs() && "Not enough registers!"); - physReg = regClass->getRegister(regIdx); - } else { - physReg = regClass->getRegister(0); - // assert(physReg < regClass->getNumRegs() && "No registers in class!"); - RegClassIdx[regClass] = 1; - } + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg); + TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); +#ifndef NDEBUG + TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); +#endif + + while (1) { + unsigned regIdx = RegClassIdx[RC]++; + assert(RI+regIdx != RE && "Not enough registers!"); + unsigned PhysReg = *(RI+regIdx); - if (isAvailableReg(physReg)) - return physReg; - else { - return getFreeReg(virtualReg); + if (!RegsUsed[PhysReg]) { + MF->getRegInfo().setPhysRegUsed(PhysReg); + return PhysReg; + } } } -MachineBasicBlock::iterator -RegAllocSimple::moveUseToReg (MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned &PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(VirtReg); - assert(regClass); - - unsigned stackOffset = allocateStackSpaceFor(VirtReg, regClass); - PhysReg = getFreeReg(VirtReg); - - // FIXME: increment the frame pointer +unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned VirtReg) { + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); + int FrameIdx = getStackSpaceFor(VirtReg, RC); + unsigned PhysReg = getFreeReg(VirtReg); // Add move instruction(s) - return RegInfo->loadRegOffset2Reg(CurrMBB, I, PhysReg, - RegInfo->getFramePointer(), - stackOffset, regClass->getDataSize()); + ++NumLoads; + TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); + return PhysReg; } -MachineBasicBlock::iterator -RegAllocSimple::saveVirtRegToStack (MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(VirtReg); - assert(regClass); - - unsigned offset = allocateStackSpaceFor(VirtReg, regClass); +void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned VirtReg, unsigned PhysReg) { + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); + + int FrameIdx = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) - return RegInfo->storeReg2RegOffset(CurrMBB, I, PhysReg, - RegInfo->getFramePointer(), - offset, regClass->getDataSize()); + ++NumStores; + TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC); } -MachineBasicBlock::iterator -RegAllocSimple::savePhysRegToStack (MachineBasicBlock::iterator I, - unsigned PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(PhysReg); - assert(regClass); - unsigned offset = allocateStackSpaceFor(PhysReg, regClass); +void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { + // loop over each instruction + for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) { + // Made to combat the incorrect allocation of r2 = add r1, r1 + std::map Virt2PhysRegMap; - // Add move instruction(s) - return RegInfo->storeReg2RegOffset(CurrMBB, I, PhysReg, - RegInfo->getFramePointer(), - offset, regClass->getDataSize()); -} + RegsUsed.resize(TRI->getNumRegs()); -bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { - RegMap.clear(); - unsigned virtualReg, physReg; - DEBUG(std::cerr << "Machine Function " << "\n"); - MF = &Fn; + // This is a preliminary pass that will invalidate any registers that are + // used by the instruction (including implicit uses). + const TargetInstrDesc &Desc = MI->getDesc(); + const unsigned *Regs; + if (Desc.ImplicitUses) { + for (Regs = Desc.ImplicitUses; *Regs; ++Regs) + RegsUsed[*Regs] = true; + } -#if 0 - // FIXME: add prolog. we should preserve callee-save registers... - MachineFunction::iterator Fi = Fn.begin(); - MachineBasicBlock &MBB = *Fi; - MachineBasicBlock::iterator MBBi = MBB.begin() - const unsigned* calleeSaveRegs = tm.getCalleeSaveRegs(); - while (*calleeSaveRegs) { - //MBBi = saveRegToStack(MBBi, *calleeSaveRegs, - ++calleeSaveRegs; - } -#endif + if (Desc.ImplicitDefs) { + for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) { + RegsUsed[*Regs] = true; + MF->getRegInfo().setPhysRegUsed(*Regs); + } + } - for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); - MBB != MBBe; ++MBB) - { - CurrMBB = &(*MBB); - - //loop over each basic block - for (MachineBasicBlock::iterator I = MBB->begin(); I != MBB->end(); ++I) - { - MachineInstr *MI = *I; - - DEBUG(std::cerr << "instr: "; - MI->print(std::cerr, TM)); - - // FIXME: add a preliminary pass that will invalidate any registers that - // are used by the instruction (including implicit uses) - - - // Loop over each instruction: - // uses, move from memory into registers - for (int i = MI->getNumOperands() - 1; i >= 0; --i) { - MachineOperand &op = MI->getOperand(i); - - if (op.getType() == MachineOperand::MO_SignExtendedImmed || - op.getType() == MachineOperand::MO_UnextendedImmed) - { - DEBUG(std::cerr << "const\n"); - } else if (op.isVirtualRegister()) { - virtualReg = (unsigned) op.getAllocatedRegNum(); - // save register to stack if it's a def - DEBUG(std::cerr << "op: " << op << "\n"); - DEBUG(std::cerr << "\t inst[" << i << "]: "; - MI->print(std::cerr, TM)); - if (op.opIsDef()) { - physReg = getFreeReg(virtualReg); - MachineBasicBlock::iterator J = I; - I = saveVirtRegToStack(J, virtualReg, physReg); + // Loop over uses, move from memory into registers. + for (int i = MI->getNumOperands() - 1; i >= 0; --i) { + MachineOperand &MO = MI->getOperand(i); + + if (MO.isReg() && MO.getReg() && + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { + unsigned virtualReg = (unsigned) MO.getReg(); + DOUT << "op: " << MO << "\n"; + DOUT << "\t inst[" << i << "]: "; + DEBUG(MI->print(*cerr.stream(), TM)); + + // make sure the same virtual register maps to the same physical + // register in any given instruction + unsigned physReg = Virt2PhysRegMap[virtualReg]; + if (physReg == 0) { + if (MO.isDef()) { + int TiedOp = Desc.findTiedToSrcOperand(i); + if (TiedOp == -1) { + physReg = getFreeReg(virtualReg); + } else { + // must be same register number as the source operand that is + // tied to. This maps a = b + c into b = b + c, and saves b into + // a's spot. + assert(MI->getOperand(TiedOp).isReg() && + MI->getOperand(TiedOp).getReg() && + MI->getOperand(TiedOp).isUse() && + "Two address instruction invalid!"); + + physReg = MI->getOperand(TiedOp).getReg(); + } + spillVirtReg(MBB, next(MI), virtualReg, physReg); } else { - I = moveUseToReg(I, virtualReg, physReg); + physReg = reloadVirtReg(MBB, MI, virtualReg); + Virt2PhysRegMap[virtualReg] = physReg; } - MI->SetMachineOperandReg(i, physReg); - DEBUG(std::cerr << "virt: " << virtualReg << - ", phys: " << op.getAllocatedRegNum() << "\n"); } + MO.setReg(physReg); + DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n"; } - - clearAllRegs(); } - + RegClassIdx.clear(); + RegsUsed.clear(); } +} - // FIXME: add epilog. we should preserve callee-save registers... - return false; // We never modify the LLVM itself. +/// runOnMachineFunction - Register allocate the whole function +/// +bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { + DOUT << "Machine Function\n"; + MF = &Fn; + TM = &MF->getTarget(); + TRI = TM->getRegisterInfo(); + TII = TM->getInstrInfo(); + + // Loop over all of the basic blocks, eliminating virtual register references + for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); + MBB != MBBe; ++MBB) + AllocateBasicBlock(*MBB); + + StackSlotForVirtReg.clear(); + return true; } -Pass *createSimpleX86RegisterAllocator(TargetMachine &TM) { - return new RegAllocSimple(TM); +FunctionPass *llvm::createSimpleRegisterAllocator() { + return new RegAllocSimple(); }