X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocSimple.cpp;h=5e5290ce3e30181fffcfc0c64c86a7e8679d9c39;hb=b0000c376cf13ed63306622ab9642cfae49f074a;hp=3437b00047375c25b166b25043ac1a675b3d22c0;hpb=7814ad0bf38047628eb3165e1b73e44da7e8b825;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 3437b000473..5e5290ce3e3 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -18,8 +18,8 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -27,21 +27,26 @@ #include "llvm/Support/Compiler.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" +#include using namespace llvm; -namespace { - static Statistic NumStores("ra-simple", "Number of stores added"); - static Statistic NumLoads ("ra-simple", "Number of loads added"); +STATISTIC(NumStores, "Number of stores added"); +STATISTIC(NumLoads , "Number of loads added"); +namespace { static RegisterRegAlloc - simpleRegAlloc("simple", " simple register allocator", + simpleRegAlloc("simple", "simple register allocator", createSimpleRegisterAllocator); class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass { + public: + static char ID; + RegAllocSimple() : MachineFunctionPass(&ID) {} + private: MachineFunction *MF; const TargetMachine *TM; - const MRegisterInfo *RegInfo; - bool *PhysRegsEverUsed; + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where // these values are spilled @@ -91,7 +96,7 @@ namespace { void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned VirtReg, unsigned PhysReg); }; - + char RegAllocSimple::ID = 0; } /// getStackSpaceFor - This allocates space for the specified virtual @@ -99,10 +104,9 @@ namespace { int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { // Find the location VirtReg would belong... - std::map::iterator I = - StackSlotForVirtReg.lower_bound(VirtReg); + std::map::iterator I = StackSlotForVirtReg.find(VirtReg); - if (I != StackSlotForVirtReg.end() && I->first == VirtReg) + if (I != StackSlotForVirtReg.end()) return I->second; // Already has space allocated? // Allocate a new stack object for this spill location... @@ -116,9 +120,11 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, } unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg); TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); +#ifndef NDEBUG TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); +#endif while (1) { unsigned regIdx = RegClassIdx[RC]++; @@ -126,7 +132,7 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { unsigned PhysReg = *(RI+regIdx); if (!RegsUsed[PhysReg]) { - PhysRegsEverUsed[PhysReg] = true; + MF->getRegInfo().setPhysRegUsed(PhysReg); return PhysReg; } } @@ -135,25 +141,26 @@ unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned VirtReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIdx = getStackSpaceFor(VirtReg, RC); unsigned PhysReg = getFreeReg(VirtReg); // Add move instruction(s) ++NumLoads; - RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); + TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); return PhysReg; } void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned VirtReg, unsigned PhysReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); + int FrameIdx = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) ++NumStores; - RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC); + TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC); } @@ -163,12 +170,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // Made to combat the incorrect allocation of r2 = add r1, r1 std::map Virt2PhysRegMap; - RegsUsed.resize(RegInfo->getNumRegs()); + RegsUsed.resize(TRI->getNumRegs()); // This is a preliminary pass that will invalidate any registers that are // used by the instruction (including implicit uses). - unsigned Opcode = MI->getOpcode(); - const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode); + const TargetInstrDesc &Desc = MI->getDesc(); const unsigned *Regs; if (Desc.ImplicitUses) { for (Regs = Desc.ImplicitUses; *Regs; ++Regs) @@ -178,18 +184,18 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { if (Desc.ImplicitDefs) { for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) { RegsUsed[*Regs] = true; - PhysRegsEverUsed[*Regs] = true; + MF->getRegInfo().setPhysRegUsed(*Regs); } } // Loop over uses, move from memory into registers. for (int i = MI->getNumOperands() - 1; i >= 0; --i) { - MachineOperand &op = MI->getOperand(i); + MachineOperand &MO = MI->getOperand(i); - if (op.isRegister() && op.getReg() && - MRegisterInfo::isVirtualRegister(op.getReg())) { - unsigned virtualReg = (unsigned) op.getReg(); - DOUT << "op: " << op << "\n"; + if (MO.isReg() && MO.getReg() && + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { + unsigned virtualReg = (unsigned) MO.getReg(); + DOUT << "op: " << MO << "\n"; DOUT << "\t inst[" << i << "]: "; DEBUG(MI->print(*cerr.stream(), TM)); @@ -197,16 +203,15 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // register in any given instruction unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { - if (op.isDef()) { - int TiedOp = TM->getInstrInfo()-> - findTiedToSrcOperand(MI->getInstrDescriptor(), i); + if (MO.isDef()) { + int TiedOp = Desc.findTiedToSrcOperand(i); if (TiedOp == -1) { physReg = getFreeReg(virtualReg); } else { // must be same register number as the source operand that is // tied to. This maps a = b + c into b = b + c, and saves b into // a's spot. - assert(MI->getOperand(TiedOp).isRegister() && + assert(MI->getOperand(TiedOp).isReg() && MI->getOperand(TiedOp).getReg() && MI->getOperand(TiedOp).isUse() && "Two address instruction invalid!"); @@ -219,8 +224,8 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { Virt2PhysRegMap[virtualReg] = physReg; } } - MI->getOperand(i).setReg(physReg); - DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n"; + MO.setReg(physReg); + DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n"; } } RegClassIdx.clear(); @@ -235,11 +240,8 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { DOUT << "Machine Function\n"; MF = &Fn; TM = &MF->getTarget(); - RegInfo = TM->getRegisterInfo(); - - PhysRegsEverUsed = new bool[RegInfo->getNumRegs()]; - std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false); - Fn.setUsedPhysRegs(PhysRegsEverUsed); + TRI = TM->getRegisterInfo(); + TII = TM->getInstrInfo(); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();