X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocSimple.cpp;h=5e5290ce3e30181fffcfc0c64c86a7e8679d9c39;hb=b0000c376cf13ed63306622ab9642cfae49f074a;hp=49a205aec5d036a7a1f223dd91fffaa07ca37cc4;hpb=198ab640bbb0b8e1cdda518b7f8b348764e4402c;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 49a205aec5d..5e5290ce3e3 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -1,410 +1,257 @@ -//===-- RegAllocSimple.cpp - A simple generic register allocator --- ------===// +//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===// // -// This file implements a simple register allocator. *Very* simple. +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements a simple register allocator. *Very* simple: It immediate +// spills every value right after it is computed, and it reloads all used +// operands from the spill area to temporary registers before each instruction. +// It does not keep values in registers across instructions. // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/MachineFunction.h" +#define DEBUG_TYPE "regalloc" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Target/MachineInstrInfo.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegAllocRegistry.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "Support/Statistic.h" -#include - -/// PhysRegClassMap - Construct a mapping of physical register numbers to their -/// register classes. -/// -/// NOTE: This class will eventually be pulled out to somewhere shared. -/// -class PhysRegClassMap { - std::map PhysReg2RegClassMap; -public: - PhysRegClassMap(const MRegisterInfo *RI) { - for (MRegisterInfo::const_iterator I = RI->regclass_begin(), - E = RI->regclass_end(); I != E; ++I) - for (unsigned i=0; i < (*I)->getNumRegs(); ++i) - PhysReg2RegClassMap[(*I)->getRegister(i)] = *I; - } - - const TargetRegisterClass *operator[](unsigned Reg) { - assert(PhysReg2RegClassMap[Reg] && "Register is not a known physreg!"); - return PhysReg2RegClassMap[Reg]; - } - - const TargetRegisterClass *get(unsigned Reg) { return operator[](Reg); } -}; +#include "llvm/Support/Debug.h" +#include "llvm/Support/Compiler.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" +#include +using namespace llvm; +STATISTIC(NumStores, "Number of stores added"); +STATISTIC(NumLoads , "Number of loads added"); namespace { - struct RegAllocSimple : public FunctionPass { - TargetMachine &TM; + static RegisterRegAlloc + simpleRegAlloc("simple", "simple register allocator", + createSimpleRegisterAllocator); + + class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass { + public: + static char ID; + RegAllocSimple() : MachineFunctionPass(&ID) {} + private: MachineFunction *MF; - const MRegisterInfo *RegInfo; - unsigned NumBytesAllocated; - - // Maps SSA Regs => offsets on the stack where these values are stored - std::map VirtReg2OffsetMap; + const TargetMachine *TM; + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; - // Maps SSA Regs => physical regs - std::map SSA2PhysRegMap; + // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where + // these values are spilled + std::map StackSlotForVirtReg; - // Maps physical register to their register classes - PhysRegClassMap PhysRegClasses; + // RegsUsed - Keep track of what registers are currently in use. This is a + // bitset. + std::vector RegsUsed; - // Made to combat the incorrect allocation of r2 = add r1, r1 - std::map VirtReg2PhysRegMap; - - // Maps RegClass => which index we can take a register from. Since this is a - // simple register allocator, when we need a register of a certain class, we - // just take the next available one. - std::map RegsUsed; + // RegClassIdx - Maps RegClass => which index we can take a register + // from. Since this is a simple register allocator, when we need a register + // of a certain class, we just take the next available one. std::map RegClassIdx; - RegAllocSimple(TargetMachine &tm) - : TM(tm), RegInfo(tm.getRegisterInfo()), PhysRegClasses(RegInfo) { - RegsUsed[RegInfo->getFramePointer()] = 1; - RegsUsed[RegInfo->getStackPointer()] = 1; - - cleanupAfterFunction(); + public: + virtual const char *getPassName() const { + return "Simple Register Allocator"; } - bool isAvailableReg(unsigned Reg) { - // assert(Reg < MRegisterInfo::FirstVirtualReg && "..."); - return RegsUsed.find(Reg) == RegsUsed.end(); + /// runOnMachineFunction - Register allocate the whole function + bool runOnMachineFunction(MachineFunction &Fn); + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequiredID(PHIEliminationID); // Eliminate PHI nodes + MachineFunctionPass::getAnalysisUsage(AU); } + private: + /// AllocateBasicBlock - Register allocate the specified basic block. + void AllocateBasicBlock(MachineBasicBlock &MBB); - /// allocateStackSpaceFor - This allocates space for the specified virtual - /// register to be held on the stack. - unsigned allocateStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass); + /// getStackSpaceFor - This returns the offset of the specified virtual + /// register on the stack, allocating space if necessary. + int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); - /// Given size (in bytes), returns a register that is currently unused + /// Given a virtual register, return a compatible physical register that is + /// currently unused. + /// /// Side effect: marks that register as being used until manually cleared - unsigned getFreeReg(unsigned virtualReg); - - /// Returns all `borrowed' registers back to the free pool - void clearAllRegs() { - RegClassIdx.clear(); - } - - /// Invalidates any references, real or implicit, to physical registers /// - void invalidatePhysRegs(const MachineInstr *MI) { - unsigned Opcode = MI->getOpcode(); - const MachineInstrInfo &MII = TM.getInstrInfo(); - const MachineInstrDescriptor &Desc = MII.get(Opcode); - const unsigned *regs = Desc.ImplicitUses; - while (*regs) - RegsUsed[*regs++] = 1; - - regs = Desc.ImplicitDefs; - while (*regs) - RegsUsed[*regs++] = 1; - } - - void cleanupAfterFunction() { - VirtReg2OffsetMap.clear(); - SSA2PhysRegMap.clear(); - NumBytesAllocated = 4; // FIXME: This is X86 specific - } + unsigned getFreeReg(unsigned virtualReg); /// Moves value from memory into that register - MachineBasicBlock::iterator - moveUseToReg (MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, unsigned VirtReg, - unsigned &PhysReg); + unsigned reloadVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, unsigned VirtReg); /// Saves reg value on the stack (maps virtual register to stack value) - MachineBasicBlock::iterator - saveVirtRegToStack (MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, unsigned VirtReg, - unsigned PhysReg); - - MachineBasicBlock::iterator - savePhysRegToStack (MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, unsigned PhysReg); - - /// runOnFunction - Top level implementation of instruction selection for - /// the entire function. - /// - bool runOnMachineFunction(MachineFunction &Fn); + void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + unsigned VirtReg, unsigned PhysReg); + }; + char RegAllocSimple::ID = 0; +} - /// AllocateBasicBlock - Register allocate the specified basic block. - void AllocateBasicBlock(MachineBasicBlock &MBB); +/// getStackSpaceFor - This allocates space for the specified virtual +/// register to be held on the stack. +int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, + const TargetRegisterClass *RC) { + // Find the location VirtReg would belong... + std::map::iterator I = StackSlotForVirtReg.find(VirtReg); - /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions - /// in predecessor basic blocks. - void EliminatePHINodes(MachineBasicBlock &MBB); + if (I != StackSlotForVirtReg.end()) + return I->second; // Already has space allocated? - bool runOnFunction(Function &Fn) { - return runOnMachineFunction(MachineFunction::get(&Fn)); - } - }; + // Allocate a new stack object for this spill location... + int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment()); -} + // Assign the slot... + StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); -/// allocateStackSpaceFor - This allocates space for the specified virtual -/// register to be held on the stack. -unsigned RegAllocSimple::allocateStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass) -{ - if (VirtReg2OffsetMap.find(VirtReg) == VirtReg2OffsetMap.end()) { - unsigned RegSize = regClass->getDataSize(); - - // Align NumBytesAllocated. We should be using TargetData alignment stuff - // to determine this, but we don't know the LLVM type associated with the - // virtual register. Instead, just align to a multiple of the size for now. - NumBytesAllocated += RegSize-1; - NumBytesAllocated = NumBytesAllocated/RegSize*RegSize; - - // Assign the slot... - VirtReg2OffsetMap[VirtReg] = NumBytesAllocated; - - // Reserve the space! - NumBytesAllocated += RegSize; - } - return VirtReg2OffsetMap[VirtReg]; + return FrameIdx; } unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { - const TargetRegisterClass* regClass = MF->getRegClass(virtualReg); - unsigned physReg; - assert(regClass); - if (RegClassIdx.find(regClass) != RegClassIdx.end()) { - unsigned regIdx = RegClassIdx[regClass]++; - assert(regIdx < regClass->getNumRegs() && "Not enough registers!"); - physReg = regClass->getRegister(regIdx); - } else { - physReg = regClass->getRegister(0); - // assert(physReg < regClass->getNumRegs() && "No registers in class!"); - RegClassIdx[regClass] = 1; - } - - if (isAvailableReg(physReg)) - return physReg; - else { - return getFreeReg(virtualReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg); + TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); +#ifndef NDEBUG + TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); +#endif + + while (1) { + unsigned regIdx = RegClassIdx[RC]++; + assert(RI+regIdx != RE && "Not enough registers!"); + unsigned PhysReg = *(RI+regIdx); + + if (!RegsUsed[PhysReg]) { + MF->getRegInfo().setPhysRegUsed(PhysReg); + return PhysReg; + } } } -MachineBasicBlock::iterator -RegAllocSimple::moveUseToReg (MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned &PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(VirtReg); - assert(regClass); - - unsigned stackOffset = allocateStackSpaceFor(VirtReg, regClass); - PhysReg = getFreeReg(VirtReg); +unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned VirtReg) { + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); + int FrameIdx = getStackSpaceFor(VirtReg, RC); + unsigned PhysReg = getFreeReg(VirtReg); // Add move instruction(s) - return RegInfo->loadRegOffset2Reg(MBB, I, PhysReg, - RegInfo->getFramePointer(), - -stackOffset, regClass->getDataSize()); + ++NumLoads; + TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); + return PhysReg; } -MachineBasicBlock::iterator -RegAllocSimple::saveVirtRegToStack (MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(VirtReg); - assert(regClass); - - unsigned stackOffset = allocateStackSpaceFor(VirtReg, regClass); +void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned VirtReg, unsigned PhysReg) { + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); + + int FrameIdx = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) - return RegInfo->storeReg2RegOffset(MBB, I, PhysReg, - RegInfo->getFramePointer(), - -stackOffset, regClass->getDataSize()); + ++NumStores; + TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC); } -MachineBasicBlock::iterator -RegAllocSimple::savePhysRegToStack (MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(PhysReg); - assert(regClass); - unsigned offset = allocateStackSpaceFor(PhysReg, regClass); +void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { + // loop over each instruction + for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) { + // Made to combat the incorrect allocation of r2 = add r1, r1 + std::map Virt2PhysRegMap; - // Add move instruction(s) - return RegInfo->storeReg2RegOffset(MBB, I, PhysReg, - RegInfo->getFramePointer(), - offset, regClass->getDataSize()); -} + RegsUsed.resize(TRI->getNumRegs()); -/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in -/// predecessor basic blocks. -void RegAllocSimple::EliminatePHINodes(MachineBasicBlock &MBB) { - while (MBB.front()->getOpcode() == 0) { - MachineInstr *MI = MBB.front(); - // get rid of the phi - MBB.erase(MBB.begin()); - - // a preliminary pass that will invalidate any registers that - // are used by the instruction (including implicit uses) - invalidatePhysRegs(MI); - - DEBUG(std::cerr << "num invalid regs: " << RegsUsed.size() << "\n"); - - DEBUG(std::cerr << "num ops: " << MI->getNumOperands() << "\n"); - MachineOperand &targetReg = MI->getOperand(0); - - // If it's a virtual register, allocate a physical one - // otherwise, just use whatever register is there now - // note: it MUST be a register -- we're assigning to it - unsigned virtualReg = (unsigned) targetReg.getAllocatedRegNum(); - unsigned physReg; - if (targetReg.isVirtualRegister()) { - physReg = getFreeReg(virtualReg); - } else { - physReg = virtualReg; + // This is a preliminary pass that will invalidate any registers that are + // used by the instruction (including implicit uses). + const TargetInstrDesc &Desc = MI->getDesc(); + const unsigned *Regs; + if (Desc.ImplicitUses) { + for (Regs = Desc.ImplicitUses; *Regs; ++Regs) + RegsUsed[*Regs] = true; } - - // Find the register class of the target register: should be the - // same as the values we're trying to store there - const TargetRegisterClass* regClass = PhysRegClasses[physReg]; - assert(regClass && "Target register class not found!"); - unsigned dataSize = regClass->getDataSize(); - - for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) { - MachineOperand &opVal = MI->getOperand(i-1); - - // Get the MachineBasicBlock equivalent of the BasicBlock that is the - // source path the phi - MachineBasicBlock &opBlock = *MI->getOperand(i).getMachineBasicBlock(); - MachineBasicBlock::iterator opI = opBlock.end(); - MachineInstr *opMI = *--opI; - const MachineInstrInfo &MII = TM.getInstrInfo(); - - // must backtrack over ALL the branches in the previous block, until no - // more - while (MII.isBranch(opMI->getOpcode()) && opI != opBlock.begin()) - opMI = *--opI; - - // move back to the first branch instruction so new instructions - // are inserted right in front of it and not in front of a non-branch - if (!MII.isBranch(opMI->getOpcode())) - ++opI; - - // Retrieve the constant value from this op, move it to target - // register of the phi - if (opVal.isImmediate()) { - opI = RegInfo->moveImm2Reg(opBlock, opI, physReg, - (unsigned) opVal.getImmedValue(), - dataSize); - saveVirtRegToStack(opBlock, opI, virtualReg, physReg); - } else { - // Allocate a physical register and add a move in the BB - unsigned opVirtualReg = (unsigned) opVal.getAllocatedRegNum(); - unsigned opPhysReg; // = getFreeReg(opVirtualReg); - opI = moveUseToReg(opBlock, opI, opVirtualReg, physReg); - //opI = RegInfo->moveReg2Reg(opBlock, opI, physReg, opPhysReg, - // dataSize); - // Save that register value to the stack of the TARGET REG - saveVirtRegToStack(opBlock, opI, virtualReg, physReg); + + if (Desc.ImplicitDefs) { + for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) { + RegsUsed[*Regs] = true; + MF->getRegInfo().setPhysRegUsed(*Regs); } - - // make regs available to other instructions - clearAllRegs(); } - - // really delete the instruction - delete MI; - } -} - -void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { - // Handle PHI instructions specially: add moves to each pred block - EliminatePHINodes(MBB); - - //loop over each basic block - for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) { - MachineInstr *MI = *I; - - // a preliminary pass that will invalidate any registers that - // are used by the instruction (including implicit uses) - invalidatePhysRegs(MI); - - // Loop over uses, move from memory into registers + // Loop over uses, move from memory into registers. for (int i = MI->getNumOperands() - 1; i >= 0; --i) { - MachineOperand &op = MI->getOperand(i); - - if (op.isImmediate()) { - DEBUG(std::cerr << "const\n"); - } else if (op.isVirtualRegister()) { - unsigned virtualReg = (unsigned) op.getAllocatedRegNum(); - DEBUG(std::cerr << "op: " << op << "\n"); - DEBUG(std::cerr << "\t inst[" << i << "]: "; - MI->print(std::cerr, TM)); - + MachineOperand &MO = MI->getOperand(i); + + if (MO.isReg() && MO.getReg() && + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { + unsigned virtualReg = (unsigned) MO.getReg(); + DOUT << "op: " << MO << "\n"; + DOUT << "\t inst[" << i << "]: "; + DEBUG(MI->print(*cerr.stream(), TM)); + // make sure the same virtual register maps to the same physical // register in any given instruction - unsigned physReg; - if (VirtReg2PhysRegMap.find(virtualReg) != VirtReg2PhysRegMap.end()) { - physReg = VirtReg2PhysRegMap[virtualReg]; - } else { - if (op.opIsDef()) { - if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { - // must be same register number as the first operand - // This maps a = b + c into b += c, and saves b into a's spot - physReg = (unsigned) MI->getOperand(1).getAllocatedRegNum(); - } else { + unsigned physReg = Virt2PhysRegMap[virtualReg]; + if (physReg == 0) { + if (MO.isDef()) { + int TiedOp = Desc.findTiedToSrcOperand(i); + if (TiedOp == -1) { physReg = getFreeReg(virtualReg); + } else { + // must be same register number as the source operand that is + // tied to. This maps a = b + c into b = b + c, and saves b into + // a's spot. + assert(MI->getOperand(TiedOp).isReg() && + MI->getOperand(TiedOp).getReg() && + MI->getOperand(TiedOp).isUse() && + "Two address instruction invalid!"); + + physReg = MI->getOperand(TiedOp).getReg(); } - MachineBasicBlock::iterator J = I; - J = saveVirtRegToStack(MBB, ++J, virtualReg, physReg); - I = --J; + spillVirtReg(MBB, next(MI), virtualReg, physReg); } else { - I = moveUseToReg(MBB, I, virtualReg, physReg); + physReg = reloadVirtReg(MBB, MI, virtualReg); + Virt2PhysRegMap[virtualReg] = physReg; } - VirtReg2PhysRegMap[virtualReg] = physReg; } - MI->SetMachineOperandReg(i, physReg); - DEBUG(std::cerr << "virt: " << virtualReg << - ", phys: " << op.getAllocatedRegNum() << "\n"); + MO.setReg(physReg); + DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n"; } } - - clearAllRegs(); - VirtReg2PhysRegMap.clear(); + RegClassIdx.clear(); + RegsUsed.clear(); } } + +/// runOnMachineFunction - Register allocate the whole function +/// bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { - DEBUG(std::cerr << "Machine Function " << "\n"); + DOUT << "Machine Function\n"; MF = &Fn; + TM = &MF->getTarget(); + TRI = TM->getRegisterInfo(); + TII = TM->getInstrInfo(); + // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); MBB != MBBe; ++MBB) AllocateBasicBlock(*MBB); - // add prologue we should preserve callee-save registers... - RegInfo->emitPrologue(Fn, NumBytesAllocated); - - const MachineInstrInfo &MII = TM.getInstrInfo(); - - // add epilogue to restore the callee-save registers - // loop over the basic block - for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); - MBB != MBBe; ++MBB) { - // check if last instruction is a RET - MachineBasicBlock::iterator I = MBB->end(); - MachineInstr *MI = *--I; - if (MII.isReturn(MI->getOpcode())) { - // this block has a return instruction, add epilogue - RegInfo->emitEpilogue(*MBB, NumBytesAllocated); - } - } - - cleanupAfterFunction(); - return false; // We never modify the LLVM itself. + StackSlotForVirtReg.clear(); + return true; } -Pass *createSimpleX86RegisterAllocator(TargetMachine &TM) { - return new RegAllocSimple(TM); +FunctionPass *llvm::createSimpleRegisterAllocator() { + return new RegAllocSimple(); }