X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocSimple.cpp;h=5e5290ce3e30181fffcfc0c64c86a7e8679d9c39;hb=b0000c376cf13ed63306622ab9642cfae49f074a;hp=a81edda858cf1aa3bc91d121b9adac93f124fe04;hpb=859a18b5833f3566799313ecba8db4916500485b;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index a81edda858c..5e5290ce3e3 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -1,10 +1,10 @@ //===-- RegAllocSimple.cpp - A simple generic register allocator ----------===// -// +// // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. -// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// //===----------------------------------------------------------------------===// // // This file implements a simple register allocator. *Very* simple: It immediate @@ -18,25 +18,36 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "Support/Debug.h" -#include "Support/Statistic.h" -#include +#include "llvm/Support/Debug.h" +#include "llvm/Support/Compiler.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" +#include +using namespace llvm; -namespace llvm { +STATISTIC(NumStores, "Number of stores added"); +STATISTIC(NumLoads , "Number of loads added"); namespace { - Statistic<> NumSpilled ("ra-simple", "Number of registers spilled"); - Statistic<> NumReloaded("ra-simple", "Number of registers reloaded"); + static RegisterRegAlloc + simpleRegAlloc("simple", "simple register allocator", + createSimpleRegisterAllocator); - class RegAllocSimple : public MachineFunctionPass { + class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass { + public: + static char ID; + RegAllocSimple() : MachineFunctionPass(&ID) {} + private: MachineFunction *MF; const TargetMachine *TM; - const MRegisterInfo *RegInfo; - + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; + // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where // these values are spilled std::map StackSlotForVirtReg; @@ -79,29 +90,29 @@ namespace { /// Moves value from memory into that register unsigned reloadVirtReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &I, unsigned VirtReg); + MachineBasicBlock::iterator I, unsigned VirtReg); /// Saves reg value on the stack (maps virtual register to stack value) - void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, + void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned VirtReg, unsigned PhysReg); }; - + char RegAllocSimple::ID = 0; } /// getStackSpaceFor - This allocates space for the specified virtual /// register to be held on the stack. int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *RC) { + const TargetRegisterClass *RC) { // Find the location VirtReg would belong... - std::map::iterator I = - StackSlotForVirtReg.lower_bound(VirtReg); + std::map::iterator I = StackSlotForVirtReg.find(VirtReg); - if (I != StackSlotForVirtReg.end() && I->first == VirtReg) + if (I != StackSlotForVirtReg.end()) return I->second; // Already has space allocated? // Allocate a new stack object for this spill location... - int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC); - + int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment()); + // Assign the slot... StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); @@ -109,42 +120,47 @@ int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, } unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg); TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); +#ifndef NDEBUG TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); +#endif while (1) { - unsigned regIdx = RegClassIdx[RC]++; + unsigned regIdx = RegClassIdx[RC]++; assert(RI+regIdx != RE && "Not enough registers!"); unsigned PhysReg = *(RI+regIdx); - - if (!RegsUsed[PhysReg]) + + if (!RegsUsed[PhysReg]) { + MF->getRegInfo().setPhysRegUsed(PhysReg); return PhysReg; + } } } unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &I, + MachineBasicBlock::iterator I, unsigned VirtReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); int FrameIdx = getStackSpaceFor(VirtReg, RC); unsigned PhysReg = getFreeReg(VirtReg); // Add move instruction(s) - ++NumReloaded; - RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); + ++NumLoads; + TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); return PhysReg; } void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &I, + MachineBasicBlock::iterator I, unsigned VirtReg, unsigned PhysReg) { - const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg); + int FrameIdx = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) - ++NumSpilled; - RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC); + ++NumStores; + TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC); } @@ -154,58 +170,62 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // Made to combat the incorrect allocation of r2 = add r1, r1 std::map Virt2PhysRegMap; - RegsUsed.resize(RegInfo->getNumRegs()); - - // a preliminary pass that will invalidate any registers that - // are used by the instruction (including implicit uses) - unsigned Opcode = MI->getOpcode(); - const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode); - const unsigned *Regs = Desc.ImplicitUses; - while (*Regs) - RegsUsed[*Regs++] = true; - - Regs = Desc.ImplicitDefs; - while (*Regs) - RegsUsed[*Regs++] = true; - - // Loop over uses, move from memory into registers + RegsUsed.resize(TRI->getNumRegs()); + + // This is a preliminary pass that will invalidate any registers that are + // used by the instruction (including implicit uses). + const TargetInstrDesc &Desc = MI->getDesc(); + const unsigned *Regs; + if (Desc.ImplicitUses) { + for (Regs = Desc.ImplicitUses; *Regs; ++Regs) + RegsUsed[*Regs] = true; + } + + if (Desc.ImplicitDefs) { + for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) { + RegsUsed[*Regs] = true; + MF->getRegInfo().setPhysRegUsed(*Regs); + } + } + + // Loop over uses, move from memory into registers. for (int i = MI->getNumOperands() - 1; i >= 0; --i) { - MachineOperand &op = MI->getOperand(i); - - if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) { - unsigned virtualReg = (unsigned) op.getReg(); - DEBUG(std::cerr << "op: " << op << "\n"); - DEBUG(std::cerr << "\t inst[" << i << "]: "; - MI->print(std::cerr, *TM)); - + MachineOperand &MO = MI->getOperand(i); + + if (MO.isReg() && MO.getReg() && + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { + unsigned virtualReg = (unsigned) MO.getReg(); + DOUT << "op: " << MO << "\n"; + DOUT << "\t inst[" << i << "]: "; + DEBUG(MI->print(*cerr.stream(), TM)); + // make sure the same virtual register maps to the same physical // register in any given instruction unsigned physReg = Virt2PhysRegMap[virtualReg]; if (physReg == 0) { - if (op.isDef()) { - if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { - // must be same register number as the first operand - // This maps a = b + c into b += c, and saves b into a's spot - assert(MI->getOperand(1).isRegister() && - MI->getOperand(1).getReg() && - MI->getOperand(1).isUse() && + if (MO.isDef()) { + int TiedOp = Desc.findTiedToSrcOperand(i); + if (TiedOp == -1) { + physReg = getFreeReg(virtualReg); + } else { + // must be same register number as the source operand that is + // tied to. This maps a = b + c into b = b + c, and saves b into + // a's spot. + assert(MI->getOperand(TiedOp).isReg() && + MI->getOperand(TiedOp).getReg() && + MI->getOperand(TiedOp).isUse() && "Two address instruction invalid!"); - physReg = MI->getOperand(1).getReg(); - } else { - physReg = getFreeReg(virtualReg); + physReg = MI->getOperand(TiedOp).getReg(); } - ++MI; - spillVirtReg(MBB, MI, virtualReg, physReg); - --MI; + spillVirtReg(MBB, next(MI), virtualReg, physReg); } else { physReg = reloadVirtReg(MBB, MI, virtualReg); Virt2PhysRegMap[virtualReg] = physReg; } } - MI->SetMachineOperandReg(i, physReg); - DEBUG(std::cerr << "virt: " << virtualReg << - ", phys: " << op.getReg() << "\n"); + MO.setReg(physReg); + DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n"; } } RegClassIdx.clear(); @@ -217,10 +237,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { /// runOnMachineFunction - Register allocate the whole function /// bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { - DEBUG(std::cerr << "Machine Function " << "\n"); + DOUT << "Machine Function\n"; MF = &Fn; TM = &MF->getTarget(); - RegInfo = TM->getRegisterInfo(); + TRI = TM->getRegisterInfo(); + TII = TM->getInstrInfo(); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); @@ -231,8 +252,6 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { return true; } -FunctionPass *createSimpleRegisterAllocator() { +FunctionPass *llvm::createSimpleRegisterAllocator() { return new RegAllocSimple(); } - -} // End llvm namespace