X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocSimple.cpp;h=6b95af82fda415860e83810b0539fa9c76f43e6d;hb=a3c58f1c060bb97371ad06bf10c4836845e0f5a3;hp=8dc4cf83803eefebcc9323e4b17509c8ca4f5063;hpb=abe8dd592d1c2e4e604e39fcf4598642fd6ea197;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index 8dc4cf83803..6b95af82fda 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -1,385 +1,227 @@ -//===-- RegAllocSimple.cpp - A simple generic register allocator --- ------===// +//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===// // -// This file implements a simple register allocator. *Very* simple. +// This file implements a simple register allocator. *Very* simple: It immediate +// spills every value right after it is computed, and it reloads all used +// operands from the spill area to temporary registers before each instruction. +// It does not keep values in registers across instructions. // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Target/MachineInstrInfo.h" +#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "Support/Statistic.h" #include namespace { - struct RegAllocSimple : public FunctionPass { - TargetMachine &TM; - MachineBasicBlock *CurrMBB; + Statistic<> NumSpilled ("ra-simple", "Number of registers spilled"); + Statistic<> NumReloaded("ra-simple", "Number of registers reloaded"); + + class RegAllocSimple : public MachineFunctionPass { MachineFunction *MF; - unsigned maxOffset; + const TargetMachine *TM; const MRegisterInfo *RegInfo; - unsigned NumBytesAllocated, ByteAlignment; - // Maps SSA Regs => offsets on the stack where these values are stored - std::map VirtReg2OffsetMap; - - // Maps SSA Regs => physical regs - std::map SSA2PhysRegMap; + // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where + // these values are spilled + std::map StackSlotForVirtReg; - // Maps physical register to their register classes - std::map PhysReg2RegClassMap; + // RegsUsed - Keep track of what registers are currently in use. This is a + // bitset. + std::vector RegsUsed; - // Made to combat the incorrect allocation of r2 = add r1, r1 - std::map VirtReg2PhysRegMap; - - // Maps RegClass => which index we can take a register from. Since this is a - // simple register allocator, when we need a register of a certain class, we - // just take the next available one. - std::map RegsUsed; + // RegClassIdx - Maps RegClass => which index we can take a register + // from. Since this is a simple register allocator, when we need a register + // of a certain class, we just take the next available one. std::map RegClassIdx; - RegAllocSimple(TargetMachine &tm) : TM(tm), CurrMBB(0), maxOffset(0), - RegInfo(tm.getRegisterInfo()), - ByteAlignment(4) - { - // build reverse mapping for physReg -> register class - RegInfo->buildReg2RegClassMap(PhysReg2RegClassMap); + public: + virtual const char *getPassName() const { + return "Simple Register Allocator"; + } - RegsUsed[RegInfo->getFramePointer()] = 1; - RegsUsed[RegInfo->getStackPointer()] = 1; + /// runOnMachineFunction - Register allocate the whole function + bool runOnMachineFunction(MachineFunction &Fn); - cleanupAfterFunction(); + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequiredID(PHIEliminationID); // Eliminate PHI nodes + MachineFunctionPass::getAnalysisUsage(AU); } + private: + /// AllocateBasicBlock - Register allocate the specified basic block. + void AllocateBasicBlock(MachineBasicBlock &MBB); - bool isAvailableReg(unsigned Reg) { - // assert(Reg < MRegisterInfo::FirstVirtualReg && "..."); - return RegsUsed.find(Reg) == RegsUsed.end(); - } + /// getStackSpaceFor - This returns the offset of the specified virtual + /// register on the stack, allocating space if neccesary. + int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); + /// Given a virtual register, return a compatible physical register that is + /// currently unused. /// - unsigned allocateStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass); - - /// Given size (in bytes), returns a register that is currently unused /// Side effect: marks that register as being used until manually cleared - unsigned getFreeReg(unsigned virtualReg); - - /// Returns all `borrowed' registers back to the free pool - void clearAllRegs() { - RegClassIdx.clear(); - } - - /// Invalidates any references, real or implicit, to physical registers /// - void invalidatePhysRegs(const MachineInstr *MI) { - unsigned Opcode = MI->getOpcode(); - const MachineInstrInfo &MII = TM.getInstrInfo(); - const MachineInstrDescriptor &Desc = MII.get(Opcode); - const unsigned *regs = Desc.ImplicitUses; - while (*regs) - RegsUsed[*regs++] = 1; - - regs = Desc.ImplicitDefs; - while (*regs) - RegsUsed[*regs++] = 1; - } - - void cleanupAfterFunction() { - VirtReg2OffsetMap.clear(); - SSA2PhysRegMap.clear(); - NumBytesAllocated = ByteAlignment; - } + unsigned getFreeReg(unsigned virtualReg); /// Moves value from memory into that register - MachineBasicBlock::iterator - moveUseToReg (MachineBasicBlock *MBB, - MachineBasicBlock::iterator I, unsigned VirtReg, - unsigned &PhysReg); + unsigned reloadVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &I, unsigned VirtReg); /// Saves reg value on the stack (maps virtual register to stack value) - MachineBasicBlock::iterator - saveVirtRegToStack (MachineBasicBlock *MBB, - MachineBasicBlock::iterator I, unsigned VirtReg, - unsigned PhysReg); + void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, + unsigned VirtReg, unsigned PhysReg); + }; - MachineBasicBlock::iterator - savePhysRegToStack (MachineBasicBlock *MBB, - MachineBasicBlock::iterator I, unsigned PhysReg); +} - /// runOnFunction - Top level implementation of instruction selection for - /// the entire function. - /// - bool runOnMachineFunction(MachineFunction &Fn); +/// getStackSpaceFor - This allocates space for the specified virtual +/// register to be held on the stack. +int RegAllocSimple::getStackSpaceFor(unsigned VirtReg, + const TargetRegisterClass *RC) { + // Find the location VirtReg would belong... + std::map::iterator I = + StackSlotForVirtReg.lower_bound(VirtReg); - bool runOnFunction(Function &Fn) { - return runOnMachineFunction(MachineFunction::get(&Fn)); - } - }; + if (I != StackSlotForVirtReg.end() && I->first == VirtReg) + return I->second; // Already has space allocated? -} + // Allocate a new stack object for this spill location... + int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC); + + // Assign the slot... + StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); -unsigned RegAllocSimple::allocateStackSpaceFor(unsigned VirtReg, - const TargetRegisterClass *regClass) -{ - if (VirtReg2OffsetMap.find(VirtReg) == VirtReg2OffsetMap.end()) { -#if 0 - unsigned size = regClass->getDataSize(); - unsigned over = NumBytesAllocated - (NumBytesAllocated % ByteAlignment); - if (size >= ByteAlignment - over) { - // need to pad by (ByteAlignment - over) - NumBytesAllocated += ByteAlignment - over; - } - VirtReg2OffsetMap[VirtReg] = NumBytesAllocated; - NumBytesAllocated += size; -#endif - // FIXME: forcing each arg to take 4 bytes on the stack - VirtReg2OffsetMap[VirtReg] = NumBytesAllocated; - NumBytesAllocated += ByteAlignment; - } - return VirtReg2OffsetMap[VirtReg]; + return FrameIdx; } unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) { - const TargetRegisterClass* regClass = MF->getRegClass(virtualReg); - unsigned physReg; - assert(regClass); - if (RegClassIdx.find(regClass) != RegClassIdx.end()) { - unsigned regIdx = RegClassIdx[regClass]++; - assert(regIdx < regClass->getNumRegs() && "Not enough registers!"); - physReg = regClass->getRegister(regIdx); - } else { - physReg = regClass->getRegister(0); - // assert(physReg < regClass->getNumRegs() && "No registers in class!"); - RegClassIdx[regClass] = 1; - } - - if (isAvailableReg(physReg)) - return physReg; - else { - return getFreeReg(virtualReg); + const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg); + TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); + TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); + + while (1) { + unsigned regIdx = RegClassIdx[RC]++; + assert(RI+regIdx != RE && "Not enough registers!"); + unsigned PhysReg = *(RI+regIdx); + + if (!RegsUsed[PhysReg]) + return PhysReg; } } -MachineBasicBlock::iterator -RegAllocSimple::moveUseToReg (MachineBasicBlock *MBB, - MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned &PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(VirtReg); - assert(regClass); - - unsigned stackOffset = allocateStackSpaceFor(VirtReg, regClass); - PhysReg = getFreeReg(VirtReg); +unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &I, + unsigned VirtReg) { + const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + int FrameIdx = getStackSpaceFor(VirtReg, RC); + unsigned PhysReg = getFreeReg(VirtReg); // Add move instruction(s) - return RegInfo->loadRegOffset2Reg(MBB, I, PhysReg, - RegInfo->getFramePointer(), - -stackOffset, regClass->getDataSize()); + ++NumReloaded; + RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC); + return PhysReg; } -MachineBasicBlock::iterator -RegAllocSimple::saveVirtRegToStack (MachineBasicBlock *MBB, - MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(VirtReg); - assert(regClass); - - unsigned stackOffset = allocateStackSpaceFor(VirtReg, regClass); +void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &I, + unsigned VirtReg, unsigned PhysReg) { + const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg); + int FrameIdx = getStackSpaceFor(VirtReg, RC); // Add move instruction(s) - return RegInfo->storeReg2RegOffset(MBB, I, PhysReg, - RegInfo->getFramePointer(), - -stackOffset, regClass->getDataSize()); + ++NumSpilled; + RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC); } -MachineBasicBlock::iterator -RegAllocSimple::savePhysRegToStack (MachineBasicBlock *MBB, - MachineBasicBlock::iterator I, - unsigned PhysReg) -{ - const TargetRegisterClass* regClass = MF->getRegClass(PhysReg); - assert(regClass); - - unsigned offset = allocateStackSpaceFor(PhysReg, regClass); - // Add move instruction(s) - return RegInfo->storeReg2RegOffset(MBB, I, PhysReg, - RegInfo->getFramePointer(), - offset, regClass->getDataSize()); -} - -bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { - cleanupAfterFunction(); +void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { + // loop over each instruction + for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) { + // Made to combat the incorrect allocation of r2 = add r1, r1 + std::map Virt2PhysRegMap; - unsigned virtualReg, physReg; - DEBUG(std::cerr << "Machine Function " << "\n"); - MF = &Fn; + MachineInstr *MI = *I; - for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); - MBB != MBBe; ++MBB) - { - CurrMBB = &(*MBB); - - // Handle PHI instructions specially: add moves to each pred block - while (MBB->front()->getOpcode() == 0) { - MachineInstr *MI = MBB->front(); - // get rid of the phi - MBB->erase(MBB->begin()); + RegsUsed.resize(MRegisterInfo::FirstVirtualRegister); - // a preliminary pass that will invalidate any registers that - // are used by the instruction (including implicit uses) - invalidatePhysRegs(MI); - - DEBUG(std::cerr << "num invalid regs: " << RegsUsed.size() << "\n"); - - DEBUG(std::cerr << "num ops: " << MI->getNumOperands() << "\n"); - MachineOperand &targetReg = MI->getOperand(0); - - // If it's a virtual register, allocate a physical one - // otherwise, just use whatever register is there now - // note: it MUST be a register -- we're assigning to it - virtualReg = (unsigned) targetReg.getAllocatedRegNum(); - if (targetReg.isVirtualRegister()) { - physReg = getFreeReg(virtualReg); - } else { - physReg = virtualReg; - } - - // Find the register class of the target register: should be the - // same as the values we're trying to store there - const TargetRegisterClass* regClass = PhysReg2RegClassMap[physReg]; - assert(regClass && "Target register class not found!"); - unsigned dataSize = regClass->getDataSize(); - - for (int i = MI->getNumOperands() - 1; i >= 2; i-=2) { - MachineOperand &opVal = MI->getOperand(i-1); - - // Get the MachineBasicBlock equivalent of the BasicBlock that is the - // source path the phi - MachineBasicBlock *opBlock = MI->getOperand(i).getMachineBasicBlock(); - MachineBasicBlock::iterator opI = opBlock->end(); - MachineInstr *opMI = *(--opI); - const MachineInstrInfo &MII = TM.getInstrInfo(); - // must backtrack over ALL the branches in the previous block, until no more - while ((MII.isBranch(opMI->getOpcode()) || MII.isReturn(opMI->getOpcode())) - && opI != opBlock->begin()) - { - opMI = *(--opI); - } - // move back to the first branch instruction so new instructions - // are inserted right in front of it and not in front of a non-branch - ++opI; - - - // Retrieve the constant value from this op, move it to target - // register of the phi - if (opVal.getType() == MachineOperand::MO_SignExtendedImmed || - opVal.getType() == MachineOperand::MO_UnextendedImmed) - { - opI = RegInfo->moveImm2Reg(opBlock, opI, physReg, - (unsigned) opVal.getImmedValue(), - dataSize); - saveVirtRegToStack(opBlock, opI, virtualReg, physReg); - } else { - // Allocate a physical register and add a move in the BB - unsigned opVirtualReg = (unsigned) opVal.getAllocatedRegNum(); - unsigned opPhysReg; // = getFreeReg(opVirtualReg); - opI = moveUseToReg(opBlock, opI, opVirtualReg, physReg); - //opI = RegInfo->moveReg2Reg(opBlock, opI, physReg, opPhysReg, - // dataSize); - // Save that register value to the stack of the TARGET REG - saveVirtRegToStack(opBlock, opI, virtualReg, physReg); - } - - // make regs available to other instructions - clearAllRegs(); - } + // a preliminary pass that will invalidate any registers that + // are used by the instruction (including implicit uses) + unsigned Opcode = MI->getOpcode(); + const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode); + if (const unsigned *Regs = Desc.ImplicitUses) + while (*Regs) + RegsUsed[*Regs++] = true; + + if (const unsigned *Regs = Desc.ImplicitDefs) + while (*Regs) + RegsUsed[*Regs++] = true; + + // Loop over uses, move from memory into registers + for (int i = MI->getNumOperands() - 1; i >= 0; --i) { + MachineOperand &op = MI->getOperand(i); - // really delete the instruction - delete MI; - } - - //loop over each basic block - for (MachineBasicBlock::iterator I = MBB->begin(); I != MBB->end(); ++I) - { - MachineInstr *MI = *I; - - // a preliminary pass that will invalidate any registers that - // are used by the instruction (including implicit uses) - invalidatePhysRegs(MI); - - // Loop over uses, move from memory into registers - for (int i = MI->getNumOperands() - 1; i >= 0; --i) { - MachineOperand &op = MI->getOperand(i); - - if (op.getType() == MachineOperand::MO_SignExtendedImmed || - op.getType() == MachineOperand::MO_UnextendedImmed) - { - DEBUG(std::cerr << "const\n"); - } else if (op.isVirtualRegister()) { - virtualReg = (unsigned) op.getAllocatedRegNum(); - DEBUG(std::cerr << "op: " << op << "\n"); - DEBUG(std::cerr << "\t inst[" << i << "]: "; - MI->print(std::cerr, TM)); - - // make sure the same virtual register maps to the same physical - // register in any given instruction - if (VirtReg2PhysRegMap.find(virtualReg) != VirtReg2PhysRegMap.end()) { - physReg = VirtReg2PhysRegMap[virtualReg]; - } else { - if (op.opIsDef()) { - if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { - // must be same register number as the first operand - // This maps a = b + c into b += c, and saves b into a's spot - physReg = (unsigned) MI->getOperand(1).getAllocatedRegNum(); - } else { - physReg = getFreeReg(virtualReg); - } - MachineBasicBlock::iterator J = I; - J = saveVirtRegToStack(CurrMBB, ++J, virtualReg, physReg); - I = --J; + if (op.isVirtualRegister()) { + unsigned virtualReg = (unsigned) op.getAllocatedRegNum(); + DEBUG(std::cerr << "op: " << op << "\n"); + DEBUG(std::cerr << "\t inst[" << i << "]: "; + MI->print(std::cerr, *TM)); + + // make sure the same virtual register maps to the same physical + // register in any given instruction + unsigned physReg = Virt2PhysRegMap[virtualReg]; + if (physReg == 0) { + if (op.opIsDef()) { + if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) { + // must be same register number as the first operand + // This maps a = b + c into b += c, and saves b into a's spot + assert(MI->getOperand(1).isRegister() && + MI->getOperand(1).getAllocatedRegNum() && + MI->getOperand(1).opIsUse() && + "Two address instruction invalid!"); + + physReg = MI->getOperand(1).getAllocatedRegNum(); } else { - I = moveUseToReg(CurrMBB, I, virtualReg, physReg); + physReg = getFreeReg(virtualReg); } - VirtReg2PhysRegMap[virtualReg] = physReg; + ++I; + spillVirtReg(MBB, I, virtualReg, physReg); + --I; + } else { + physReg = reloadVirtReg(MBB, I, virtualReg); + Virt2PhysRegMap[virtualReg] = physReg; } - MI->SetMachineOperandReg(i, physReg); - DEBUG(std::cerr << "virt: " << virtualReg << - ", phys: " << op.getAllocatedRegNum() << "\n"); } + MI->SetMachineOperandReg(i, physReg); + DEBUG(std::cerr << "virt: " << virtualReg << + ", phys: " << op.getAllocatedRegNum() << "\n"); } - - clearAllRegs(); - VirtReg2PhysRegMap.clear(); } - + RegClassIdx.clear(); + RegsUsed.clear(); } +} - // add prologue we should preserve callee-save registers... - MachineFunction::iterator Fi = Fn.begin(); - MachineBasicBlock *MBB = Fi; - MachineBasicBlock::iterator MBBi = MBB->begin(); - RegInfo->emitPrologue(MBB, MBBi, NumBytesAllocated); - // add epilogue to restore the callee-save registers - // loop over the basic block +/// runOnMachineFunction - Register allocate the whole function +/// +bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { + DEBUG(std::cerr << "Machine Function " << "\n"); + MF = &Fn; + TM = &MF->getTarget(); + RegInfo = TM->getRegisterInfo(); + + // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); MBB != MBBe; ++MBB) - { - // check if last instruction is a RET - MachineBasicBlock::iterator I = (*MBB).end(); - MachineInstr *MI = *(--I); - const MachineInstrInfo &MII = TM.getInstrInfo(); - if (MII.isReturn(MI->getOpcode())) { - // this block has a return instruction, add epilogue - RegInfo->emitEpilogue(MBB, I, NumBytesAllocated); - } - } + AllocateBasicBlock(*MBB); - return false; // We never modify the LLVM itself. + StackSlotForVirtReg.clear(); + return true; } -Pass *createSimpleX86RegisterAllocator(TargetMachine &TM) { - return new RegAllocSimple(TM); +Pass *createSimpleRegisterAllocator() { + return new RegAllocSimple(); }