X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocSimple.cpp;h=7dc98904abcc9b8625b41b8dd337ae91e4600a2b;hb=f6e29499ac036821e7f84e264663c24888d68c78;hp=081edd8d5eb8b0a5f8b3b2c8bbe36e4b3687a44e;hpb=c9235d2e855c56e9aa157969f8132a05f9ba89d8;p=oota-llvm.git

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 081edd8d5eb..7dc98904abc 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -35,17 +35,18 @@ STATISTIC(NumLoads , "Number of loads added");
 
 namespace {
   static RegisterRegAlloc
-    simpleRegAlloc("simple", "  simple register allocator",
+    simpleRegAlloc("simple", "simple register allocator",
                    createSimpleRegisterAllocator);
 
   class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
   public:
     static char ID;
-    RegAllocSimple() : MachineFunctionPass((intptr_t)&ID) {}
+    RegAllocSimple() : MachineFunctionPass(&ID) {}
   private:
     MachineFunction *MF;
     const TargetMachine *TM;
     const TargetRegisterInfo *TRI;
+    const TargetInstrInfo *TII;
 
     // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
     // these values are spilled
@@ -103,10 +104,9 @@ namespace {
 int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
                                      const TargetRegisterClass *RC) {
   // Find the location VirtReg would belong...
-  std::map<unsigned, int>::iterator I =
-    StackSlotForVirtReg.lower_bound(VirtReg);
+  std::map<unsigned, int>::iterator I = StackSlotForVirtReg.find(VirtReg);
 
-  if (I != StackSlotForVirtReg.end() && I->first == VirtReg)
+  if (I != StackSlotForVirtReg.end())
     return I->second;          // Already has space allocated?
 
   // Allocate a new stack object for this spill location...
@@ -145,7 +145,6 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
 
   // Add move instruction(s)
   ++NumLoads;
-  const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
   TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
   return PhysReg;
 }
@@ -154,7 +153,6 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I,
                                   unsigned VirtReg, unsigned PhysReg) {
   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
-  const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
   
   int FrameIdx = getStackSpaceFor(VirtReg, RC);
 
@@ -190,12 +188,12 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
 
     // Loop over uses, move from memory into registers.
     for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
-      MachineOperand &op = MI->getOperand(i);
+      MachineOperand &MO = MI->getOperand(i);
 
-      if (op.isRegister() && op.getReg() &&
-          TargetRegisterInfo::isVirtualRegister(op.getReg())) {
-        unsigned virtualReg = (unsigned) op.getReg();
-        DOUT << "op: " << op << "\n";
+      if (MO.isReg() && MO.getReg() &&
+          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
+        unsigned virtualReg = (unsigned) MO.getReg();
+        DOUT << "op: " << MO << "\n";
         DOUT << "\t inst[" << i << "]: ";
         DEBUG(MI->print(*cerr.stream(), TM));
 
@@ -203,7 +201,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
         // register in any given instruction
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
-          if (op.isDef()) {
+          if (MO.isDef()) {
             int TiedOp = Desc.findTiedToSrcOperand(i);
             if (TiedOp == -1) {
               physReg = getFreeReg(virtualReg);
@@ -211,7 +209,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
               // must be same register number as the source operand that is 
               // tied to. This maps a = b + c into b = b + c, and saves b into
               // a's spot.
-              assert(MI->getOperand(TiedOp).isRegister()  &&
+              assert(MI->getOperand(TiedOp).isReg()  &&
                      MI->getOperand(TiedOp).getReg() &&
                      MI->getOperand(TiedOp).isUse() &&
                      "Two address instruction invalid!");
@@ -224,8 +222,8 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
             Virt2PhysRegMap[virtualReg] = physReg;
           }
         }
-        MI->getOperand(i).setReg(physReg);
-        DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
+        MO.setReg(physReg);
+        DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n";
       }
     }
     RegClassIdx.clear();
@@ -241,6 +239,7 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
   MF = &Fn;
   TM = &MF->getTarget();
   TRI = TM->getRegisterInfo();
+  TII = TM->getInstrInfo();
 
   // Loop over all of the basic blocks, eliminating virtual register references
   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();