X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegisterScavenging.cpp;h=c1d7ff97e44e74711465e79c85441538b9e5d83e;hb=f6e29499ac036821e7f84e264663c24888d68c78;hp=2535d78cd989c613ee355f4928b3d839b6b02475;hpb=d68f47c6fd744e051f7f2d97b6366d40bf27c438;p=oota-llvm.git diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index 2535d78cd98..c1d7ff97e44 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -19,9 +19,11 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/STLExtras.h" using namespace llvm; @@ -33,13 +35,14 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg, bool SeenSuperDef = false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister()) + if (!MO.isReg()) continue; - if (TRI->isSuperRegister(SubReg, MO.getReg())) + if (TRI->isSuperRegister(SubReg, MO.getReg())) { if (MO.isUse()) SeenSuperUse = true; else if (MO.isImplicit()) SeenSuperDef = true; + } } return SeenSuperDef && SeenSuperUse; @@ -48,34 +51,41 @@ static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg, static bool RedefinesSuperRegPart(const MachineInstr *MI, const MachineOperand &MO, const TargetRegisterInfo *TRI) { - assert(MO.isRegister() && MO.isDef() && "Not a register def!"); + assert(MO.isReg() && MO.isDef() && "Not a register def!"); return RedefinesSuperRegPart(MI, MO.getReg(), TRI); } /// setUsed - Set the register and its sub-registers as being used. -void RegScavenger::setUsed(unsigned Reg) { +void RegScavenger::setUsed(unsigned Reg, bool ImpDef) { RegsAvailable.reset(Reg); + ImplicitDefed[Reg] = ImpDef; for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); - unsigned SubReg = *SubRegs; ++SubRegs) + unsigned SubReg = *SubRegs; ++SubRegs) { RegsAvailable.reset(SubReg); + ImplicitDefed[SubReg] = ImpDef; + } } /// setUnused - Set the register and its sub-registers as being unused. void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) { RegsAvailable.set(Reg); + ImplicitDefed.reset(Reg); for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) - if (!RedefinesSuperRegPart(MI, Reg, TRI)) + if (!RedefinesSuperRegPart(MI, Reg, TRI)) { RegsAvailable.set(SubReg); + ImplicitDefed.reset(SubReg); + } } void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { - const MachineFunction &MF = *mbb->getParent(); + MachineFunction &MF = *mbb->getParent(); const TargetMachine &TM = MF.getTarget(); TII = TM.getInstrInfo(); TRI = TM.getRegisterInfo(); + MRI = &MF.getRegInfo(); assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && "Target changed?"); @@ -83,6 +93,7 @@ void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) { if (!MBB) { NumPhysRegs = TRI->getNumRegs(); RegsAvailable.resize(NumPhysRegs); + ImplicitDefed.resize(NumPhysRegs); // Create reserved registers bitvector. ReservedRegs = TRI->getReservedRegs(MF); @@ -119,7 +130,7 @@ void RegScavenger::restoreScavengedReg() { return; TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg, - ScavengingFrameIndex, ScavengedRC); + ScavengingFrameIndex, ScavengedRC); MachineBasicBlock::iterator II = prior(MBBI); TRI->eliminateFrameIndex(II, 0, this); setUsed(ScavengedReg); @@ -127,6 +138,40 @@ void RegScavenger::restoreScavengedReg() { ScavengedRC = NULL; } +/// isLiveInButUnusedBefore - Return true if register is livein the MBB not +/// not used before it reaches the MI that defines register. +static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI, + MachineBasicBlock *MBB, + const TargetRegisterInfo *TRI, + MachineRegisterInfo* MRI) { + // First check if register is livein. + bool isLiveIn = false; + for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), + E = MBB->livein_end(); I != E; ++I) + if (Reg == *I || TRI->isSuperRegister(Reg, *I)) { + isLiveIn = true; + break; + } + if (!isLiveIn) + return false; + + // Is there any use of it before the specified MI? + SmallPtrSet UsesInMBB; + for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), + UE = MRI->use_end(); UI != UE; ++UI) { + MachineInstr *UseMI = &*UI; + if (UseMI->getParent() == MBB) + UsesInMBB.insert(UseMI); + } + if (UsesInMBB.empty()) + return true; + + for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I) + if (UsesInMBB.count(&*I)) + return false; + return true; +} + void RegScavenger::forward() { // Move ptr forward. if (!Tracking) { @@ -149,7 +194,7 @@ void RegScavenger::forward() { BitVector ChangedRegs(NumPhysRegs); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); @@ -170,8 +215,7 @@ void RegScavenger::forward() { // instruction. for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); unsigned SubReg = *SubRegs; ++SubRegs) - if (!RedefinesSuperRegPart(MI, Reg, TRI)) - ChangedRegs.set(SubReg); + ChangedRegs.set(SubReg); } } @@ -180,10 +224,11 @@ void RegScavenger::forward() { setUnused(ChangedRegs); // Process defs. + bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; unsigned Reg = MO.getReg(); @@ -204,9 +249,13 @@ void RegScavenger::forward() { if (RedefinesSuperRegPart(MI, MO, TRI)) continue; - assert((isUnused(Reg) || isReserved(Reg)) && + // Implicit def is allowed to "re-define" any register. Similarly, + // implicitly defined registers can be clobbered. + assert((isReserved(Reg) || isUnused(Reg) || + IsImpDef || isImplicitlyDefined(Reg) || + isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && "Re-defining a live register!"); - setUsed(Reg); + setUsed(Reg, IsImpDef); } } @@ -221,7 +270,7 @@ void RegScavenger::backward() { const TargetInstrDesc &TID = MI->getDesc(); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isDef()) + if (!MO.isReg() || !MO.isDef()) continue; // Skip two-address destination operand. if (TID.findTiedToSrcOperand(i) != -1) @@ -236,7 +285,7 @@ void RegScavenger::backward() { BitVector ChangedRegs(NumPhysRegs); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) @@ -329,7 +378,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, // Exclude all the registers being used by the instruction. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { MachineOperand &MO = I->getOperand(i); - if (MO.isRegister()) + if (MO.isReg()) Candidates.reset(MO.getReg()); }