X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FScheduleDAGEmit.cpp;h=770f5bbbdbb1d8d98a1bc4f4700a998ec9a96214;hb=ef4cfc749a61d0d0252196c957697436ba7ec068;hp=ce3283dc3df1adda09f7c74886fa44db3c99217d;hpb=343f0c046702831a4a6aec951b6a297a23241a55;p=oota-llvm.git diff --git a/lib/CodeGen/ScheduleDAGEmit.cpp b/lib/CodeGen/ScheduleDAGEmit.cpp index ce3283dc3df..770f5bbbdbb 100644 --- a/lib/CodeGen/ScheduleDAGEmit.cpp +++ b/lib/CodeGen/ScheduleDAGEmit.cpp @@ -29,42 +29,41 @@ using namespace llvm; void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) { - MI->addMemOperand(*MF, MO); + MI->addMemOperand(MF, MO); } void ScheduleDAG::EmitNoop() { - TII->insertNoop(*BB, BB->end()); + TII->insertNoop(*BB, InsertPos); } -void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, +void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, DenseMap &VRBaseMap) { for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { - if (I->isCtrl) continue; // ignore chain preds - if (I->Dep->CopyDstRC) { + if (I->isCtrl()) continue; // ignore chain preds + if (I->getSUnit()->CopyDstRC) { // Copy to physical register. - DenseMap::iterator VRI = VRBaseMap.find(I->Dep); + DenseMap::iterator VRI = VRBaseMap.find(I->getSUnit()); assert(VRI != VRBaseMap.end() && "Node emitted out of order - late"); // Find the destination physical register. unsigned Reg = 0; for (SUnit::const_succ_iterator II = SU->Succs.begin(), EE = SU->Succs.end(); II != EE; ++II) { - if (I->Reg) { - Reg = I->Reg; + if (II->getReg()) { + Reg = II->getReg(); break; } } - assert(I->Reg && "Unknown physical register!"); - TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second, + TII->copyRegToReg(*BB, InsertPos, Reg, VRI->second, SU->CopyDstRC, SU->CopySrcRC); } else { // Copy from physical register. - assert(I->Reg && "Unknown physical register!"); + assert(I->getReg() && "Unknown physical register!"); unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC); bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second; isNew = isNew; // Silence compiler warning. assert(isNew && "Node emitted out of order - early"); - TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, + TII->copyRegToReg(*BB, InsertPos, VRBase, I->getReg(), SU->CopyDstRC, SU->CopySrcRC); } break;