X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FScheduleDAGInstrs.cpp;h=8e18b3d17fda28e37b3a04a825690cdf6e5ffbd5;hb=236aa8a5032282d8793b537c0f3f7ffb381a83d4;hp=c162d0e3dcb044e4fa489c2674c407f1415fc14d;hpb=0b1d4a798d1dd2f39521b6b381cd1c1911c9ab52;p=oota-llvm.git diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index c162d0e3dcb..8e18b3d17fd 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -13,97 +13,133 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "sched-instrs" -#include "llvm/CodeGen/MachineDominators.h" +#include "ScheduleDAGInstrs.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/ScheduleDAGInstrs.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtarget.h" -#include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/SmallSet.h" -#include using namespace llvm; -namespace { - class VISIBILITY_HIDDEN LoopDependencies { - const MachineLoopInfo &MLI; - const MachineDominatorTree &MDT; - - public: - typedef std::map > - LoopDeps; - LoopDeps Deps; - - LoopDependencies(const MachineLoopInfo &mli, - const MachineDominatorTree &mdt) : - MLI(mli), MDT(mdt) {} - - void VisitLoop(const MachineLoop *Loop) { - Deps.clear(); - MachineBasicBlock *Header = Loop->getHeader(); - SmallSet LoopLiveIns; - for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(), - LE = Header->livein_end(); LI != LE; ++LI) - LoopLiveIns.insert(*LI); - - VisitRegion(MDT.getNode(Header), Loop, LoopLiveIns); - } +ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, + const MachineLoopInfo &mli, + const MachineDominatorTree &mdt) + : ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {} + +/// Run - perform scheduling. +/// +void ScheduleDAGInstrs::Run(MachineBasicBlock *bb, + MachineBasicBlock::iterator begin, + MachineBasicBlock::iterator end, + unsigned endcount) { + BB = bb; + Begin = begin; + InsertPosIndex = endcount; + + ScheduleDAG::Run(bb, end); +} - private: - void VisitRegion(const MachineDomTreeNode *Node, - const MachineLoop *Loop, - const SmallSet &LoopLiveIns) { - MachineBasicBlock *MBB = Node->getBlock(); - if (!Loop->contains(MBB)) return; - - unsigned Count = 0; - for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); - I != E; ++I, ++Count) { - const MachineInstr *MI = I; - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isUse()) - continue; - unsigned MOReg = MO.getReg(); - if (LoopLiveIns.count(MOReg)) - Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count))); - } - } +/// getOpcode - If this is an Instruction or a ConstantExpr, return the +/// opcode value. Otherwise return UserOp1. +static unsigned getOpcode(const Value *V) { + if (const Instruction *I = dyn_cast(V)) + return I->getOpcode(); + if (const ConstantExpr *CE = dyn_cast(V)) + return CE->getOpcode(); + // Use UserOp1 to mean there's no opcode. + return Instruction::UserOp1; +} - const std::vector &Children = Node->getChildren(); - for (unsigned I = 0, E = Children.size(); I != E; ++I) - VisitRegion(Children[I], Loop, LoopLiveIns); +/// getUnderlyingObjectFromInt - This is the function that does the work of +/// looking through basic ptrtoint+arithmetic+inttoptr sequences. +static const Value *getUnderlyingObjectFromInt(const Value *V) { + do { + if (const User *U = dyn_cast(V)) { + // If we find a ptrtoint, we can transfer control back to the + // regular getUnderlyingObjectFromInt. + if (getOpcode(U) == Instruction::PtrToInt) + return U->getOperand(0); + // If we find an add of a constant or a multiplied value, it's + // likely that the other operand will lead us to the base + // object. We don't have to worry about the case where the + // object address is somehow being computed bt the multiply, + // because our callers only care when the result is an + // identifibale object. + if (getOpcode(U) != Instruction::Add || + (!isa(U->getOperand(1)) && + getOpcode(U->getOperand(1)) != Instruction::Mul)) + return V; + V = U->getOperand(0); + } else { + return V; } - }; + assert(isa(V->getType()) && "Unexpected operand type!"); + } while (1); } -ScheduleDAGInstrs::ScheduleDAGInstrs(MachineBasicBlock *bb, - const TargetMachine &tm, - const MachineLoopInfo &mli, - const MachineDominatorTree &mdt) - : ScheduleDAG(0, bb, tm), MLI(mli), MDT(mdt) {} +/// getUnderlyingObject - This is a wrapper around Value::getUnderlyingObject +/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences. +static const Value *getUnderlyingObject(const Value *V) { + // First just call Value::getUnderlyingObject to let it do what it does. + do { + V = V->getUnderlyingObject(); + // If it found an inttoptr, use special code to continue climing. + if (getOpcode(V) != Instruction::IntToPtr) + break; + const Value *O = getUnderlyingObjectFromInt(cast(V)->getOperand(0)); + // If that succeeded in finding a pointer, continue the search. + if (!isa(O->getType())) + break; + V = O; + } while (1); + return V; +} + +/// getUnderlyingObjectForInstr - If this machine instr has memory reference +/// information and it can be tracked to a normal reference to a known +/// object, return the Value for that object. Otherwise return null. +static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI) { + if (!MI->hasOneMemOperand() || + !MI->memoperands_begin()->getValue() || + MI->memoperands_begin()->isVolatile()) + return 0; + + const Value *V = MI->memoperands_begin()->getValue(); + if (!V) + return 0; + + V = getUnderlyingObject(V); + if (!isa(V) && !isIdentifiedObject(V)) + return 0; + + return V; +} + +void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) { + if (MachineLoop *ML = MLI.getLoopFor(BB)) + if (BB == ML->getLoopLatch()) { + MachineBasicBlock *Header = ML->getHeader(); + for (MachineBasicBlock::livein_iterator I = Header->livein_begin(), + E = Header->livein_end(); I != E; ++I) + LoopLiveInRegs.insert(*I); + LoopRegs.VisitLoop(ML); + } +} void ScheduleDAGInstrs::BuildSchedGraph() { - SUnits.clear(); + // We'll be allocating one SUnit for each instruction, plus one for + // the region exit node. SUnits.reserve(BB->size()); // We build scheduling units by walking a block's instruction list from bottom // to top. - // Remember where defs and uses of each physical register are as we procede. - std::vector Defs[TargetRegisterInfo::FirstVirtualRegister] = {}; - std::vector Uses[TargetRegisterInfo::FirstVirtualRegister] = {}; - - // Remember where unknown loads are after the most recent unknown store - // as we procede. - std::vector PendingLoads; - // Remember where a generic side-effecting instruction is as we procede. If // ChainMMO is null, this is assumed to have arbitrary side-effects. If // ChainMMO is non-null, then Chain makes only a single memory reference. @@ -115,24 +151,6 @@ void ScheduleDAGInstrs::BuildSchedGraph() { std::map MemDefs; std::map > MemUses; - // Terminators can perform control transfers, we we need to make sure that - // all the work of the block is done before the terminator. - SUnit *Terminator = 0; - - LoopDependencies LoopRegs(MLI, MDT); - - // Track which regs are live into a loop, to help guide back-edge-aware - // scheduling. - SmallSet LoopLiveInRegs; - if (MachineLoop *ML = MLI.getLoopFor(BB)) - if (BB == ML->getLoopLatch()) { - MachineBasicBlock *Header = ML->getHeader(); - for (MachineBasicBlock::livein_iterator I = Header->livein_begin(), - E = Header->livein_end(); I != E; ++I) - LoopLiveInRegs.insert(*I); - LoopRegs.VisitLoop(ML); - } - // Check to see if the scheduler cares about latencies. bool UnitLatencies = ForceUnitLatencies(); @@ -140,10 +158,14 @@ void ScheduleDAGInstrs::BuildSchedGraph() { unsigned SpecialAddressLatency = TM.getSubtarget().getSpecialAddressLatency(); - for (MachineBasicBlock::iterator MII = BB->end(), MIE = BB->begin(); + // Walk the list of instructions, from bottom moving up. + for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; MII != MIE; --MII) { MachineInstr *MI = prior(MII); const TargetInstrDesc &TID = MI->getDesc(); + assert(!TID.isTerminator() && !MI->isLabel() && + "Cannot schedule terminators or labels!"); + // Create the SUnit for this MI. SUnit *SU = NewSUnit(MI); // Assign the Latency field of SU using target-provided information. @@ -218,8 +240,7 @@ void ScheduleDAGInstrs::BuildSchedGraph() { // If a def is going to wrap back around to the top of the loop, // backschedule it. - // TODO: Blocks in loops without terminators can benefit too. - if (!UnitLatencies && Terminator && DefList.empty()) { + if (!UnitLatencies && DefList.empty()) { LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg); if (I != LoopRegs.Deps.end()) { const MachineOperand *UseMO = I->second.first; @@ -243,10 +264,10 @@ void ScheduleDAGInstrs::BuildSchedGraph() { // scheduling region. Latency -= std::min(Latency, Count); // Add the artifical edge. - Terminator->addPred(SDep(SU, SDep::Order, Latency, - /*Reg=*/0, /*isNormalMemory=*/false, - /*isMustAlias=*/false, - /*isArtificial=*/true)); + ExitSU.addPred(SDep(SU, SDep::Order, Latency, + /*Reg=*/0, /*isNormalMemory=*/false, + /*isMustAlias=*/false, + /*isArtificial=*/true)); } else if (SpecialAddressLatency > 0 && UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) { // The entire loop body is within the current scheduling region @@ -275,7 +296,7 @@ void ScheduleDAGInstrs::BuildSchedGraph() { // after stack slots are lowered to actual addresses. // TODO: Use an AliasAnalysis and do real alias-analysis queries, and // produce more precise dependence information. - if (TID.isCall() || TID.isTerminator() || TID.hasUnmodeledSideEffects()) { + if (TID.isCall() || TID.hasUnmodeledSideEffects()) { new_chain: // This is the conservative case. Add dependencies on all memory // references. @@ -299,7 +320,7 @@ void ScheduleDAGInstrs::BuildSchedGraph() { // See if it is known to just have a single memory reference. MachineInstr *ChainMI = Chain->getInstr(); const TargetInstrDesc &ChainTID = ChainMI->getDesc(); - if (!ChainTID.isCall() && !ChainTID.isTerminator() && + if (!ChainTID.isCall() && !ChainTID.hasUnmodeledSideEffects() && ChainMI->hasOneMemOperand() && !ChainMI->memoperands_begin()->isVolatile() && @@ -310,12 +331,8 @@ void ScheduleDAGInstrs::BuildSchedGraph() { // Unknown memory accesses. Assume the worst. ChainMMO = 0; } else if (TID.mayStore()) { - if (MI->hasOneMemOperand() && - MI->memoperands_begin()->getValue() && - !MI->memoperands_begin()->isVolatile() && - isa(MI->memoperands_begin()->getValue())) { + if (const Value *V = getUnderlyingObjectForInstr(MI)) { // A store to a specific PseudoSourceValue. Add precise dependencies. - const Value *V = MI->memoperands_begin()->getValue(); // Handle the def in MemDefs, if there is one. std::map::iterator I = MemDefs.find(V); if (I != MemDefs.end()) { @@ -334,6 +351,10 @@ void ScheduleDAGInstrs::BuildSchedGraph() { /*isNormalMemory=*/true)); J->second.clear(); } + // Add dependencies from all the PendingLoads, since without + // memoperands we must assume they alias anything. + for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) + PendingLoads[k]->addPred(SDep(SU, SDep::Order, SU->Latency)); // Add a general dependence too, if needed. if (Chain) Chain->addPred(SDep(SU, SDep::Order, SU->Latency)); @@ -343,12 +364,8 @@ void ScheduleDAGInstrs::BuildSchedGraph() { } else if (TID.mayLoad()) { if (TII->isInvariantLoad(MI)) { // Invariant load, no chain dependencies needed! - } else if (MI->hasOneMemOperand() && - MI->memoperands_begin()->getValue() && - !MI->memoperands_begin()->isVolatile() && - isa(MI->memoperands_begin()->getValue())) { + } else if (const Value *V = getUnderlyingObjectForInstr(MI)) { // A load from a specific PseudoSourceValue. Add precise dependencies. - const Value *V = MI->memoperands_begin()->getValue(); std::map::iterator I = MemDefs.find(V); if (I != MemDefs.end()) I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0, @@ -364,20 +381,29 @@ void ScheduleDAGInstrs::BuildSchedGraph() { // cases where memoperand information is unavailable. goto new_chain; } else { - // A normal load. Just depend on the general chain. + // A normal load. Depend on the general chain, as well as on + // all stores. In the absense of MachineMemOperand information, + // we can't even assume that the load doesn't alias well-behaved + // memory locations. if (Chain) Chain->addPred(SDep(SU, SDep::Order, SU->Latency)); + for (std::map::iterator I = MemDefs.begin(), + E = MemDefs.end(); I != E; ++I) + I->second->addPred(SDep(SU, SDep::Order, SU->Latency)); PendingLoads.push_back(SU); } } + } - // Add chain edges from the terminator to ensure that all the work of the - // block is completed before any control transfers. - if (Terminator && SU->Succs.empty()) - Terminator->addPred(SDep(SU, SDep::Order, SU->Latency)); - if (TID.isTerminator() || MI->isLabel()) - Terminator = SU; + for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) { + Defs[i].clear(); + Uses[i].clear(); } + PendingLoads.clear(); +} + +void ScheduleDAGInstrs::FinishBlock() { + // Nothing to do. } void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) { @@ -402,7 +428,12 @@ void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { std::string s; raw_string_ostream oss(s); - SU->getInstr()->print(oss); + if (SU == &EntrySU) + oss << ""; + else if (SU == &ExitSU) + oss << ""; + else + SU->getInstr()->print(oss); return oss.str(); } @@ -410,8 +441,11 @@ std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() { // For MachineInstr-based scheduling, we're rescheduling the instructions in // the block, so start by removing them from the block. - while (!BB->empty()) - BB->remove(BB->begin()); + while (Begin != InsertPos) { + MachineBasicBlock::iterator I = Begin; + ++Begin; + BB->remove(I); + } // Then re-insert them according to the given schedule. for (unsigned i = 0, e = Sequence.size(); i != e; i++) { @@ -422,8 +456,13 @@ MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() { continue; } - BB->push_back(SU->getInstr()); + BB->insert(InsertPos, SU->getInstr()); } + // Update the Begin iterator, as the first instruction in the block + // may have been scheduled later. + if (!Sequence.empty()) + Begin = Sequence[0]->getInstr(); + return BB; }