X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FScheduleDAGInstrs.cpp;h=8e18b3d17fda28e37b3a04a825690cdf6e5ffbd5;hb=ef4cfc749a61d0d0252196c957697436ba7ec068;hp=fa42d393a3be3ee5d742c18cd94ac1fcdc533342;hpb=4ea8e85e19b844ef0ff704f27959b6a2ea7369f9;p=oota-llvm.git diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index fa42d393a3b..8e18b3d17fd 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -13,35 +13,133 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "sched-instrs" -#include "llvm/CodeGen/ScheduleDAGInstrs.h" +#include "ScheduleDAGInstrs.h" +#include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Target/TargetSubtarget.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#include +#include "llvm/ADT/SmallSet.h" using namespace llvm; -ScheduleDAGInstrs::ScheduleDAGInstrs(MachineBasicBlock *bb, - const TargetMachine &tm) - : ScheduleDAG(0, bb, tm) {} +ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, + const MachineLoopInfo &mli, + const MachineDominatorTree &mdt) + : ScheduleDAG(mf), MLI(mli), MDT(mdt), LoopRegs(MLI, MDT) {} -void ScheduleDAGInstrs::BuildSchedUnits() { - SUnits.clear(); +/// Run - perform scheduling. +/// +void ScheduleDAGInstrs::Run(MachineBasicBlock *bb, + MachineBasicBlock::iterator begin, + MachineBasicBlock::iterator end, + unsigned endcount) { + BB = bb; + Begin = begin; + InsertPosIndex = endcount; + + ScheduleDAG::Run(bb, end); +} + +/// getOpcode - If this is an Instruction or a ConstantExpr, return the +/// opcode value. Otherwise return UserOp1. +static unsigned getOpcode(const Value *V) { + if (const Instruction *I = dyn_cast(V)) + return I->getOpcode(); + if (const ConstantExpr *CE = dyn_cast(V)) + return CE->getOpcode(); + // Use UserOp1 to mean there's no opcode. + return Instruction::UserOp1; +} + +/// getUnderlyingObjectFromInt - This is the function that does the work of +/// looking through basic ptrtoint+arithmetic+inttoptr sequences. +static const Value *getUnderlyingObjectFromInt(const Value *V) { + do { + if (const User *U = dyn_cast(V)) { + // If we find a ptrtoint, we can transfer control back to the + // regular getUnderlyingObjectFromInt. + if (getOpcode(U) == Instruction::PtrToInt) + return U->getOperand(0); + // If we find an add of a constant or a multiplied value, it's + // likely that the other operand will lead us to the base + // object. We don't have to worry about the case where the + // object address is somehow being computed bt the multiply, + // because our callers only care when the result is an + // identifibale object. + if (getOpcode(U) != Instruction::Add || + (!isa(U->getOperand(1)) && + getOpcode(U->getOperand(1)) != Instruction::Mul)) + return V; + V = U->getOperand(0); + } else { + return V; + } + assert(isa(V->getType()) && "Unexpected operand type!"); + } while (1); +} + +/// getUnderlyingObject - This is a wrapper around Value::getUnderlyingObject +/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences. +static const Value *getUnderlyingObject(const Value *V) { + // First just call Value::getUnderlyingObject to let it do what it does. + do { + V = V->getUnderlyingObject(); + // If it found an inttoptr, use special code to continue climing. + if (getOpcode(V) != Instruction::IntToPtr) + break; + const Value *O = getUnderlyingObjectFromInt(cast(V)->getOperand(0)); + // If that succeeded in finding a pointer, continue the search. + if (!isa(O->getType())) + break; + V = O; + } while (1); + return V; +} + +/// getUnderlyingObjectForInstr - If this machine instr has memory reference +/// information and it can be tracked to a normal reference to a known +/// object, return the Value for that object. Otherwise return null. +static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI) { + if (!MI->hasOneMemOperand() || + !MI->memoperands_begin()->getValue() || + MI->memoperands_begin()->isVolatile()) + return 0; + + const Value *V = MI->memoperands_begin()->getValue(); + if (!V) + return 0; + + V = getUnderlyingObject(V); + if (!isa(V) && !isIdentifiedObject(V)) + return 0; + + return V; +} + +void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) { + if (MachineLoop *ML = MLI.getLoopFor(BB)) + if (BB == ML->getLoopLatch()) { + MachineBasicBlock *Header = ML->getHeader(); + for (MachineBasicBlock::livein_iterator I = Header->livein_begin(), + E = Header->livein_end(); I != E; ++I) + LoopLiveInRegs.insert(*I); + LoopRegs.VisitLoop(ML); + } +} + +void ScheduleDAGInstrs::BuildSchedGraph() { + // We'll be allocating one SUnit for each instruction, plus one for + // the region exit node. SUnits.reserve(BB->size()); // We build scheduling units by walking a block's instruction list from bottom // to top. - // Remember where defs and uses of each physical register are as we procede. - SUnit *Defs[TargetRegisterInfo::FirstVirtualRegister] = {}; - std::vector Uses[TargetRegisterInfo::FirstVirtualRegister] = {}; - - // Remember where unknown loads are after the most recent unknown store - // as we procede. - std::vector PendingLoads; - // Remember where a generic side-effecting instruction is as we procede. If // ChainMMO is null, this is assumed to have arbitrary side-effects. If // ChainMMO is non-null, then Chain makes only a single memory reference. @@ -53,17 +151,28 @@ void ScheduleDAGInstrs::BuildSchedUnits() { std::map MemDefs; std::map > MemUses; - // Terminators can perform control transfers, we we need to make sure that - // all the work of the block is done before the terminator. - SUnit *Terminator = 0; + // Check to see if the scheduler cares about latencies. + bool UnitLatencies = ForceUnitLatencies(); + + // Ask the target if address-backscheduling is desirable, and if so how much. + unsigned SpecialAddressLatency = + TM.getSubtarget().getSpecialAddressLatency(); - for (MachineBasicBlock::iterator MII = BB->end(), MIE = BB->begin(); + // Walk the list of instructions, from bottom moving up. + for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; MII != MIE; --MII) { MachineInstr *MI = prior(MII); + const TargetInstrDesc &TID = MI->getDesc(); + assert(!TID.isTerminator() && !MI->isLabel() && + "Cannot schedule terminators or labels!"); + // Create the SUnit for this MI. SUnit *SU = NewSUnit(MI); // Assign the Latency field of SU using target-provided information. - ComputeLatency(SU); + if (UnitLatencies) + SU->Latency = 1; + else + ComputeLatency(SU); // Add register-based dependencies (data, anti, and output). for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) { @@ -74,33 +183,109 @@ void ScheduleDAGInstrs::BuildSchedUnits() { assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!"); std::vector &UseList = Uses[Reg]; - SUnit *&Def = Defs[Reg]; + std::vector &DefList = Defs[Reg]; // Optionally add output and anti dependencies. // TODO: Using a latency of 1 here assumes there's no cost for // reusing registers. SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; - if (Def && Def != SU) - Def->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/Reg)); + for (unsigned i = 0, e = DefList.size(); i != e; ++i) { + SUnit *DefSU = DefList[i]; + if (DefSU != SU && + (Kind != SDep::Output || !MO.isDead() || + !DefSU->getInstr()->registerDefIsDead(Reg))) + DefSU->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/Reg)); + } for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - SUnit *&Def = Defs[*Alias]; - if (Def && Def != SU) - Def->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/ *Alias)); + std::vector &DefList = Defs[*Alias]; + for (unsigned i = 0, e = DefList.size(); i != e; ++i) { + SUnit *DefSU = DefList[i]; + if (DefSU != SU && + (Kind != SDep::Output || !MO.isDead() || + !DefSU->getInstr()->registerDefIsDead(Reg))) + DefSU->addPred(SDep(SU, Kind, /*Latency=*/1, /*Reg=*/ *Alias)); + } } if (MO.isDef()) { // Add any data dependencies. - for (unsigned i = 0, e = UseList.size(); i != e; ++i) - if (UseList[i] != SU) - UseList[i]->addPred(SDep(SU, SDep::Data, SU->Latency, Reg)); + unsigned DataLatency = SU->Latency; + for (unsigned i = 0, e = UseList.size(); i != e; ++i) { + SUnit *UseSU = UseList[i]; + if (UseSU != SU) { + unsigned LDataLatency = DataLatency; + // Optionally add in a special extra latency for nodes that + // feed addresses. + // TODO: Do this for register aliases too. + if (SpecialAddressLatency != 0 && !UnitLatencies) { + MachineInstr *UseMI = UseSU->getInstr(); + const TargetInstrDesc &UseTID = UseMI->getDesc(); + int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg); + assert(RegUseIndex >= 0 && "UseMI doesn's use register!"); + if ((UseTID.mayLoad() || UseTID.mayStore()) && + (unsigned)RegUseIndex < UseTID.getNumOperands() && + UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass()) + LDataLatency += SpecialAddressLatency; + } + UseSU->addPred(SDep(SU, SDep::Data, LDataLatency, Reg)); + } + } for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { std::vector &UseList = Uses[*Alias]; - for (unsigned i = 0, e = UseList.size(); i != e; ++i) - if (UseList[i] != SU) - UseList[i]->addPred(SDep(SU, SDep::Data, SU->Latency, *Alias)); + for (unsigned i = 0, e = UseList.size(); i != e; ++i) { + SUnit *UseSU = UseList[i]; + if (UseSU != SU) + UseSU->addPred(SDep(SU, SDep::Data, DataLatency, *Alias)); + } + } + + // If a def is going to wrap back around to the top of the loop, + // backschedule it. + if (!UnitLatencies && DefList.empty()) { + LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg); + if (I != LoopRegs.Deps.end()) { + const MachineOperand *UseMO = I->second.first; + unsigned Count = I->second.second; + const MachineInstr *UseMI = UseMO->getParent(); + unsigned UseMOIdx = UseMO - &UseMI->getOperand(0); + const TargetInstrDesc &UseTID = UseMI->getDesc(); + // TODO: If we knew the total depth of the region here, we could + // handle the case where the whole loop is inside the region but + // is large enough that the isScheduleHigh trick isn't needed. + if (UseMOIdx < UseTID.getNumOperands()) { + // Currently, we only support scheduling regions consisting of + // single basic blocks. Check to see if the instruction is in + // the same region by checking to see if it has the same parent. + if (UseMI->getParent() != MI->getParent()) { + unsigned Latency = SU->Latency; + if (UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) + Latency += SpecialAddressLatency; + // This is a wild guess as to the portion of the latency which + // will be overlapped by work done outside the current + // scheduling region. + Latency -= std::min(Latency, Count); + // Add the artifical edge. + ExitSU.addPred(SDep(SU, SDep::Order, Latency, + /*Reg=*/0, /*isNormalMemory=*/false, + /*isMustAlias=*/false, + /*isArtificial=*/true)); + } else if (SpecialAddressLatency > 0 && + UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) { + // The entire loop body is within the current scheduling region + // and the latency of this operation is assumed to be greater + // than the latency of the loop. + // TODO: Recursively mark data-edge predecessors as + // isScheduleHigh too. + SU->isScheduleHigh = true; + } + } + LoopRegs.Deps.erase(I); + } } UseList.clear(); - Def = SU; + if (!MO.isDead()) + DefList.clear(); + DefList.push_back(SU); } else { UseList.push_back(SU); } @@ -111,9 +296,7 @@ void ScheduleDAGInstrs::BuildSchedUnits() { // after stack slots are lowered to actual addresses. // TODO: Use an AliasAnalysis and do real alias-analysis queries, and // produce more precise dependence information. - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.isCall() || TID.isReturn() || TID.isBranch() || - TID.hasUnmodeledSideEffects()) { + if (TID.isCall() || TID.hasUnmodeledSideEffects()) { new_chain: // This is the conservative case. Add dependencies on all memory // references. @@ -137,7 +320,7 @@ void ScheduleDAGInstrs::BuildSchedUnits() { // See if it is known to just have a single memory reference. MachineInstr *ChainMI = Chain->getInstr(); const TargetInstrDesc &ChainTID = ChainMI->getDesc(); - if (!ChainTID.isCall() && !ChainTID.isReturn() && !ChainTID.isBranch() && + if (!ChainTID.isCall() && !ChainTID.hasUnmodeledSideEffects() && ChainMI->hasOneMemOperand() && !ChainMI->memoperands_begin()->isVolatile() && @@ -148,12 +331,8 @@ void ScheduleDAGInstrs::BuildSchedUnits() { // Unknown memory accesses. Assume the worst. ChainMMO = 0; } else if (TID.mayStore()) { - if (MI->hasOneMemOperand() && - MI->memoperands_begin()->getValue() && - !MI->memoperands_begin()->isVolatile() && - isa(MI->memoperands_begin()->getValue())) { + if (const Value *V = getUnderlyingObjectForInstr(MI)) { // A store to a specific PseudoSourceValue. Add precise dependencies. - const Value *V = MI->memoperands_begin()->getValue(); // Handle the def in MemDefs, if there is one. std::map::iterator I = MemDefs.find(V); if (I != MemDefs.end()) { @@ -172,6 +351,10 @@ void ScheduleDAGInstrs::BuildSchedUnits() { /*isNormalMemory=*/true)); J->second.clear(); } + // Add dependencies from all the PendingLoads, since without + // memoperands we must assume they alias anything. + for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) + PendingLoads[k]->addPred(SDep(SU, SDep::Order, SU->Latency)); // Add a general dependence too, if needed. if (Chain) Chain->addPred(SDep(SU, SDep::Order, SU->Latency)); @@ -181,12 +364,8 @@ void ScheduleDAGInstrs::BuildSchedUnits() { } else if (TID.mayLoad()) { if (TII->isInvariantLoad(MI)) { // Invariant load, no chain dependencies needed! - } else if (MI->hasOneMemOperand() && - MI->memoperands_begin()->getValue() && - !MI->memoperands_begin()->isVolatile() && - isa(MI->memoperands_begin()->getValue())) { + } else if (const Value *V = getUnderlyingObjectForInstr(MI)) { // A load from a specific PseudoSourceValue. Add precise dependencies. - const Value *V = MI->memoperands_begin()->getValue(); std::map::iterator I = MemDefs.find(V); if (I != MemDefs.end()) I->second->addPred(SDep(SU, SDep::Order, SU->Latency, /*Reg=*/0, @@ -202,20 +381,29 @@ void ScheduleDAGInstrs::BuildSchedUnits() { // cases where memoperand information is unavailable. goto new_chain; } else { - // A normal load. Just depend on the general chain. + // A normal load. Depend on the general chain, as well as on + // all stores. In the absense of MachineMemOperand information, + // we can't even assume that the load doesn't alias well-behaved + // memory locations. if (Chain) Chain->addPred(SDep(SU, SDep::Order, SU->Latency)); + for (std::map::iterator I = MemDefs.begin(), + E = MemDefs.end(); I != E; ++I) + I->second->addPred(SDep(SU, SDep::Order, SU->Latency)); PendingLoads.push_back(SU); } } + } - // Add chain edges from the terminator to ensure that all the work of the - // block is completed before any control transfers. - if (Terminator && SU->Succs.empty()) - Terminator->addPred(SDep(SU, SDep::Order, SU->Latency)); - if (TID.isTerminator() || MI->isLabel()) - Terminator = SU; + for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) { + Defs[i].clear(); + Uses[i].clear(); } + PendingLoads.clear(); +} + +void ScheduleDAGInstrs::FinishBlock() { + // Nothing to do. } void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) { @@ -240,7 +428,12 @@ void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { std::string s; raw_string_ostream oss(s); - SU->getInstr()->print(oss); + if (SU == &EntrySU) + oss << ""; + else if (SU == &ExitSU) + oss << ""; + else + SU->getInstr()->print(oss); return oss.str(); } @@ -248,9 +441,13 @@ std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() { // For MachineInstr-based scheduling, we're rescheduling the instructions in // the block, so start by removing them from the block. - while (!BB->empty()) - BB->remove(BB->begin()); + while (Begin != InsertPos) { + MachineBasicBlock::iterator I = Begin; + ++Begin; + BB->remove(I); + } + // Then re-insert them according to the given schedule. for (unsigned i = 0, e = Sequence.size(); i != e; i++) { SUnit *SU = Sequence[i]; if (!SU) { @@ -259,8 +456,13 @@ MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() { continue; } - BB->push_back(SU->getInstr()); + BB->insert(InsertPos, SU->getInstr()); } + // Update the Begin iterator, as the first instruction in the block + // may have been scheduled later. + if (!Sequence.empty()) + Begin = Sequence[0]->getInstr(); + return BB; }