X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FDAGCombiner.cpp;h=0622c552d5a218fc726bf6f1dd9943dadb583fee;hb=ee4c619b3b28a42078fc8033e5dccd42fc6edd42;hp=747a0b1e546b91a3abfc2cc639f0e0f09f43a105;hpb=475871a144eb604ddaf37503397ba0941442e5fb;p=oota-llvm.git

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 747a0b1e546..0622c552d5a 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -51,6 +51,7 @@ namespace {
     SelectionDAG &DAG;
     TargetLowering &TLI;
     bool AfterLegalize;
+    bool Fast;
 
     // Worklist of all of the nodes that need to be simplified.
     std::vector<SDNode*> WorkList;
@@ -124,9 +125,9 @@ namespace {
     // Visitation implementation - Implement dag node combining for different
     // node types.  The semantics are as follows:
     // Return Value:
-    //   SDValue.Val == 0   - No change was made
-    //   SDValue.Val == N   - N was replaced, is dead, and is already handled.
-    //   otherwise            - N should be replaced by the returned Operand.
+    //   SDValue.getNode() == 0 - No change was made
+    //   SDValue.getNode() == N - N was replaced, is dead and has been handled.
+    //   otherwise              - N should be replaced by the returned Operand.
     //
     SDValue visitTokenFactor(SDNode *N);
     SDValue visitMERGE_VALUES(SDNode *N);
@@ -237,10 +238,11 @@ namespace {
     SDValue FindBetterChain(SDNode *N, SDValue Chain);
     
 public:
-    DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
+    DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
       : DAG(D),
         TLI(D.getTargetLoweringInfo()),
         AfterLegalize(false),
+        Fast(fast),
         AA(A) {}
     
     /// Run - runs the dag combiner on all nodes in the work list
@@ -462,7 +464,7 @@ static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
 // free when it is profitable to do so.
 static bool isOneUseSetCC(SDValue N) {
   SDValue N0, N1, N2;
-  if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
+  if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
     return true;
   return false;
 }
@@ -474,11 +476,11 @@ SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){
   if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
     if (isa<ConstantSDNode>(N1)) {
       SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
-      AddToWorkList(OpNode.Val);
+      AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
     } else if (N0.hasOneUse()) {
       SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
-      AddToWorkList(OpNode.Val);
+      AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
     }
   }
@@ -487,11 +489,11 @@ SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){
   if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
     if (isa<ConstantSDNode>(N0)) {
       SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
-      AddToWorkList(OpNode.Val);
+      AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
     } else if (N1.hasOneUse()) {
       SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
-      AddToWorkList(OpNode.Val);
+      AddToWorkList(OpNode.getNode());
       return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
     }
   }
@@ -503,7 +505,7 @@ SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
   assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
   ++NodesCombined;
   DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
-  DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
   DOUT << " and " << NumTo-1 << " other values\n";
   WorkListRemover DeadNodes(*this);
   DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
@@ -511,8 +513,8 @@ SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
   if (AddTo) {
     // Push the new nodes and any users onto the worklist
     for (unsigned i = 0, e = NumTo; i != e; ++i) {
-      AddToWorkList(To[i].Val);
-      AddUsersToWorkList(To[i].Val);
+      AddToWorkList(To[i].getNode());
+      AddUsersToWorkList(To[i].getNode());
     }
   }
   
@@ -535,12 +537,12 @@ bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
     return false;
   
   // Revisit the node.
-  AddToWorkList(Op.Val);
+  AddToWorkList(Op.getNode());
   
   // Replace the old value with the new one.
   ++NodesCombined;
-  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
-  DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
+  DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
   DOUT << '\n';
   
   // Replace all uses.  If any nodes become isomorphic to other nodes and 
@@ -549,22 +551,22 @@ bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
   DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
   
   // Push the new node and any (possibly new) users onto the worklist.
-  AddToWorkList(TLO.New.Val);
-  AddUsersToWorkList(TLO.New.Val);
+  AddToWorkList(TLO.New.getNode());
+  AddUsersToWorkList(TLO.New.getNode());
   
   // Finally, if the node is now dead, remove it from the graph.  The node
   // may not be dead if the replacement process recursively simplified to
   // something else needing this node.
-  if (TLO.Old.Val->use_empty()) {
-    removeFromWorkList(TLO.Old.Val);
+  if (TLO.Old.getNode()->use_empty()) {
+    removeFromWorkList(TLO.Old.getNode());
     
     // If the operands of this node are only used by the node, they will now
     // be dead.  Make sure to visit them first to delete dead nodes early.
-    for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
-      if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
-        AddToWorkList(TLO.Old.Val->getOperand(i).Val);
+    for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
+      if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
+        AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
     
-    DAG.DeleteNode(TLO.Old.Val);
+    DAG.DeleteNode(TLO.Old.getNode());
   }
   return true;
 }
@@ -603,7 +605,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
     // reduced number of uses, allowing other xforms.
     if (N->use_empty() && N != &Dummy) {
       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-        AddToWorkList(N->getOperand(i).Val);
+        AddToWorkList(N->getOperand(i).getNode());
       
       DAG.DeleteNode(N);
       continue;
@@ -611,7 +613,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
     
     SDValue RV = combine(N);
     
-    if (RV.Val == 0)
+    if (RV.getNode() == 0)
       continue;
     
     ++NodesCombined;
@@ -620,19 +622,19 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
     // zero, we know that the node must have defined multiple values and
     // CombineTo was used.  Since CombineTo takes care of the worklist 
     // mechanics for us, we have no work to do in this case.
-    if (RV.Val == N)
+    if (RV.getNode() == N)
       continue;
     
     assert(N->getOpcode() != ISD::DELETED_NODE &&
-           RV.Val->getOpcode() != ISD::DELETED_NODE &&
+           RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
            "Node was deleted but visit returned new node!");
 
     DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
-    DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
+    DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
     DOUT << '\n';
     WorkListRemover DeadNodes(*this);
-    if (N->getNumValues() == RV.Val->getNumValues())
-      DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes);
+    if (N->getNumValues() == RV.getNode()->getNumValues())
+      DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
     else {
       assert(N->getValueType(0) == RV.getValueType() &&
              N->getNumValues() == 1 && "Type mismatch");
@@ -641,14 +643,14 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
     }
       
     // Push the new node and any users onto the worklist
-    AddToWorkList(RV.Val);
-    AddUsersToWorkList(RV.Val);
+    AddToWorkList(RV.getNode());
+    AddUsersToWorkList(RV.getNode());
     
     // Add any uses of the old node to the worklist in case this node is the
     // last one that uses them.  They may become dead after this node is
     // deleted.
     for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-      AddToWorkList(N->getOperand(i).Val);
+      AddToWorkList(N->getOperand(i).getNode());
       
     // Nodes can be reintroduced into the worklist.  Make sure we do not
     // process a node that has been replaced.
@@ -734,7 +736,7 @@ SDValue DAGCombiner::combine(SDNode *N) {
   SDValue RV = visit(N);
 
   // If nothing happened, try a target-specific DAG combine.
-  if (RV.Val == 0) {
+  if (RV.getNode() == 0) {
     assert(N->getOpcode() != ISD::DELETED_NODE &&
            "Node was deleted but visit returned NULL!");
 
@@ -751,7 +753,7 @@ SDValue DAGCombiner::combine(SDNode *N) {
 
   // If N is a commutative binary node, try commuting it to enable more 
   // sdisel CSE.
-  if (RV.Val == 0 && 
+  if (RV.getNode() == 0 && 
       SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
       N->getNumValues() == 1) {
     SDValue N0 = N->getOperand(0);
@@ -788,9 +790,9 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
   // If N has two operands, where one has an input chain equal to the other,
   // the 'other' chain is redundant.
   if (N->getNumOperands() == 2) {
-    if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
+    if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
       return N->getOperand(0);
-    if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
+    if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
       return N->getOperand(1);
   }
   
@@ -820,11 +822,11 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
         
       case ISD::TokenFactor:
         if ((CombinerAA || Op.hasOneUse()) &&
-            std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
+            std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
           // Queue up for processing.
-          TFs.push_back(Op.Val);
+          TFs.push_back(Op.getNode());
           // Clean up in case the token factor is removed.
-          AddToWorkList(Op.Val);
+          AddToWorkList(Op.getNode());
           Changed = true;
           break;
         }
@@ -832,7 +834,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
         
       default:
         // Only add if it isn't already in the list.
-        if (SeenOps.insert(Op.Val))
+        if (SeenOps.insert(Op.getNode()))
           Ops.push_back(Op);
         else
           Changed = true;
@@ -878,7 +880,7 @@ SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) {
   SDValue N00 = N0.getOperand(0);
   SDValue N01 = N0.getOperand(1);
   ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
-  if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
+  if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
       isa<ConstantSDNode>(N00.getOperand(1))) {
     N0 = DAG.getNode(ISD::ADD, VT,
                      DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
@@ -948,7 +950,7 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (add x, undef) -> undef
@@ -958,13 +960,20 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
     return N1;
   // fold (add c1, c2) -> c1+c2
   if (N0C && N1C)
-    return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT);
+    return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::ADD, VT, N1, N0);
   // fold (add x, 0) -> x
   if (N1C && N1C->isNullValue())
     return N0;
+  // fold (add Sym, c) -> Sym+c
+  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
+    if (!AfterLegalize && TLI.isOffsetFoldingLegal(GA) && N1C &&
+        GA->getOpcode() == ISD::GlobalAddress)
+      return DAG.getGlobalAddress(GA->getGlobal(), VT,
+                                  GA->getOffset() +
+                                    (uint64_t)N1C->getSExtValue());
   // fold ((c1-A)+c2) -> (c1+c2)-A
   if (N1C && N0.getOpcode() == ISD::SUB)
     if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
@@ -974,7 +983,7 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
                          N0.getOperand(1));
   // reassociate add
   SDValue RADD = ReassociateOps(ISD::ADD, N0, N1);
-  if (RADD.Val != 0)
+  if (RADD.getNode() != 0)
     return RADD;
   // fold ((0-A) + B) -> B-A
   if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
@@ -1009,23 +1018,23 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
   }
 
   // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
-  if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
+  if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
     SDValue Result = combineShlAddConstant(N0, N1, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
-  if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
+  if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
     SDValue Result = combineShlAddConstant(N1, N0, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
 
   // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
-  if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
+  if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
     SDValue Result = combineSelectAndUse(N, N0, N1, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
-  if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
+  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
     SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
 
   return SDValue();
@@ -1094,14 +1103,14 @@ SDValue DAGCombiner::visitADDE(SDNode *N) {
 SDValue DAGCombiner::visitSUB(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
   MVT VT = N0.getValueType();
   
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (sub x, x) -> 0
@@ -1109,7 +1118,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
     return DAG.getConstant(0, N->getValueType(0));
   // fold (sub c1, c2) -> c1-c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::SUB, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
   // fold (sub x, c) -> (add x, -c)
   if (N1C)
     return DAG.getNode(ISD::ADD, VT, N0,
@@ -1121,9 +1130,9 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
   if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
     return N0.getOperand(0);
   // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
-  if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
+  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
     SDValue Result = combineSelectAndUse(N, N1, N0, DAG);
-    if (Result.Val) return Result;
+    if (Result.getNode()) return Result;
   }
   // If either operand of a sub is undef, the result is undef
   if (N0.getOpcode() == ISD::UNDEF)
@@ -1131,6 +1140,21 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
   if (N1.getOpcode() == ISD::UNDEF)
     return N1;
 
+  // If the relocation model supports it, consider symbol offsets.
+  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
+    if (!AfterLegalize && TLI.isOffsetFoldingLegal(GA)) {
+      // fold (sub Sym, c) -> Sym-c
+      if (N1C && GA->getOpcode() == ISD::GlobalAddress)
+        return DAG.getGlobalAddress(GA->getGlobal(), VT,
+                                    GA->getOffset() -
+                                      (uint64_t)N1C->getSExtValue());
+      // fold (sub Sym+c1, Sym+c2) -> c1-c2
+      if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
+        if (GA->getGlobal() == GB->getGlobal())
+          return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
+                                 VT);
+    }
+
   return SDValue();
 }
 
@@ -1144,7 +1168,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (mul x, undef) -> 0
@@ -1152,7 +1176,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
     return DAG.getConstant(0, VT);
   // fold (mul c1, c2) -> c1*c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::MUL, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::MUL, VT, N1, N0);
@@ -1168,12 +1192,12 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
                        DAG.getConstant(N1C->getAPIntValue().logBase2(),
                                        TLI.getShiftAmountTy()));
   // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
-  if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
+  if (N1C && isPowerOf2_64(-N1C->getSExtValue())) {
     // FIXME: If the input is something that is easily negated (e.g. a 
     // single-use add), we should put the negate there.
     return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
                        DAG.getNode(ISD::SHL, VT, N0,
-                            DAG.getConstant(Log2_64(-N1C->getSignExtended()),
+                            DAG.getConstant(Log2_64(-N1C->getSExtValue()),
                                             TLI.getShiftAmountTy())));
   }
 
@@ -1181,7 +1205,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
   if (N1C && N0.getOpcode() == ISD::SHL && 
       isa<ConstantSDNode>(N0.getOperand(1))) {
     SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
-    AddToWorkList(C3.Val);
+    AddToWorkList(C3.getNode());
     return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
   }
   
@@ -1191,19 +1215,20 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
     SDValue Sh(0,0), Y(0,0);
     // Check for both (mul (shl X, C), Y)  and  (mul Y, (shl X, C)).
     if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
-        N0.Val->hasOneUse()) {
+        N0.getNode()->hasOneUse()) {
       Sh = N0; Y = N1;
     } else if (N1.getOpcode() == ISD::SHL && 
-               isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
+               isa<ConstantSDNode>(N1.getOperand(1)) &&
+               N1.getNode()->hasOneUse()) {
       Sh = N1; Y = N0;
     }
-    if (Sh.Val) {
+    if (Sh.getNode()) {
       SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
       return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
     }
   }
   // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
-  if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 
+  if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 
       isa<ConstantSDNode>(N0.getOperand(1))) {
     return DAG.getNode(ISD::ADD, VT, 
                        DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
@@ -1212,7 +1237,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
   
   // reassociate mul
   SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1);
-  if (RMUL.Val != 0)
+  if (RMUL.getNode() != 0)
     return RMUL;
 
   return SDValue();
@@ -1221,21 +1246,21 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
 SDValue DAGCombiner::visitSDIV(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
   MVT VT = N->getValueType(0);
 
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (sdiv c1, c2) -> c1/c2
   if (N0C && N1C && !N1C->isNullValue())
-    return DAG.getNode(ISD::SDIV, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
   // fold (sdiv X, 1) -> X
-  if (N1C && N1C->getSignExtended() == 1LL)
+  if (N1C && N1C->getSExtValue() == 1LL)
     return N0;
   // fold (sdiv X, -1) -> 0-X
   if (N1C && N1C->isAllOnesValue())
@@ -1248,42 +1273,42 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
   }
   // fold (sdiv X, pow2) -> simple ops after legalize
   if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
-      (isPowerOf2_64(N1C->getSignExtended()) || 
-       isPowerOf2_64(-N1C->getSignExtended()))) {
+      (isPowerOf2_64(N1C->getSExtValue()) || 
+       isPowerOf2_64(-N1C->getSExtValue()))) {
     // If dividing by powers of two is cheap, then don't perform the following
     // fold.
     if (TLI.isPow2DivCheap())
       return SDValue();
-    int64_t pow2 = N1C->getSignExtended();
+    int64_t pow2 = N1C->getSExtValue();
     int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
     unsigned lg2 = Log2_64(abs2);
     // Splat the sign bit into the register
     SDValue SGN = DAG.getNode(ISD::SRA, VT, N0,
                                 DAG.getConstant(VT.getSizeInBits()-1,
                                                 TLI.getShiftAmountTy()));
-    AddToWorkList(SGN.Val);
+    AddToWorkList(SGN.getNode());
     // Add (N0 < 0) ? abs2 - 1 : 0;
     SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN,
                                 DAG.getConstant(VT.getSizeInBits()-lg2,
                                                 TLI.getShiftAmountTy()));
     SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
-    AddToWorkList(SRL.Val);
-    AddToWorkList(ADD.Val);    // Divide by pow2
+    AddToWorkList(SRL.getNode());
+    AddToWorkList(ADD.getNode());    // Divide by pow2
     SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD,
                                 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
     // If we're dividing by a positive value, we're done.  Otherwise, we must
     // negate the result.
     if (pow2 > 0)
       return SRA;
-    AddToWorkList(SRA.Val);
+    AddToWorkList(SRA.getNode());
     return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
   }
   // if integer divide is expensive and we satisfy the requirements, emit an
   // alternate sequence.
-  if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 
+  if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 
       !TLI.isIntDivCheap()) {
     SDValue Op = BuildSDIV(N);
-    if (Op.Val) return Op;
+    if (Op.getNode()) return Op;
   }
 
   // undef / X -> 0
@@ -1299,19 +1324,19 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
 SDValue DAGCombiner::visitUDIV(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
+  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
   MVT VT = N->getValueType(0);
   
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (udiv c1, c2) -> c1/c2
   if (N0C && N1C && !N1C->isNullValue())
-    return DAG.getNode(ISD::UDIV, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
   // fold (udiv x, (1 << c)) -> x >>u c
   if (N1C && N1C->getAPIntValue().isPowerOf2())
     return DAG.getNode(ISD::SRL, VT, N0, 
@@ -1326,7 +1351,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) {
                                     DAG.getConstant(SHC->getAPIntValue()
                                                                     .logBase2(),
                                                     ADDVT));
-        AddToWorkList(Add.Val);
+        AddToWorkList(Add.getNode());
         return DAG.getNode(ISD::SRL, VT, N0, Add);
       }
     }
@@ -1334,7 +1359,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) {
   // fold (udiv x, c) -> alternate
   if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
     SDValue Op = BuildUDIV(N);
-    if (Op.Val) return Op;
+    if (Op.getNode()) return Op;
   }
 
   // undef / X -> 0
@@ -1356,7 +1381,7 @@ SDValue DAGCombiner::visitSREM(SDNode *N) {
   
   // fold (srem c1, c2) -> c1%c2
   if (N0C && N1C && !N1C->isNullValue())
-    return DAG.getNode(ISD::SREM, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
   // If we know the sign bits of both operands are zero, strength reduce to a
   // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
   if (!VT.isVector()) {
@@ -1368,12 +1393,12 @@ SDValue DAGCombiner::visitSREM(SDNode *N) {
   // X%C to the equivalent of X-X/C*C.
   if (N1C && !N1C->isNullValue()) {
     SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
-    AddToWorkList(Div.Val);
-    SDValue OptimizedDiv = combine(Div.Val);
-    if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
+    AddToWorkList(Div.getNode());
+    SDValue OptimizedDiv = combine(Div.getNode());
+    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
       SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
       SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
-      AddToWorkList(Mul.Val);
+      AddToWorkList(Mul.getNode());
       return Sub;
     }
   }
@@ -1397,7 +1422,7 @@ SDValue DAGCombiner::visitUREM(SDNode *N) {
   
   // fold (urem c1, c2) -> c1%c2
   if (N0C && N1C && !N1C->isNullValue())
-    return DAG.getNode(ISD::UREM, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
   // fold (urem x, pow2) -> (and x, pow2-1)
   if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
     return DAG.getNode(ISD::AND, VT, N0,
@@ -1410,7 +1435,7 @@ SDValue DAGCombiner::visitUREM(SDNode *N) {
           DAG.getNode(ISD::ADD, VT, N1,
                  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
                                  VT));
-        AddToWorkList(Add.Val);
+        AddToWorkList(Add.getNode());
         return DAG.getNode(ISD::AND, VT, N0, Add);
       }
     }
@@ -1420,11 +1445,12 @@ SDValue DAGCombiner::visitUREM(SDNode *N) {
   // X%C to the equivalent of X-X/C*C.
   if (N1C && !N1C->isNullValue()) {
     SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
-    SDValue OptimizedDiv = combine(Div.Val);
-    if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) {
+    AddToWorkList(Div.getNode());
+    SDValue OptimizedDiv = combine(Div.getNode());
+    if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
       SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1);
       SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
-      AddToWorkList(Mul.Val);
+      AddToWorkList(Mul.getNode());
       return Sub;
     }
   }
@@ -1513,9 +1539,9 @@ SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
   if (LoExists) {
     SDValue Lo = DAG.getNode(LoOp, N->getValueType(0),
                                N->op_begin(), N->getNumOperands());
-    AddToWorkList(Lo.Val);
-    SDValue LoOpt = combine(Lo.Val);
-    if (LoOpt.Val && LoOpt.Val != Lo.Val &&
+    AddToWorkList(Lo.getNode());
+    SDValue LoOpt = combine(Lo.getNode());
+    if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
         (!AfterLegalize ||
          TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
       return CombineTo(N, LoOpt, LoOpt);
@@ -1524,9 +1550,9 @@ SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
   if (HiExists) {
     SDValue Hi = DAG.getNode(HiOp, N->getValueType(1),
                                N->op_begin(), N->getNumOperands());
-    AddToWorkList(Hi.Val);
-    SDValue HiOpt = combine(Hi.Val);
-    if (HiOpt.Val && HiOpt != Hi &&
+    AddToWorkList(Hi.getNode());
+    SDValue HiOpt = combine(Hi.getNode());
+    if (HiOpt.getNode() && HiOpt != Hi &&
         (!AfterLegalize ||
          TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
       return CombineTo(N, HiOpt, HiOpt);
@@ -1536,28 +1562,28 @@ SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
 
 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
-  if (Res.Val) return Res;
+  if (Res.getNode()) return Res;
 
   return SDValue();
 }
 
 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
-  if (Res.Val) return Res;
+  if (Res.getNode()) return Res;
 
   return SDValue();
 }
 
 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
-  if (Res.Val) return Res;
+  if (Res.getNode()) return Res;
   
   return SDValue();
 }
 
 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
   SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
-  if (Res.Val) return Res;
+  if (Res.getNode()) return Res;
   
   return SDValue();
 }
@@ -1580,7 +1606,7 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
     SDValue ORNode = DAG.getNode(N->getOpcode(), 
                                    N0.getOperand(0).getValueType(),
                                    N0.getOperand(0), N1.getOperand(0));
-    AddToWorkList(ORNode.Val);
+    AddToWorkList(ORNode.getNode());
     return DAG.getNode(N0.getOpcode(), VT, ORNode);
   }
   
@@ -1594,7 +1620,7 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
     SDValue ORNode = DAG.getNode(N->getOpcode(),
                                    N0.getOperand(0).getValueType(),
                                    N0.getOperand(0), N1.getOperand(0));
-    AddToWorkList(ORNode.Val);
+    AddToWorkList(ORNode.getNode());
     return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
   }
   
@@ -1613,7 +1639,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (and x, undef) -> 0
@@ -1621,7 +1647,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
     return DAG.getConstant(0, VT);
   // fold (and c1, c2) -> c1&c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::AND, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::AND, VT, N1, N0);
@@ -1634,7 +1660,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
     return DAG.getConstant(0, VT);
   // reassociate and
   SDValue RAND = ReassociateOps(ISD::AND, N0, N1);
-  if (RAND.Val != 0)
+  if (RAND.getNode() != 0)
     return RAND;
   // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
   if (N1C && N0.getOpcode() == ISD::OR)
@@ -1656,7 +1682,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
       // We actually want to replace all uses of the any_extend with the
       // zero_extend, to avoid duplicating things.  This will later cause this
       // AND to be folded.
-      CombineTo(N0.Val, Zext);
+      CombineTo(N0.getNode(), Zext);
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
   }
@@ -1670,19 +1696,19 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
       // fold (X == 0) & (Y == 0) -> (X|Y == 0)
       if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
-        AddToWorkList(ORNode.Val);
+        AddToWorkList(ORNode.getNode());
         return DAG.getSetCC(VT, ORNode, LR, Op1);
       }
       // fold (X == -1) & (Y == -1) -> (X&Y == -1)
       if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
         SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
-        AddToWorkList(ANDNode.Val);
+        AddToWorkList(ANDNode.getNode());
         return DAG.getSetCC(VT, ANDNode, LR, Op1);
       }
       // fold (X >  -1) & (Y >  -1) -> (X|Y > -1)
       if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
-        AddToWorkList(ORNode.Val);
+        AddToWorkList(ORNode.getNode());
         return DAG.getSetCC(VT, ORNode, LR, Op1);
       }
     }
@@ -1702,7 +1728,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
   // Simplify: and (op x...), (op y...)  -> (op (and x, y))
   if (N0.getOpcode() == N1.getOpcode()) {
     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
-    if (Tmp.Val) return Tmp;
+    if (Tmp.getNode()) return Tmp;
   }
   
   // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
@@ -1711,7 +1737,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
       SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
   // fold (zext_inreg (extload x)) -> (zextload x)
-  if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
+  if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
     // If we zero all the possible extended bits, then we can turn this into
@@ -1720,19 +1746,19 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
     if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
                                      BitWidth - EVT.getSizeInBits())) &&
         ((!AfterLegalize && !LN0->isVolatile()) ||
-         TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
+         TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
                                          LN0->getBasePtr(), LN0->getSrcValue(),
                                          LN0->getSrcValueOffset(), EVT,
                                          LN0->isVolatile(), 
                                          LN0->getAlignment());
       AddToWorkList(N);
-      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
   }
   // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
-  if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+  if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
       N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
@@ -1742,14 +1768,14 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
     if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
                                      BitWidth - EVT.getSizeInBits())) &&
         ((!AfterLegalize && !LN0->isVolatile()) ||
-         TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
+         TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
                                          LN0->getBasePtr(), LN0->getSrcValue(),
                                          LN0->getSrcValueOffset(), EVT,
                                          LN0->isVolatile(), 
                                          LN0->getAlignment());
       AddToWorkList(N);
-      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+      CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
   }
@@ -1771,7 +1797,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
       // Do not generate loads of non-round integer types since these can
       // be expensive (and would be wrong if the type is not byte sized).
       if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
-          (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
+          (!AfterLegalize || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
         MVT PtrType = N0.getOperand(1).getValueType();
         // For big endian targets, we need to add an offset to the pointer to
         // load the correct bytes.  For little endian systems, we merely need to
@@ -1786,13 +1812,13 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
                                DAG.getConstant(PtrOff, PtrType));
           Alignment = MinAlign(Alignment, PtrOff);
         }
-        AddToWorkList(NewPtr.Val);
+        AddToWorkList(NewPtr.getNode());
         SDValue Load =
           DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
                          LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
                          LN0->isVolatile(), Alignment);
         AddToWorkList(N);
-        CombineTo(N0.Val, Load, Load.getValue(1));
+        CombineTo(N0.getNode(), Load, Load.getValue(1));
         return SDValue(N, 0);   // Return N so it doesn't get rechecked!
       }
     }
@@ -1812,7 +1838,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (or x, undef) -> -1
@@ -1820,7 +1846,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
     return DAG.getConstant(~0ULL, VT);
   // fold (or c1, c2) -> c1|c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::OR, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::OR, VT, N1, N0);
@@ -1835,10 +1861,10 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
     return N1;
   // reassociate or
   SDValue ROR = ReassociateOps(ISD::OR, N0, N1);
-  if (ROR.Val != 0)
+  if (ROR.getNode() != 0)
     return ROR;
   // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
-  if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
+  if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
              isa<ConstantSDNode>(N0.getOperand(1))) {
     ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
     return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
@@ -1858,7 +1884,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
       if (cast<ConstantSDNode>(LR)->isNullValue() && 
           (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
         SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
-        AddToWorkList(ORNode.Val);
+        AddToWorkList(ORNode.getNode());
         return DAG.getSetCC(VT, ORNode, LR, Op1);
       }
       // fold (X != -1) | (Y != -1) -> (X&Y != -1)
@@ -1866,7 +1892,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
       if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 
           (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
         SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
-        AddToWorkList(ANDNode.Val);
+        AddToWorkList(ANDNode.getNode());
         return DAG.getSetCC(VT, ANDNode, LR, Op1);
       }
     }
@@ -1886,7 +1912,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
   // Simplify: or (op x...), (op y...)  -> (op (or x, y))
   if (N0.getOpcode() == N1.getOpcode()) {
     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
-    if (Tmp.Val) return Tmp;
+    if (Tmp.getNode()) return Tmp;
   }
   
   // (X & C1) | (Y & C2)  -> (X|Y) & C3  if possible.
@@ -1895,7 +1921,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
       N0.getOperand(1).getOpcode() == ISD::Constant &&
       N1.getOperand(1).getOpcode() == ISD::Constant &&
       // Don't increase # computations.
-      (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
+      (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
     // We can only do this xform if we know that bits from X that are set in C2
     // but not in C1 are already zero.  Likewise for Y.
     const APInt &LHSMask =
@@ -1984,8 +2010,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
   // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
   if (LHSShiftAmt.getOpcode() == ISD::Constant &&
       RHSShiftAmt.getOpcode() == ISD::Constant) {
-    uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
-    uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
+    uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
+    uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
     if ((LShVal + RShVal) != OpSizeInBits)
       return 0;
 
@@ -1996,14 +2022,14 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
       Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
     
     // If there is an AND of either shifted operand, apply it to the result.
-    if (LHSMask.Val || RHSMask.Val) {
+    if (LHSMask.getNode() || RHSMask.getNode()) {
       APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
       
-      if (LHSMask.Val) {
+      if (LHSMask.getNode()) {
         APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
         Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
       }
-      if (RHSMask.Val) {
+      if (RHSMask.getNode()) {
         APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
         Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
       }
@@ -2011,12 +2037,12 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
       Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
     }
     
-    return Rot.Val;
+    return Rot.getNode();
   }
   
   // If there is a mask here, and we have a variable shift, we can't be sure
   // that we're masking out the right stuff.
-  if (LHSMask.Val || RHSMask.Val)
+  if (LHSMask.getNode() || RHSMask.getNode())
     return 0;
   
   // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
@@ -2027,9 +2053,9 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
           dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
       if (SUBC->getAPIntValue() == OpSizeInBits) {
         if (HasROTL)
-          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
+          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
         else
-          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
       }
     }
   }
@@ -2041,49 +2067,49 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
     if (ConstantSDNode *SUBC = 
           dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
       if (SUBC->getAPIntValue() == OpSizeInBits) {
-        if (HasROTL)
-          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
+        if (HasROTR)
+          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode();
         else
-          return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+          return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode();
       }
     }
   }
 
-  // Look for sign/zext/any-extended cases:
+  // Look for sign/zext/any-extended or truncate cases:
   if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
        || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
-       || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
+       || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
+       || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
       (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
        || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
-       || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
+       || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
+       || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
     SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
     SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
     if (RExtOp0.getOpcode() == ISD::SUB &&
         RExtOp0.getOperand(1) == LExtOp0) {
       // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
-      //   (rotr x, y)
+      //   (rotl x, y)
       // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
-      //   (rotl x, (sub 32, y))
-      if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
+      //   (rotr x, (sub 32, y))
+      if (ConstantSDNode *SUBC =
+            dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
         if (SUBC->getAPIntValue() == OpSizeInBits) {
-          if (HasROTL)
-            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
-          else
-            return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+          return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg,
+                             HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
         }
       }
     } else if (LExtOp0.getOpcode() == ISD::SUB &&
                RExtOp0 == LExtOp0.getOperand(1)) {
-      // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 
-      //   (rotl x, y)
-      // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
-      //   (rotr x, (sub 32, y))
-      if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
+      // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 
+      //   (rotr x, y)
+      // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
+      //   (rotl x, (sub 32, y))
+      if (ConstantSDNode *SUBC =
+            dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
         if (SUBC->getAPIntValue() == OpSizeInBits) {
-          if (HasROTL)
-            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
-          else
-            return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
+          return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg,
+                             HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
         }
       }
     }
@@ -2104,7 +2130,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
@@ -2117,7 +2143,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
     return N1;
   // fold (xor c1, c2) -> c1^c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::XOR, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
   // canonicalize constant to RHS
   if (N0C && !N1C)
     return DAG.getNode(ISD::XOR, VT, N1, N0);
@@ -2126,7 +2152,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
     return N0;
   // reassociate xor
   SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1);
-  if (RXOR.Val != 0)
+  if (RXOR.getNode() != 0)
     return RXOR;
   // fold !(x cc y) -> (x !cc y)
   if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
@@ -2142,11 +2168,12 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
   }
   // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
   if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
-      N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
+      N0.getNode()->hasOneUse() &&
+      isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
     SDValue V = N0.getOperand(0);
     V = DAG.getNode(ISD::XOR, V.getValueType(), V, 
                     DAG.getConstant(1, V.getValueType()));
-    AddToWorkList(V.Val);
+    AddToWorkList(V.getNode());
     return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
   }
   
@@ -2158,7 +2185,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
       LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
       RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
-      AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
+      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
       return DAG.getNode(NewOpcode, VT, LHS, RHS);
     }
   }
@@ -2170,7 +2197,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
       LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
       RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
-      AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
+      AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
       return DAG.getNode(NewOpcode, VT, LHS, RHS);
     }
   }
@@ -2202,7 +2229,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
   // Simplify: xor (op x...), (op y...)  -> (op (xor x, y))
   if (N0.getOpcode() == N1.getOpcode()) {
     SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
-    if (Tmp.Val) return Tmp;
+    if (Tmp.getNode()) return Tmp;
   }
   
   // Simplify the expression using non-local knowledge.
@@ -2216,7 +2243,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
 /// visitShiftByConstant - Handle transforms common to the three shifts, when
 /// the shift amount is a constant.
 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
-  SDNode *LHS = N->getOperand(0).Val;
+  SDNode *LHS = N->getOperand(0).getNode();
   if (!LHS->hasOneUse()) return SDValue();
   
   // We want to pull some binops through shifts, so that we have (and (shift))
@@ -2251,7 +2278,7 @@ SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
   //
   //void foo(int *X, int i) { X[i & 1235] = 1; }
   //int bar(int *X, int i) { return X[i & 255]; }
-  SDNode *BinOpLHSVal = LHS->getOperand(0).Val;
+  SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
   if ((BinOpLHSVal->getOpcode() != ISD::SHL && 
        BinOpLHSVal->getOpcode() != ISD::SRA &&
        BinOpLHSVal->getOpcode() != ISD::SRL) ||
@@ -2294,12 +2321,12 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
   
   // fold (shl c1, c2) -> c1<<c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::SHL, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
   // fold (shl 0, x) -> 0
   if (N0C && N0C->isNullValue())
     return N0;
   // fold (shl x, c >= size(x)) -> undef
-  if (N1C && N1C->getValue() >= OpSizeInBits)
+  if (N1C && N1C->getZExtValue() >= OpSizeInBits)
     return DAG.getNode(ISD::UNDEF, VT);
   // fold (shl x, 0) -> x
   if (N1C && N1C->isNullValue())
@@ -2308,13 +2335,30 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
   if (DAG.MaskedValueIsZero(SDValue(N, 0),
                             APInt::getAllOnesValue(VT.getSizeInBits())))
     return DAG.getConstant(0, VT);
+  // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c))
+  // iff (trunc c) == c
+  if (N1.getOpcode() == ISD::TRUNCATE &&
+      N1.getOperand(0).getOpcode() == ISD::AND &&
+      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
+    SDValue N101 = N1.getOperand(0).getOperand(1);
+    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
+      MVT TruncVT = N1.getValueType();
+      SDValue N100 = N1.getOperand(0).getOperand(0);
+      return DAG.getNode(ISD::SHL, VT, N0,
+                         DAG.getNode(ISD::AND, TruncVT,
+                                     DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
+                                     DAG.getConstant(N101C->getZExtValue(),
+                                                     TruncVT)));
+    }
+  }
+
   if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
   // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
   if (N1C && N0.getOpcode() == ISD::SHL && 
       N0.getOperand(1).getOpcode() == ISD::Constant) {
-    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
-    uint64_t c2 = N1C->getValue();
+    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
+    uint64_t c2 = N1C->getZExtValue();
     if (c1 + c2 > OpSizeInBits)
       return DAG.getConstant(0, VT);
     return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 
@@ -2324,8 +2368,8 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
   //                               (srl (and x, -1 << c1), c1-c2)
   if (N1C && N0.getOpcode() == ISD::SRL && 
       N0.getOperand(1).getOpcode() == ISD::Constant) {
-    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
-    uint64_t c2 = N1C->getValue();
+    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
+    uint64_t c2 = N1C->getZExtValue();
     SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
                                  DAG.getConstant(~0ULL << c1, VT));
     if (c2 > c1)
@@ -2338,9 +2382,9 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
   // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
   if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
     return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
-                       DAG.getConstant(~0ULL << N1C->getValue(), VT));
+                       DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
   
-  return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
+  return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
 }
 
 SDValue DAGCombiner::visitSRA(SDNode *N) {
@@ -2352,7 +2396,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
   
   // fold (sra c1, c2) -> c1>>c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::SRA, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
   // fold (sra 0, x) -> 0
   if (N0C && N0C->isNullValue())
     return N0;
@@ -2360,7 +2404,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
   if (N0C && N0C->isAllOnesValue())
     return N0;
   // fold (sra x, c >= size(x)) -> undef
-  if (N1C && N1C->getValue() >= VT.getSizeInBits())
+  if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
     return DAG.getNode(ISD::UNDEF, VT);
   // fold (sra x, 0) -> x
   if (N1C && N1C->isNullValue())
@@ -2368,7 +2412,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
   // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
   // sext_inreg.
   if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
-    unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue();
+    unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
     MVT EVT = MVT::getIntegerVT(LowBits);
     if (EVT.isSimple() && // TODO: remove when apint codegen support lands.
         (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
@@ -2379,7 +2423,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
   // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
   if (N1C && N0.getOpcode() == ISD::SRA) {
     if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
-      unsigned Sum = N1C->getValue() + C1->getValue();
+      unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
       if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
       return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
                          DAG.getConstant(Sum, N1C->getValueType(0)));
@@ -2398,13 +2442,13 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
       // Determine what the truncate's result bitsize and type would be.
       unsigned VTValSize = VT.getSizeInBits();
       MVT TruncVT =
-        MVT::getIntegerVT(VTValSize - N1C->getValue());
+        MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
       // Determine the residual right-shift amount.
-      unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
+      unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
 
       // If the shift is not a no-op (in which case this should be just a sign 
       // extend already), the truncated to type is legal, sign_extend is legal 
-      // on that type, and the the truncate to that type is both legal and free, 
+      // on that type, and the the truncate to that type is both legal and free,
       // perform the transform.
       if (ShiftAmt && 
           TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) &&
@@ -2419,6 +2463,23 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
     }
   }
   
+  // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c))
+  // iff (trunc c) == c
+  if (N1.getOpcode() == ISD::TRUNCATE &&
+      N1.getOperand(0).getOpcode() == ISD::AND &&
+      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
+    SDValue N101 = N1.getOperand(0).getOperand(1);
+    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
+      MVT TruncVT = N1.getValueType();
+      SDValue N100 = N1.getOperand(0).getOperand(0);
+      return DAG.getNode(ISD::SRA, VT, N0,
+                         DAG.getNode(ISD::AND, TruncVT,
+                                     DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
+                                     DAG.getConstant(N101C->getZExtValue(),
+                                                     TruncVT)));
+    }
+  }
+
   // Simplify, based on bits shifted out of the LHS. 
   if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
@@ -2428,7 +2489,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
   if (DAG.SignBitIsZero(N0))
     return DAG.getNode(ISD::SRL, VT, N0, N1);
 
-  return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
+  return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
 }
 
 SDValue DAGCombiner::visitSRL(SDNode *N) {
@@ -2441,12 +2502,12 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
   
   // fold (srl c1, c2) -> c1 >>u c2
   if (N0C && N1C)
-    return DAG.getNode(ISD::SRL, VT, N0, N1);
+    return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
   // fold (srl 0, x) -> 0
   if (N0C && N0C->isNullValue())
     return N0;
   // fold (srl x, c >= size(x)) -> undef
-  if (N1C && N1C->getValue() >= OpSizeInBits)
+  if (N1C && N1C->getZExtValue() >= OpSizeInBits)
     return DAG.getNode(ISD::UNDEF, VT);
   // fold (srl x, 0) -> x
   if (N1C && N1C->isNullValue())
@@ -2459,8 +2520,8 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
   // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
   if (N1C && N0.getOpcode() == ISD::SRL && 
       N0.getOperand(1).getOpcode() == ISD::Constant) {
-    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
-    uint64_t c2 = N1C->getValue();
+    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
+    uint64_t c2 = N1C->getZExtValue();
     if (c1 + c2 > OpSizeInBits)
       return DAG.getConstant(0, VT);
     return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 
@@ -2471,17 +2532,17 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
   if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
     // Shifting in all undef bits?
     MVT SmallVT = N0.getOperand(0).getValueType();
-    if (N1C->getValue() >= SmallVT.getSizeInBits())
+    if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
       return DAG.getNode(ISD::UNDEF, VT);
 
     SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
-    AddToWorkList(SmallShift.Val);
+    AddToWorkList(SmallShift.getNode());
     return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
   }
   
   // fold (srl (sra X, Y), 31) -> (srl X, 31).  This srl only looks at the sign
   // bit, which is unmodified by sra.
-  if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) {
+  if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) {
     if (N0.getOpcode() == ISD::SRA)
       return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
   }
@@ -2513,18 +2574,35 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
       if (ShAmt) {
         Op = DAG.getNode(ISD::SRL, VT, Op,
                          DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
-        AddToWorkList(Op.Val);
+        AddToWorkList(Op.getNode());
       }
       return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
     }
   }
+
+  // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
+  // iff (trunc c) == c
+  if (N1.getOpcode() == ISD::TRUNCATE &&
+      N1.getOperand(0).getOpcode() == ISD::AND &&
+      N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
+    SDValue N101 = N1.getOperand(0).getOperand(1);
+    if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
+      MVT TruncVT = N1.getValueType();
+      SDValue N100 = N1.getOperand(0).getOperand(0);
+      return DAG.getNode(ISD::SRL, VT, N0,
+                         DAG.getNode(ISD::AND, TruncVT,
+                                     DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
+                                     DAG.getConstant(N101C->getZExtValue(),
+                                                     TruncVT)));
+    }
+  }
   
   // fold operands of srl based on knowledge that the low bits are not
   // demanded.
   if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
     return SDValue(N, 0);
   
-  return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue();
+  return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
 }
 
 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
@@ -2585,7 +2663,7 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
     SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
     if (VT == VT0)
       return XORNode;
-    AddToWorkList(XORNode.Val);
+    AddToWorkList(XORNode.getNode());
     if (VT.bitsGT(VT0))
       return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
     return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
@@ -2593,13 +2671,13 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
   // fold select C, 0, X -> ~C & X
   if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
     SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
-    AddToWorkList(XORNode.Val);
+    AddToWorkList(XORNode.getNode());
     return DAG.getNode(ISD::AND, VT, XORNode, N2);
   }
   // fold select C, X, 1 -> ~C | X
   if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
     SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
-    AddToWorkList(XORNode.Val);
+    AddToWorkList(XORNode.getNode());
     return DAG.getNode(ISD::OR, VT, XORNode, N1);
   }
   // fold select C, X, 0 -> C & X
@@ -2646,9 +2724,9 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
   
   // Determine if the condition we're dealing with is constant
   SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
-  if (SCC.Val) AddToWorkList(SCC.Val);
+  if (SCC.getNode()) AddToWorkList(SCC.getNode());
 
-  if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
+  if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
     if (!SCCC->isNullValue())
       return N2;    // cond always true -> true val
     else
@@ -2656,7 +2734,7 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
   }
   
   // Fold to a simpler select_cc
-  if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
+  if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
     return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 
                        SCC.getOperand(0), SCC.getOperand(1), N2, N3, 
                        SCC.getOperand(2));
@@ -2684,7 +2762,8 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
                                     TargetLowering &TLI) {
   bool HasCopyToRegUses = false;
   bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
-  for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end();
+  for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
+                            UE = N0.getNode()->use_end();
        UI != UE; ++UI) {
     SDNode *User = *UI;
     if (User == N)
@@ -2728,7 +2807,7 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
       SDNode *User = *UI;
       for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
         SDValue UseOp = User->getOperand(i);
-        if (UseOp.Val == N && UseOp.ResNo == 0) {
+        if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
           BothLiveOut = true;
           break;
         }
@@ -2758,10 +2837,10 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   if (N0.getOpcode() == ISD::TRUNCATE) {
     // fold (sext (truncate (load x))) -> (sext (smaller load x))
     // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
-    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
-    if (NarrowLoad.Val) {
-      if (NarrowLoad.Val != N0.Val)
-        CombineTo(N0.Val, NarrowLoad);
+    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
+    if (NarrowLoad.getNode()) {
+      if (NarrowLoad.getNode() != N0.getNode())
+        CombineTo(N0.getNode(), NarrowLoad);
       return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
     }
 
@@ -2803,9 +2882,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   }
   
   // fold (sext (load x)) -> (sext (truncate (sextload x)))
-  if (ISD::isNON_EXTLoad(N0.Val) &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
-       TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) {
+       TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
     bool DoXform = true;
     SmallVector<SDNode*, 4> SetCCs;
     if (!N0.hasOneUse())
@@ -2820,7 +2899,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
                                          LN0->getAlignment());
       CombineTo(N, ExtLoad);
       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
-      CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
+      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
       // Extend SetCC uses if necessary.
       for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
         SDNode *SetCC = SetCCs[i];
@@ -2842,19 +2921,20 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
 
   // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
   // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
-  if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
-      ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
+  if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
+      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
     if ((!AfterLegalize && !LN0->isVolatile()) ||
-        TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
+        TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
                                          LN0->getBasePtr(), LN0->getSrcValue(),
                                          LN0->getSrcValueOffset(), EVT,
                                          LN0->isVolatile(), 
                                          LN0->getAlignment());
       CombineTo(N, ExtLoad);
-      CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+      CombineTo(N0.getNode(),
+                DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
                 ExtLoad.getValue(1));
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
@@ -2866,7 +2946,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
                        DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
                        cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
-    if (SCC.Val) return SCC;
+    if (SCC.getNode()) return SCC;
   }
   
   // fold (sext x) -> (zext x) if the sign bit is known zero.
@@ -2892,10 +2972,10 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
   // fold (zext (truncate (load x))) -> (zext (smaller load x))
   // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
   if (N0.getOpcode() == ISD::TRUNCATE) {
-    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
-    if (NarrowLoad.Val) {
-      if (NarrowLoad.Val != N0.Val)
-        CombineTo(N0.Val, NarrowLoad);
+    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
+    if (NarrowLoad.getNode()) {
+      if (NarrowLoad.getNode() != N0.getNode())
+        CombineTo(N0.getNode(), NarrowLoad);
       return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
     }
   }
@@ -2928,9 +3008,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
   }
   
   // fold (zext (load x)) -> (zext (truncate (zextload x)))
-  if (ISD::isNON_EXTLoad(N0.Val) &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
-       TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
+       TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
     bool DoXform = true;
     SmallVector<SDNode*, 4> SetCCs;
     if (!N0.hasOneUse())
@@ -2945,7 +3025,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
                                          LN0->getAlignment());
       CombineTo(N, ExtLoad);
       SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad);
-      CombineTo(N0.Val, Trunc, ExtLoad.getValue(1));
+      CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
       // Extend SetCC uses if necessary.
       for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
         SDNode *SetCC = SetCCs[i];
@@ -2967,19 +3047,20 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
 
   // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
   // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
-  if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
-      ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
+  if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
+      ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
     if ((!AfterLegalize && !LN0->isVolatile()) ||
-        TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT)) {
+        TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
       SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
                                          LN0->getBasePtr(), LN0->getSrcValue(),
                                          LN0->getSrcValueOffset(), EVT,
                                          LN0->isVolatile(),
                                          LN0->getAlignment());
       CombineTo(N, ExtLoad);
-      CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+      CombineTo(N0.getNode(),
+                DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
                 ExtLoad.getValue(1));
       return SDValue(N, 0);   // Return N so it doesn't get rechecked!
     }
@@ -2991,7 +3072,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
                        DAG.getConstant(1, VT), DAG.getConstant(0, VT),
                        cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
-    if (SCC.Val) return SCC;
+    if (SCC.getNode()) return SCC;
   }
   
   return SDValue();
@@ -3015,10 +3096,10 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
   // fold (aext (truncate (load x))) -> (aext (smaller load x))
   // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
   if (N0.getOpcode() == ISD::TRUNCATE) {
-    SDValue NarrowLoad = ReduceLoadWidth(N0.Val);
-    if (NarrowLoad.Val) {
-      if (NarrowLoad.Val != N0.Val)
-        CombineTo(N0.Val, NarrowLoad);
+    SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
+    if (NarrowLoad.getNode()) {
+      if (NarrowLoad.getNode() != N0.getNode())
+        CombineTo(N0.getNode(), NarrowLoad);
       return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
     }
   }
@@ -3049,9 +3130,9 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
   }
   
   // fold (aext (load x)) -> (aext (truncate (extload x)))
-  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
-       TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
+       TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
                                        LN0->getBasePtr(), LN0->getSrcValue(),
@@ -3060,8 +3141,13 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
-              ExtLoad.getValue(1));
+    // Redirect any chain users to the new load.
+    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
+                                  SDValue(ExtLoad.getNode(), 1));
+    // If any node needs the original loaded value, recompute it.
+    if (!LN0->use_empty())
+      CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+                ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
   
@@ -3069,7 +3155,7 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
   // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
   // fold (aext ( extload x)) -> (aext (truncate (extload  x)))
   if (N0.getOpcode() == ISD::LOAD &&
-      !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+      !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
       N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT EVT = LN0->getMemoryVT();
@@ -3080,7 +3166,8 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+    CombineTo(N0.getNode(),
+              DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
               ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
@@ -3091,7 +3178,7 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
       SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
                        DAG.getConstant(1, VT), DAG.getConstant(0, VT),
                        cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
-    if (SCC.Val)
+    if (SCC.getNode())
       return SCC;
   }
   
@@ -3114,14 +3201,14 @@ SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
     break;
   case ISD::SRL:
     // Only look at single-use SRLs.
-    if (!V.Val->hasOneUse())
+    if (!V.getNode()->hasOneUse())
       break;
     if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
       // See if we can recursively simplify the LHS.
-      unsigned Amt = RHSC->getValue();
+      unsigned Amt = RHSC->getZExtValue();
       APInt NewMask = Mask << Amt;
       SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
-      if (SimplifyLHS.Val) {
+      if (SimplifyLHS.getNode()) {
         return DAG.getNode(ISD::SRL, V.getValueType(), 
                            SimplifyLHS, V.getOperand(1));
       }
@@ -3142,12 +3229,16 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
   MVT VT = N->getValueType(0);
   MVT EVT = N->getValueType(0);
 
+  // This transformation isn't valid for vector loads.
+  if (VT.isVector())
+    return SDValue();
+
   // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
   // extended to VT.
   if (Opc == ISD::SIGN_EXTEND_INREG) {
     ExtType = ISD::SEXTLOAD;
     EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
-    if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
+    if (AfterLegalize && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
       return SDValue();
   }
 
@@ -3156,7 +3247,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
   bool CombineSRL =  false;
   if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
     if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
-      ShAmt = N01->getValue();
+      ShAmt = N01->getZExtValue();
       // Is the shift amount a multiple of size of VT?
       if ((ShAmt & (EVTBits-1)) == 0) {
         N0 = N0.getOperand(0);
@@ -3169,17 +3260,16 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
 
   // Do not generate loads of non-round integer types since these can
   // be expensive (and would be wrong if the type is not byte sized).
-  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && VT.isRound() &&
+  if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() &&
+      cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
       // Do not change the width of a volatile load.
       !cast<LoadSDNode>(N0)->isVolatile()) {
-    assert(N0.getValueType().getSizeInBits() > EVTBits &&
-           "Cannot truncate to larger type!");
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     MVT PtrType = N0.getOperand(1).getValueType();
     // For big endian targets, we need to adjust the offset to the pointer to
     // load the correct bytes.
     if (TLI.isBigEndian()) {
-      unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits();
+      unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
       unsigned EVTStoreBits = EVT.getStoreSizeInBits();
       ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
     }
@@ -3187,22 +3277,22 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
     unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
     SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
                                    DAG.getConstant(PtrOff, PtrType));
-    AddToWorkList(NewPtr.Val);
+    AddToWorkList(NewPtr.getNode());
     SDValue Load = (ExtType == ISD::NON_EXTLOAD)
       ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
-                    LN0->getSrcValue(), LN0->getSrcValueOffset(),
+                    LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
                     LN0->isVolatile(), NewAlign)
       : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
-                       LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
-                       LN0->isVolatile(), NewAlign);
+                       LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
+                       EVT, LN0->isVolatile(), NewAlign);
     AddToWorkList(N);
     if (CombineSRL) {
       WorkListRemover DeadNodes(*this);
       DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
                                     &DeadNodes);
-      CombineTo(N->getOperand(0).Val, Load);
+      CombineTo(N->getOperand(0).getNode(), Load);
     } else
-      CombineTo(N0.Val, Load, Load.getValue(1));
+      CombineTo(N0.getNode(), Load, Load.getValue(1));
     if (ShAmt) {
       if (Opc == ISD::SIGN_EXTEND_INREG)
         return DAG.getNode(Opc, VT, Load, N->getOperand(1));
@@ -3238,6 +3328,15 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
     return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
   }
 
+  // fold (sext_in_reg (sext x)) -> (sext x)
+  // fold (sext_in_reg (aext x)) -> (sext x)
+  // if x is small enough.
+  if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
+    SDValue N00 = N0.getOperand(0);
+    if (N00.getValueType().getSizeInBits() < EVTBits)
+      return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1);
+  }
+
   // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
   if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
     return DAG.getZeroExtendInReg(N0, EVT);
@@ -3250,7 +3349,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   // fold (sext_in_reg (load x)) -> (smaller sextload x)
   // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
   SDValue NarrowLoad = ReduceLoadWidth(N);
-  if (NarrowLoad.Val)
+  if (NarrowLoad.getNode())
     return NarrowLoad;
 
   // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
@@ -3258,21 +3357,21 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
   // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
   if (N0.getOpcode() == ISD::SRL) {
     if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
-      if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) {
+      if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
         // We can turn this into an SRA iff the input to the SRL is already sign
         // extended enough.
         unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
-        if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits)
+        if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
           return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
       }
   }
 
   // fold (sext_inreg (extload x)) -> (sextload x)
-  if (ISD::isEXTLoad(N0.Val) && 
-      ISD::isUNINDEXEDLoad(N0.Val) &&
+  if (ISD::isEXTLoad(N0.getNode()) && 
+      ISD::isUNINDEXEDLoad(N0.getNode()) &&
       EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
-       TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
+       TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
                                        LN0->getBasePtr(), LN0->getSrcValue(),
@@ -3280,15 +3379,15 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
   // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
-  if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+  if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
       N0.hasOneUse() &&
       EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
-       TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
+       TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
                                        LN0->getBasePtr(), LN0->getSrcValue(),
@@ -3296,7 +3395,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
+    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
   return SDValue();
@@ -3336,7 +3435,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
   SDValue Shorter =
     GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
                                              VT.getSizeInBits()));
-  if (Shorter.Val)
+  if (Shorter.getNode())
     return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
 
   // fold (truncate (load x)) -> (smaller load x)
@@ -3347,8 +3446,8 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
   SDValue Elt = N->getOperand(i);
   if (Elt.getOpcode() != ISD::MERGE_VALUES)
-    return Elt.Val;
-  return Elt.getOperand(Elt.ResNo).Val;
+    return Elt.getNode();
+  return Elt.getOperand(Elt.getResNo()).getNode();
 }
 
 /// CombineConsecutiveLoads - build_pair (load, load) -> load
@@ -3371,7 +3470,7 @@ SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
       TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
     LoadSDNode *LD = cast<LoadSDNode>(LD1);
     unsigned Align = LD->getAlignment();
-    unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
+    unsigned NewAlign = TLI.getTargetData()->
       getABITypeAlignment(VT.getTypeForMVT());
     if (NewAlign <= Align &&
         (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT)))
@@ -3391,7 +3490,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
   // on the bitconvert.
   // First check to see if this is all constant.
   if (!AfterLegalize &&
-      N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
+      N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
       VT.isVector()) {
     bool isSimple = true;
     for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
@@ -3406,14 +3505,14 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
     assert(!DestEltVT.isVector() &&
            "Element type of vector ValueType must not be vector!");
     if (isSimple) {
-      return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
+      return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
     }
   }
   
-  // If the input is a constant, let getNode() fold it.
+  // If the input is a constant, let getNode fold it.
   if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
     SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
-    if (Res.Val != N) return Res;
+    if (Res.getNode() != N) return Res;
   }
   
   if (N0.getOpcode() == ISD::BIT_CONVERT)  // conv(conv(x,t1),t2) -> conv(x,t2)
@@ -3421,12 +3520,12 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
 
   // fold (conv (load x)) -> (load (conv*)x)
   // If the resultant load doesn't need a higher alignment than the original!
-  if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() &&
+  if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
       // Do not change the width of a volatile load.
       !cast<LoadSDNode>(N0)->isVolatile() &&
       (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
-    unsigned Align = TLI.getTargetMachine().getTargetData()->
+    unsigned Align = TLI.getTargetData()->
       getABITypeAlignment(VT.getTypeForMVT());
     unsigned OrigAlign = LN0->getAlignment();
     if (Align <= OrigAlign) {
@@ -3434,7 +3533,8 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
                                    LN0->getSrcValue(), LN0->getSrcValueOffset(),
                                    LN0->isVolatile(), OrigAlign);
       AddToWorkList(N);
-      CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
+      CombineTo(N0.getNode(),
+                DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
                 Load.getValue(1));
       return Load;
     }
@@ -3444,9 +3544,9 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
   // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
   // This often reduces constant pool loads.
   if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
-      N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
+      N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
     SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
-    AddToWorkList(NewConv.Val);
+    AddToWorkList(NewConv.getNode());
     
     APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
     if (N0.getOpcode() == ISD::FNEG)
@@ -3458,45 +3558,45 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
   // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign'
   // Note that we don't handle copysign(x,cst) because this can always be folded
   // to an fneg or fabs.
-  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
+  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
       isa<ConstantFPSDNode>(N0.getOperand(0)) &&
       VT.isInteger() && !VT.isVector()) {
     unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
     SDValue X = DAG.getNode(ISD::BIT_CONVERT,
                               MVT::getIntegerVT(OrigXWidth),
                               N0.getOperand(1));
-    AddToWorkList(X.Val);
+    AddToWorkList(X.getNode());
 
     // If X has a different width than the result/lhs, sext it or truncate it.
     unsigned VTWidth = VT.getSizeInBits();
     if (OrigXWidth < VTWidth) {
       X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
-      AddToWorkList(X.Val);
+      AddToWorkList(X.getNode());
     } else if (OrigXWidth > VTWidth) {
       // To get the sign bit in the right place, we have to shift it right
       // before truncating.
       X = DAG.getNode(ISD::SRL, X.getValueType(), X, 
                       DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
-      AddToWorkList(X.Val);
+      AddToWorkList(X.getNode());
       X = DAG.getNode(ISD::TRUNCATE, VT, X);
-      AddToWorkList(X.Val);
+      AddToWorkList(X.getNode());
     }
     
     APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
     X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
-    AddToWorkList(X.Val);
+    AddToWorkList(X.getNode());
 
     SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
     Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
-    AddToWorkList(Cst.Val);
+    AddToWorkList(Cst.getNode());
 
     return DAG.getNode(ISD::OR, VT, X, Cst);
   }
 
   // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 
   if (N0.getOpcode() == ISD::BUILD_PAIR) {
-    SDValue CombineLD = CombineConsecutiveLoads(N0.Val, VT);
-    if (CombineLD.Val)
+    SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
+    if (CombineLD.getNode())
       return CombineLD;
   }
   
@@ -3527,7 +3627,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
     SmallVector<SDValue, 8> Ops;
     for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
       Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
-      AddToWorkList(Ops.back().Val);
+      AddToWorkList(Ops.back().getNode());
     }
     MVT VT = MVT::getVectorVT(DstEltVT,
                               BV->getValueType(0).getVectorNumElements());
@@ -3542,7 +3642,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
     // same sizes.
     assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
     MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
-    BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
+    BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
     SrcEltVT = IntVT;
   }
   
@@ -3551,7 +3651,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
   if (DstEltVT.isFloatingPoint()) {
     assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
     MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
-    SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
+    SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
     
     // Next, convert to FP elements of the same size.
     return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
@@ -3631,7 +3731,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (fadd c1, c2) -> c1+c2
@@ -3651,7 +3751,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
   
   // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
   if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
-      N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
+      N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
     return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
                        DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
   
@@ -3668,7 +3768,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (fsub c1, c2) -> c1-c2
@@ -3698,7 +3798,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (fmul c1, c2) -> c1*c2
@@ -3728,7 +3828,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
   
   // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
   if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
-      N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
+      N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
     return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
                        DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
   
@@ -3745,7 +3845,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
   // fold vector ops
   if (VT.isVector()) {
     SDValue FoldedVOp = SimplifyVBinOp(N);
-    if (FoldedVOp.Val) return FoldedVOp;
+    if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
   // fold (fdiv c1, c2) -> c1/c2
@@ -3912,15 +4012,15 @@ SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
   if (N0.getOpcode() == ISD::FP_ROUND) {
     // This is a value preserving truncation if both round's are.
     bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
-                   N0.Val->getConstantOperandVal(1) == 1;
+                   N0.getNode()->getConstantOperandVal(1) == 1;
     return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
                        DAG.getIntPtrConstant(IsTrunc));
   }
   
   // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
-  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
+  if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
     SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
-    AddToWorkList(Tmp.Val);
+    AddToWorkList(Tmp.getNode());
     return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
   }
   
@@ -3935,7 +4035,7 @@ SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
   
   // fold (fp_round_inreg c1fp) -> c1fp
   if (N0CFP) {
-    SDValue Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
+    SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
     return DAG.getNode(ISD::FP_EXTEND, VT, Round);
   }
   return SDValue();
@@ -3957,7 +4057,8 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
 
   // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
   // value of X.
-  if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
+  if (N0.getOpcode() == ISD::FP_ROUND
+      && N0.getNode()->getConstantOperandVal(1) == 1) {
     SDValue In = N0.getOperand(0);
     if (In.getValueType() == VT) return In;
     if (VT.bitsLT(In.getValueType()))
@@ -3966,9 +4067,9 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
   }
       
   // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
-  if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+  if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
       ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) ||
-       TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
+       TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
                                        LN0->getBasePtr(), LN0->getSrcValue(),
@@ -3977,8 +4078,8 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
                                        LN0->isVolatile(), 
                                        LN0->getAlignment());
     CombineTo(N, ExtLoad);
-    CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
-                                  DAG.getIntPtrConstant(1)),
+    CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(),
+                                        ExtLoad, DAG.getIntPtrConstant(1)),
               ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
@@ -3994,7 +4095,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
 
   // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
   // constant pool values.
-  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
+  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
       N0.getOperand(0).getValueType().isInteger() &&
       !N0.getOperand(0).getValueType().isVector()) {
     SDValue Int = N0.getOperand(0);
@@ -4002,7 +4103,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
     if (IntVT.isInteger() && !IntVT.isVector()) {
       Int = DAG.getNode(ISD::XOR, IntVT, Int, 
                         DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
-      AddToWorkList(Int.Val);
+      AddToWorkList(Int.getNode());
       return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
     }
   }
@@ -4028,7 +4129,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
   
   // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
   // constant pool values.
-  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
+  if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
       N0.getOperand(0).getValueType().isInteger() &&
       !N0.getOperand(0).getValueType().isVector()) {
     SDValue Int = N0.getOperand(0);
@@ -4036,7 +4137,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {
     if (IntVT.isInteger() && !IntVT.isVector()) {
       Int = DAG.getNode(ISD::AND, IntVT, Int, 
                         DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
-      AddToWorkList(Int.Val);
+      AddToWorkList(Int.getNode());
       return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
     }
   }
@@ -4074,9 +4175,9 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
   
   // Use SimplifySetCC to simplify SETCC's.
   SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
-  if (Simp.Val) AddToWorkList(Simp.Val);
+  if (Simp.getNode()) AddToWorkList(Simp.getNode());
 
-  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
+  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
 
   // fold br_cc true, dest -> br dest (unconditional branch)
   if (SCCC && !SCCC->isNullValue())
@@ -4087,7 +4188,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
     return N->getOperand(0);
 
   // fold to a simpler setcc
-  if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
+  if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
     return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 
                        Simp.getOperand(2), Simp.getOperand(0),
                        Simp.getOperand(1), N->getOperand(4));
@@ -4131,7 +4232,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
   // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
   // out.  There is no reason to make this a preinc/predec.
   if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
-      Ptr.Val->hasOneUse())
+      Ptr.getNode()->hasOneUse())
     return false;
 
   // Ask the target to do addressing mode selection.
@@ -4161,14 +4262,14 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
   // Check #2.
   if (!isLoad) {
     SDValue Val = cast<StoreSDNode>(N)->getValue();
-    if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val))
+    if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
       return false;
   }
 
   // Now check for #3 and #4.
   bool RealUse = false;
-  for (SDNode::use_iterator I = Ptr.Val->use_begin(),
-         E = Ptr.Val->use_end(); I != E; ++I) {
+  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
+         E = Ptr.getNode()->use_end(); I != E; ++I) {
     SDNode *Use = *I;
     if (Use == N)
       continue;
@@ -4192,7 +4293,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
   ++PreIndexedNodes;
   ++NodesCombined;
   DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
-  DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
+  DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
   DOUT << '\n';
   WorkListRemover DeadNodes(*this);
   if (isLoad) {
@@ -4211,8 +4312,8 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
   // Replace the uses of Ptr with uses of the updated base value.
   DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
                                 &DeadNodes);
-  removeFromWorkList(Ptr.Val);
-  DAG.DeleteNode(Ptr.Val);
+  removeFromWorkList(Ptr.getNode());
+  DAG.DeleteNode(Ptr.getNode());
 
   return true;
 }
@@ -4249,11 +4350,11 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
   } else
     return false;
 
-  if (Ptr.Val->hasOneUse())
+  if (Ptr.getNode()->hasOneUse())
     return false;
   
-  for (SDNode::use_iterator I = Ptr.Val->use_begin(),
-         E = Ptr.Val->use_end(); I != E; ++I) {
+  for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
+         E = Ptr.getNode()->use_end(); I != E; ++I) {
     SDNode *Op = *I;
     if (Op == N ||
         (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
@@ -4280,10 +4381,10 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
 
       // Check for #1.
       bool TryNext = false;
-      for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
-             EE = BasePtr.Val->use_end(); II != EE; ++II) {
+      for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
+             EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
         SDNode *Use = *II;
-        if (Use == Ptr.Val)
+        if (Use == Ptr.getNode())
           continue;
 
         // If all the uses are load / store addresses, then don't do the
@@ -4294,9 +4395,9 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
                  EEE = Use->use_end(); III != EEE; ++III) {
             SDNode *UseUse = *III;
             if (!((UseUse->getOpcode() == ISD::LOAD &&
-                   cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
+                   cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
                   (UseUse->getOpcode() == ISD::STORE &&
-                   cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)))
+                   cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
               RealUse = true;
           }
 
@@ -4317,7 +4418,7 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
         ++PostIndexedNodes;
         ++NodesCombined;
         DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
-        DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
+        DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
         DOUT << '\n';
         WorkListRemover DeadNodes(*this);
         if (isLoad) {
@@ -4366,7 +4467,7 @@ static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
     // FIXME: Handle FI+CST.
     const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
     if (MFI.isFixedObjectIndex(FrameIdx)) {
-      int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx);
+      int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
 
       // The alignment of the frame index can be determined from its offset from
       // the incoming frame position.  If the frame object is at offset 32 and
@@ -4395,7 +4496,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
   SDValue Ptr   = LD->getBasePtr();
   
   // Try to infer better alignment information than the load already has.
-  if (LD->isUnindexed()) {
+  if (!Fast && LD->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > LD->getAlignment())
         return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
@@ -4420,7 +4521,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
         // Now we replace use of chain2 with chain1.  This makes the second load
         // isomorphic to the one we are deleting, and thus makes this load live.
         DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
-        DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG));
+        DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
         DOUT << "\n";
         WorkListRemover DeadNodes(*this);
         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
@@ -4436,7 +4537,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
       if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
         SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
         DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
-        DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG));
+        DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
         DOUT << " and 2 other values\n";
         WorkListRemover DeadNodes(*this);
         DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
@@ -4457,7 +4558,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
   // TODO: Handle TRUNCSTORE/LOADEXT
   if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
       !LD->isVolatile()) {
-    if (ISD::isNON_TRUNCStore(Chain.Val)) {
+    if (ISD::isNON_TRUNCStore(Chain.getNode())) {
       StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
       if (PrevST->getBasePtr() == Ptr &&
           PrevST->getValue().getValueType() == N->getValueType(0))
@@ -4513,7 +4614,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
   SDValue Ptr   = ST->getBasePtr();
   
   // Try to infer better alignment information than the store already has.
-  if (ST->isUnindexed()) {
+  if (!Fast && ST->isUnindexed()) {
     if (unsigned Align = InferAlignment(Ptr, DAG)) {
       if (Align > ST->getAlignment())
         return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(),
@@ -4528,7 +4629,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
       ST->isUnindexed()) {
     unsigned Align = ST->getAlignment();
     MVT SVT = Value.getOperand(0).getValueType();
-    unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
+    unsigned OrigAlign = TLI.getTargetData()->
       getABITypeAlignment(SVT.getTypeForMVT());
     if (Align <= OrigAlign &&
         ((!AfterLegalize && !ST->isVolatile()) ||
@@ -4555,7 +4656,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
         if ((!AfterLegalize && !ST->isVolatile()) ||
             TLI.isOperationLegal(ISD::STORE, MVT::i32)) {
           Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
-                              convertToAPInt().getZExtValue(), MVT::i32);
+                              bitcastToAPInt().getZExtValue(), MVT::i32);
           return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
                               ST->getSrcValueOffset(), ST->isVolatile(),
                               ST->getAlignment());
@@ -4564,7 +4665,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
       case MVT::f64:
         if ((!AfterLegalize && !ST->isVolatile()) ||
             TLI.isOperationLegal(ISD::STORE, MVT::i64)) {
-          Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
+          Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
                                   getZExtValue(), MVT::i64);
           return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
                               ST->getSrcValueOffset(), ST->isVolatile(),
@@ -4574,7 +4675,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
           // Many FP stores are not made apparent until after legalize, e.g. for
           // argument passing.  Since this is so common, custom legalize the
           // 64-bit integer store into two 32-bit stores.
-          uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
+          uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
           SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
           SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
           if (TLI.isBigEndian()) std::swap(Lo, Hi);
@@ -4641,8 +4742,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
       GetDemandedBits(Value,
                  APInt::getLowBitsSet(Value.getValueSizeInBits(),
                                       ST->getMemoryVT().getSizeInBits()));
-    AddToWorkList(Value.Val);
-    if (Shorter.Val)
+    AddToWorkList(Value.getNode());
+    if (Shorter.getNode())
       return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
                                ST->getSrcValueOffset(), ST->getMemoryVT(),
                                ST->isVolatile(), ST->getAlignment());
@@ -4672,7 +4773,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
   // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
   // truncating store.  We can do this even if this is already a truncstore.
   if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
-      && Value.Val->hasOneUse() && ST->isUnindexed() &&
+      && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
       TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
                             ST->getMemoryVT())) {
     return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
@@ -4691,8 +4792,9 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
   // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
   // vector with the inserted element.
   if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
-    unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
-    SmallVector<SDValue, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+    SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
+                                InVec.getNode()->op_end());
     if (Elt < Ops.size())
       Ops[Elt] = InVal;
     return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
@@ -4715,7 +4817,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
   SDValue EltNo = N->getOperand(1);
 
   if (isa<ConstantSDNode>(EltNo)) {
-    unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
+    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
     bool NewLoad = false;
     MVT VT = InVec.getValueType();
     MVT EVT = VT.getVectorElementType();
@@ -4730,23 +4832,23 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
     }
 
     LoadSDNode *LN0 = NULL;
-    if (ISD::isNormalLoad(InVec.Val))
+    if (ISD::isNormalLoad(InVec.getNode()))
       LN0 = cast<LoadSDNode>(InVec);
     else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
              InVec.getOperand(0).getValueType() == EVT &&
-             ISD::isNormalLoad(InVec.getOperand(0).Val)) {
+             ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
       LN0 = cast<LoadSDNode>(InVec.getOperand(0));
     } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
       // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
       // =>
       // (load $addr+1*size)
       unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
-                                          getOperand(Elt))->getValue();
+                                          getOperand(Elt))->getZExtValue();
       unsigned NumElems = InVec.getOperand(2).getNumOperands();
       InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
       if (InVec.getOpcode() == ISD::BIT_CONVERT)
         InVec = InVec.getOperand(0);
-      if (ISD::isNormalLoad(InVec.Val)) {
+      if (ISD::isNormalLoad(InVec.getNode())) {
         LN0 = cast<LoadSDNode>(InVec);
         Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
       }
@@ -4758,7 +4860,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
     if (NewLoad) {
       // Check the resultant load doesn't need a higher alignment than the
       // original load.
-      unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
+      unsigned NewAlign = TLI.getTargetData()->
         getABITypeAlignment(LVT.getTypeForMVT());
       if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT))
         return SDValue();
@@ -4816,9 +4918,9 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
     if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
       continue;
     
-    if (VecIn1.Val == 0) {
+    if (VecIn1.getNode() == 0) {
       VecIn1 = ExtractedFromVec;
-    } else if (VecIn2.Val == 0) {
+    } else if (VecIn2.getNode() == 0) {
       VecIn2 = ExtractedFromVec;
     } else {
       // Too many inputs.
@@ -4828,7 +4930,7 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
   }
   
   // If everything is good, we can make a shuffle operation.
-  if (VecIn1.Val) {
+  if (VecIn1.getNode()) {
     SmallVector<SDValue, 8> BuildVecIndices;
     for (unsigned i = 0; i != NumInScalars; ++i) {
       if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
@@ -4845,7 +4947,8 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
       }
 
       // Otherwise, use InIdx + VecSize
-      unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
+      unsigned Idx =
+        cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue();
       BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
     }
     
@@ -4855,7 +4958,7 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
     // Return the new VECTOR_SHUFFLE node.
     SDValue Ops[5];
     Ops[0] = VecIn1;
-    if (VecIn2.Val) {
+    if (VecIn2.getNode()) {
       Ops[1] = VecIn2;
     } else {
       // Use an undef build_vector as input for the second operand.
@@ -4864,7 +4967,7 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
                                                EltType));
       Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
                            &UnOps[0], UnOps.size());
-      AddToWorkList(Ops[1].Val);
+      AddToWorkList(Ops[1].getNode());
     }
     Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
                          &BuildVecIndices[0], BuildVecIndices.size());
@@ -4896,7 +4999,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
   bool isIdentity = true;
   for (unsigned i = 0; i != NumElts; ++i) {
     if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
-        cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
+        cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) {
       isIdentity = false;
       break;
     }
@@ -4907,7 +5010,8 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
   isIdentity = true;
   for (unsigned i = 0; i != NumElts; ++i) {
     if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
-        cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
+        cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() !=
+          i+NumElts) {
       isIdentity = false;
       break;
     }
@@ -4922,7 +5026,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
   unsigned BaseIdx = 0;
   for (unsigned i = 0; i != NumElts; ++i)
     if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
-      unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
+      unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue();
       int V = (Idx < NumElts) ? 0 : 1;
       if (VecNum == -1) {
         VecNum = V;
@@ -4946,7 +5050,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
   // If it is a splat, check if the argument vector is a build_vector with
   // all scalar elements the same.
   if (isSplat) {
-    SDNode *V = N0.Val;
+    SDNode *V = N0.getNode();
 
     // If this is a bit convert that changes the element type of the vector but
     // not the number of vector elements, look through it.  Be careful not to
@@ -4955,7 +5059,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
       SDValue ConvInput = V->getOperand(0);
       if (ConvInput.getValueType().isVector() &&
           ConvInput.getValueType().getVectorNumElements() == NumElts)
-        V = ConvInput.Val;
+        V = ConvInput.getNode();
     }
 
     if (V->getOpcode() == ISD::BUILD_VECTOR) {
@@ -4970,7 +5074,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
           }
         }
         // Splat of <u, u, u, u>, return <u, u, u, u>
-        if (!Base.Val)
+        if (!Base.getNode())
           return N0;
         for (unsigned i = 0; i != NumElems; ++i) {
           if (V->getOperand(i) != Base) {
@@ -4993,18 +5097,20 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
     SmallVector<SDValue, 8> MappedOps;
     for (unsigned i = 0; i != NumElts; ++i) {
       if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
-          cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
+          cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() <
+            NumElts) {
         MappedOps.push_back(ShufMask.getOperand(i));
       } else {
         unsigned NewIdx = 
-          cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
+          cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
+          NumElts;
         MappedOps.push_back(DAG.getConstant(NewIdx,
                                         ShufMask.getOperand(i).getValueType()));
       }
     }
     ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
                            &MappedOps[0], MappedOps.size());
-    AddToWorkList(ShufMask.Val);
+    AddToWorkList(ShufMask.getNode());
     return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
                        N0,
                        DAG.getNode(ISD::UNDEF, N->getValueType(0)),
@@ -5028,29 +5134,29 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
       std::vector<SDValue> IdxOps;
       unsigned NumOps = RHS.getNumOperands();
       unsigned NumElts = NumOps;
-      MVT EVT = RHS.getValueType().getVectorElementType();
       for (unsigned i = 0; i != NumElts; ++i) {
         SDValue Elt = RHS.getOperand(i);
         if (!isa<ConstantSDNode>(Elt))
           return SDValue();
         else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
-          IdxOps.push_back(DAG.getConstant(i, EVT));
+          IdxOps.push_back(DAG.getIntPtrConstant(i));
         else if (cast<ConstantSDNode>(Elt)->isNullValue())
-          IdxOps.push_back(DAG.getConstant(NumElts, EVT));
+          IdxOps.push_back(DAG.getIntPtrConstant(NumElts));
         else
           return SDValue();
       }
 
       // Let's see if the target supports this vector_shuffle.
-      if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
+      if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG))
         return SDValue();
 
       // Return the new VECTOR_SHUFFLE node.
+      MVT EVT = RHS.getValueType().getVectorElementType();
       MVT VT = MVT::getVectorVT(EVT, NumElts);
       std::vector<SDValue> Ops;
       LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
       Ops.push_back(LHS);
-      AddToWorkList(LHS.Val);
+      AddToWorkList(LHS.getNode());
       std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
       Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
                                 &ZeroOps[0], ZeroOps.size()));
@@ -5080,7 +5186,7 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   SDValue Shuffle = XformToShuffleWithZero(N);
-  if (Shuffle.Val) return Shuffle;
+  if (Shuffle.getNode()) return Shuffle;
 
   // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
   // this operation.
@@ -5102,13 +5208,13 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
       if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
           N->getOpcode() == ISD::FDIV) {
         if ((RHSOp.getOpcode() == ISD::Constant &&
-             cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
+             cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
             (RHSOp.getOpcode() == ISD::ConstantFP &&
-             cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
+             cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
           break;
       }
       Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
-      AddToWorkList(Ops.back().Val);
+      AddToWorkList(Ops.back().getNode());
       assert((Ops.back().getOpcode() == ISD::UNDEF ||
               Ops.back().getOpcode() == ISD::Constant ||
               Ops.back().getOpcode() == ISD::ConstantFP) &&
@@ -5132,14 +5238,14 @@ SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){
   // If we got a simplified select_cc node back from SimplifySelectCC, then
   // break it down into a new SETCC node, and a new SELECT node, and then return
   // the SELECT node, since we were called with a SELECT node.
-  if (SCC.Val) {
+  if (SCC.getNode()) {
     // Check to see if we got a select_cc back (to turn into setcc/select).
     // Otherwise, just return whatever node we got back, like fabs.
     if (SCC.getOpcode() == ISD::SELECT_CC) {
       SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
                                     SCC.getOperand(0), SCC.getOperand(1), 
                                     SCC.getOperand(4));
-      AddToWorkList(SETCC.Val);
+      AddToWorkList(SETCC.getNode());
       return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
                          SCC.getOperand(3), SETCC);
     }
@@ -5183,8 +5289,8 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
         if (TheSelect->getOpcode() == ISD::SELECT) {
           // Check that the condition doesn't reach either load.  If so, folding
           // this will induce a cycle into the DAG.
-          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
-              !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) {
+          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
+              !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
             Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
                                TheSelect->getOperand(0), LLD->getBasePtr(),
                                RLD->getBasePtr());
@@ -5192,10 +5298,10 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
         } else {
           // Check that the condition doesn't reach either load.  If so, folding
           // this will induce a cycle into the DAG.
-          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
-              !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) &&
-              !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) &&
-              !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) {
+          if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
+              !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
+              !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
+              !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
             Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
                              TheSelect->getOperand(0),
                              TheSelect->getOperand(1), 
@@ -5204,7 +5310,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
           }
         }
         
-        if (Addr.Val) {
+        if (Addr.getNode()) {
           SDValue Load;
           if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
             Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
@@ -5226,8 +5332,8 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
         
           // Users of the old loads now use the new load's chain.  We know the
           // old-load value is dead now.
-          CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
-          CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
+          CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
+          CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
           return true;
         }
       }
@@ -5242,14 +5348,14 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
                                       ISD::CondCode CC, bool NotExtCompare) {
   
   MVT VT = N2.getValueType();
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
-  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
-  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
+  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
+  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
 
   // Determine if the condition we're dealing with is constant
   SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false);
-  if (SCC.Val) AddToWorkList(SCC.Val);
-  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
+  if (SCC.getNode()) AddToWorkList(SCC.getNode());
+  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
 
   // fold select_cc true, x, y -> x
   if (SCCC && !SCCC->isNullValue())
@@ -5293,20 +5399,20 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
         ShCtV = XType.getSizeInBits()-ShCtV-1;
         SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
         SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
-        AddToWorkList(Shift.Val);
+        AddToWorkList(Shift.getNode());
         if (XType.bitsGT(AType)) {
           Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
-          AddToWorkList(Shift.Val);
+          AddToWorkList(Shift.getNode());
         }
         return DAG.getNode(ISD::AND, AType, Shift, N2);
       }
       SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
                                     DAG.getConstant(XType.getSizeInBits()-1,
                                                     TLI.getShiftAmountTy()));
-      AddToWorkList(Shift.Val);
+      AddToWorkList(Shift.getNode());
       if (XType.bitsGT(AType)) {
         Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
-        AddToWorkList(Shift.Val);
+        AddToWorkList(Shift.getNode());
       }
       return DAG.getNode(ISD::AND, AType, Shift, N2);
     }
@@ -5336,8 +5442,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
       SCC  = DAG.getSetCC(MVT::i1, N0, N1, CC);
       Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
     }
-    AddToWorkList(SCC.Val);
-    AddToWorkList(Temp.Val);
+    AddToWorkList(SCC.getNode());
+    AddToWorkList(Temp.getNode());
     
     if (N2C->getAPIntValue() == 1)
       return Temp;
@@ -5399,8 +5505,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
                                   DAG.getConstant(XType.getSizeInBits()-1,
                                                   TLI.getShiftAmountTy()));
     SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
-    AddToWorkList(Shift.Val);
-    AddToWorkList(Add.Val);
+    AddToWorkList(Shift.getNode());
+    AddToWorkList(Add.getNode());
     return DAG.getNode(ISD::XOR, XType, Add, Shift);
   }
   // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
@@ -5414,8 +5520,8 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
                                       DAG.getConstant(XType.getSizeInBits()-1,
                                                       TLI.getShiftAmountTy()));
         SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
-        AddToWorkList(Shift.Val);
-        AddToWorkList(Add.Val);
+        AddToWorkList(Shift.getNode());
+        AddToWorkList(Add.getNode());
         return DAG.getNode(ISD::XOR, XType, Add, Shift);
       }
     }
@@ -5471,7 +5577,7 @@ static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
   if (Base.getOpcode() == ISD::ADD) {
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
       Base = Base.getOperand(0);
-      Offset += C->getValue();
+      Offset += C->getZExtValue();
     }
   }
   
@@ -5569,8 +5675,8 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
     Chains.pop_back();
     
      // Don't bother if we've been before.
-    if (Visited.find(Chain.Val) != Visited.end()) continue;
-    Visited.insert(Chain.Val);
+    if (Visited.find(Chain.getNode()) != Visited.end()) continue;
+    Visited.insert(Chain.getNode());
   
     switch (Chain.getOpcode()) {
     case ISD::EntryToken:
@@ -5584,7 +5690,7 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
       int64_t OpSize;
       const Value *OpSrcValue;
       int OpSrcValueOffset;
-      bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
+      bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
                                     OpSrcValue, OpSrcValueOffset);
       
       // If chain is alias then stop here.
@@ -5596,7 +5702,7 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
         // Look further up the chain.
         Chains.push_back(Chain.getOperand(0));      
         // Clean up old chain.
-        AddToWorkList(Chain.Val);
+        AddToWorkList(Chain.getNode());
       }
       break;
     }
@@ -5609,7 +5715,7 @@ void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
       for (unsigned n = Chain.getNumOperands(); n;)
         Chains.push_back(Chain.getOperand(--n));
       // Eliminate the token factor if we can.
-      AddToWorkList(Chain.Val);
+      AddToWorkList(Chain.getNode());
       break;
       
     default:
@@ -5641,15 +5747,16 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
                                    &Aliases[0], Aliases.size());
 
   // Make sure the old chain gets cleaned up.
-  if (NewChain != OldChain) AddToWorkList(OldChain.Val);
+  if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
   
   return NewChain;
 }
 
 // SelectionDAG::Combine - This is the entry point for the file.
 //
-void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
+void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA,
+                           bool Fast) {
   /// run - This is the main entry point to this class.
   ///
-  DAGCombiner(*this, AA).Run(RunningAfterLegalize);
+  DAGCombiner(*this, AA, Fast).Run(RunningAfterLegalize);
 }