X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FDAGCombiner.cpp;h=581d6ee0426668ae65256c5dec9d0f15794ce0d8;hb=7ba11c552b8a25ad1272b44d96e886a784dae0b7;hp=9db987936377eefe8ad48140177343adfe9559c4;hpb=ad205a76871b5112a4bf70edca0df9d03b92de49;p=oota-llvm.git

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9db98793637..581d6ee0426 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -592,6 +592,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
   AfterLegalize = RunningAfterLegalize;
 
   // Add all the dag nodes to the worklist.
+  WorkList.reserve(DAG.allnodes_size());
   for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
        E = DAG.allnodes_end(); I != E; ++I)
     WorkList.push_back(I);
@@ -1057,10 +1058,8 @@ SDOperand DAGCombiner::visitADDC(SDNode *N) {
                      DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
   
   // canonicalize constant to RHS.
-  if (N0C && !N1C) {
-    SDOperand Ops[] = { N1, N0 };
-    return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
-  }
+  if (N0C && !N1C)
+    return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
   
   // fold (addc x, 0) -> x + no carry out
   if (N1C && N1C->isNullValue())
@@ -1094,16 +1093,12 @@ SDOperand DAGCombiner::visitADDE(SDNode *N) {
   //MVT VT = N0.getValueType();
   
   // canonicalize constant to RHS
-  if (N0C && !N1C) {
-    SDOperand Ops[] = { N1, N0, CarryIn };
-    return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
-  }
+  if (N0C && !N1C)
+    return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn);
   
   // fold (adde x, y, false) -> (addc x, y)
-  if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
-    SDOperand Ops[] = { N1, N0 };
-    return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
-  }
+  if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
+    return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0);
   
   return SDOperand();
 }
@@ -3451,7 +3446,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
     if (Align <= OrigAlign) {
       SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
                                    LN0->getSrcValue(), LN0->getSrcValueOffset(),
-                                   LN0->isVolatile(), Align);
+                                   LN0->isVolatile(), OrigAlign);
       AddToWorkList(N);
       CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
                 Load.getValue(1));
@@ -3850,10 +3845,22 @@ SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   MVT VT = N->getValueType(0);
-  
+  MVT OpVT = N0.getValueType();
+
   // fold (sint_to_fp c1) -> c1fp
-  if (N0C && N0.getValueType() != MVT::ppcf128)
+  if (N0C && OpVT != MVT::ppcf128)
     return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
+  
+  // If the input is a legal type, and SINT_TO_FP is not legal on this target,
+  // but UINT_TO_FP is legal on this target, try to convert.
+  if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) &&
+      TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) {
+    // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 
+    if (DAG.SignBitIsZero(N0))
+      return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
+  }
+  
+  
   return SDOperand();
 }
 
@@ -3861,10 +3868,21 @@ SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
   MVT VT = N->getValueType(0);
+  MVT OpVT = N0.getValueType();
 
   // fold (uint_to_fp c1) -> c1fp
-  if (N0C && N0.getValueType() != MVT::ppcf128)
+  if (N0C && OpVT != MVT::ppcf128)
     return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
+  
+  // If the input is a legal type, and UINT_TO_FP is not legal on this target,
+  // but SINT_TO_FP is legal on this target, try to convert.
+  if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) &&
+      TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) {
+    // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 
+    if (DAG.SignBitIsZero(N0))
+      return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
+  }
+  
   return SDOperand();
 }
 
@@ -4530,7 +4548,7 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
         ((!AfterLegalize && !ST->isVolatile()) ||
          TLI.isOperationLegal(ISD::STORE, SVT)))
       return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
-                          ST->getSrcValueOffset(), ST->isVolatile(), Align);
+                          ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
   }
 
   // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'