X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FLegalizeDAG.cpp;h=4b4c02bd8d82ae48ce89ae8d16502e7bd1e605b9;hb=dddc6291fb5274282a20d5923b50535d456d34a4;hp=7812187fa43406e5eb50bc82750f410d8fe1b75c;hpb=db45d1c649aa2e7c71accd8ad460aa764886cab3;p=oota-llvm.git

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 7812187fa43..4b4c02bd8d8 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -22,6 +22,7 @@
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetSubtarget.h"
 #include "llvm/CallingConv.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
@@ -85,17 +86,17 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize {
   /// LegalizedNodes - For nodes that are of legal width, and that have more
   /// than one use, this map indicates what regularized operand to use.  This
   /// allows us to avoid legalizing the same thing more than once.
-  DenseMap<SDOperandImpl, SDOperand> LegalizedNodes;
+  DenseMap<SDOperand, SDOperand> LegalizedNodes;
 
   /// PromotedNodes - For nodes that are below legal width, and that have more
   /// than one use, this map indicates what promoted value to use.  This allows
   /// us to avoid promoting the same thing more than once.
-  DenseMap<SDOperandImpl, SDOperand> PromotedNodes;
+  DenseMap<SDOperand, SDOperand> PromotedNodes;
 
   /// ExpandedNodes - For nodes that need to be expanded this map indicates
   /// which which operands are the expanded version of the input.  This allows
   /// us to avoid expanding the same node more than once.
-  DenseMap<SDOperandImpl, std::pair<SDOperand, SDOperand> > ExpandedNodes;
+  DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
 
   /// SplitNodes - For vector nodes that need to be split, this map indicates
   /// which which operands are the split version of the input.  This allows us
@@ -114,26 +115,25 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize {
       LegalizedNodes.insert(std::make_pair(To, To));
   }
   void AddPromotedOperand(SDOperand From, SDOperand To) {
-    bool isNew = PromotedNodes.insert(std::make_pair(From, To));
+    bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
     assert(isNew && "Got into the map somehow?");
     // If someone requests legalization of the new node, return itself.
     LegalizedNodes.insert(std::make_pair(To, To));
   }
 
 public:
-
-  SelectionDAGLegalize(SelectionDAG &DAG);
+  explicit SelectionDAGLegalize(SelectionDAG &DAG);
 
   /// getTypeAction - Return how we should legalize values of this type, either
   /// it is already legal or we need to expand it into multiple registers of
   /// smaller integer type, or we need to promote it to a larger type.
-  LegalizeAction getTypeAction(MVT::ValueType VT) const {
+  LegalizeAction getTypeAction(MVT VT) const {
     return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
   }
 
   /// isTypeLegal - Return true if this type is legal on this target.
   ///
-  bool isTypeLegal(MVT::ValueType VT) const {
+  bool isTypeLegal(MVT VT) const {
     return getTypeAction(VT) == Legal;
   }
 
@@ -154,6 +154,13 @@ private:
   /// no way of lowering.  "Unroll" the vector, splitting out the scalars and
   /// operating on each element individually.
   SDOperand UnrollVectorOp(SDOperand O);
+  
+  /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
+  /// insertion index for the INSERT_VECTOR_ELT instruction.  In this case, it
+  /// is necessary to spill the vector being inserted into to memory, perform
+  /// the insert there, and then read the result back.
+  SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
+                                           SDOperand Idx);
 
   /// PromoteOp - Given an operation that produces a value in an invalid type,
   /// promote it to compute the value into a larger type.  The produced value
@@ -188,29 +195,23 @@ private:
   ///
   /// If this is a legal shuffle, this method returns the (possibly promoted)
   /// build_vector Mask.  If it's not a legal shuffle, it returns null.
-  SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
+  SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const;
   
   bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
 
   void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
     
-  SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
+  SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
                           SDOperand &Hi);
-  SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
-                          SDOperand Source);
+  SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source);
 
-  SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, 
-                             MVT::ValueType DestVT);
+  SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT);
   SDOperand ExpandBUILD_VECTOR(SDNode *Node);
   SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
-  SDOperand ExpandLegalINT_TO_FP(bool isSigned,
-                                 SDOperand LegalOp,
-                                 MVT::ValueType DestVT);
-  SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
-                                  bool isSigned);
-  SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
-                                  bool isSigned);
+  SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT);
+  SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned);
+  SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned);
 
   SDOperand ExpandBSWAP(SDOperand Op);
   SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
@@ -230,8 +231,7 @@ private:
 ///
 /// Note that this will also return true for shuffles that are promoted to a
 /// different type.
-SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 
-                                             SDOperand Mask) const {
+SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
   switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
   default: return 0;
   case TargetLowering::Legal:
@@ -240,11 +240,11 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
   case TargetLowering::Promote: {
     // If this is promoted to a different type, convert the shuffle mask and
     // ask if it is legal in the promoted type!
-    MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
+    MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
 
     // If we changed # elements, change the shuffle mask.
     unsigned NumEltsGrowth =
-      MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
+      NVT.getVectorNumElements() / VT.getVectorNumElements();
     assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
     if (NumEltsGrowth > 1) {
       // Renumber the elements.
@@ -312,8 +312,7 @@ static void ComputeTopDownOrdering(SelectionDAG &DAG,
   }
 
   assert(Order.size() == Visited.size() &&
-         Order.size() == 
-         (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
+         Order.size() == DAG.allnodes_size() &&
          "Error: DAG is cyclic!");
 }
 
@@ -450,20 +449,20 @@ bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
 /// HandleOp - Legalize, Promote, or Expand the specified operand as
 /// appropriate for its type.
 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
-  MVT::ValueType VT = Op.getValueType();
+  MVT VT = Op.getValueType();
   switch (getTypeAction(VT)) {
   default: assert(0 && "Bad type action!");
   case Legal:   (void)LegalizeOp(Op); break;
   case Promote: (void)PromoteOp(Op); break;
   case Expand:
-    if (!MVT::isVector(VT)) {
+    if (!VT.isVector()) {
       // If this is an illegal scalar, expand it into its two component
       // pieces.
       SDOperand X, Y;
       if (Op.getOpcode() == ISD::TargetConstant)
         break;  // Allow illegal target nodes.
       ExpandOp(Op, X, Y);
-    } else if (MVT::getVectorNumElements(VT) == 1) {
+    } else if (VT.getVectorNumElements() == 1) {
       // If this is an illegal single element vector, convert it to a
       // scalar operation.
       (void)ScalarizeVectorOp(Op);
@@ -489,9 +488,8 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
   // double.  This shrinks FP constants and canonicalizes them for targets where
   // an FP extending load is the same cost as a normal load (such as on the x87
   // fp stack or PPC FP unit).
-  MVT::ValueType VT = CFP->getValueType(0);
-  ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
-                                      CFP->getValueAPF());
+  MVT VT = CFP->getValueType(0);
+  ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
   if (!UseCP) {
     if (VT!=MVT::f64 && VT!=MVT::f32)
       assert(0 && "Invalid type expansion");
@@ -499,16 +497,16 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
                            (VT == MVT::f64) ? MVT::i64 : MVT::i32);
   }
 
-  MVT::ValueType OrigVT = VT;
-  MVT::ValueType SVT = VT;
+  MVT OrigVT = VT;
+  MVT SVT = VT;
   while (SVT != MVT::f32) {
-    SVT = (unsigned)SVT - 1;
+    SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
     if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
         // Only do this if the target has a native EXTLOAD instruction from
         // smaller type.
         TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
         TLI.ShouldShrinkFPConstant(OrigVT)) {
-      const Type *SType = MVT::getTypeForValueType(SVT);
+      const Type *SType = SVT.getTypeForMVT();
       LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
       VT = SVT;
       Extend = true;
@@ -528,13 +526,13 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
 /// operations.
 static
-SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
+SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
                                       SelectionDAG &DAG, TargetLowering &TLI) {
-  MVT::ValueType VT = Node->getValueType(0);
-  MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
+  MVT VT = Node->getValueType(0);
+  MVT SrcVT = Node->getOperand(1).getValueType();
   assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
          "fcopysign expansion only supported for f32 and f64");
-  MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
+  MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
 
   // First get the sign bit of second operand.
   SDOperand Mask1 = (SrcVT == MVT::f64)
@@ -544,13 +542,16 @@ SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
   SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
   SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
   // Shift right or sign-extend it if the two operands have different types.
-  int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
+  int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
   if (SizeDiff > 0) {
     SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
                           DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
     SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
-  } else if (SizeDiff < 0)
-    SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
+  } else if (SizeDiff < 0) {
+    SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
+    SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
+                          DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
+  }
 
   // Clear the sign bit of first operand.
   SDOperand Mask2 = (VT == MVT::f64)
@@ -572,17 +573,17 @@ SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
   SDOperand Chain = ST->getChain();
   SDOperand Ptr = ST->getBasePtr();
   SDOperand Val = ST->getValue();
-  MVT::ValueType VT = Val.getValueType();
+  MVT VT = Val.getValueType();
   int Alignment = ST->getAlignment();
   int SVOffset = ST->getSrcValueOffset();
-  if (MVT::isFloatingPoint(ST->getMemoryVT()) || 
-      MVT::isVector(ST->getMemoryVT())) {
+  if (ST->getMemoryVT().isFloatingPoint() ||
+      ST->getMemoryVT().isVector()) {
     // Expand to a bitconvert of the value to the integer type of the 
     // same size, then a (misaligned) int store.
-    MVT::ValueType intVT;
-    if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
+    MVT intVT;
+    if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
       intVT = MVT::i128;
-    else if (MVT::is64BitVector(VT) || VT==MVT::f64)
+    else if (VT.is64BitVector() || VT==MVT::f64)
       intVT = MVT::i64;
     else if (VT==MVT::f32)
       intVT = MVT::i32;
@@ -593,12 +594,13 @@ SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
     return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
                         SVOffset, ST->isVolatile(), Alignment);
   }
-  assert(MVT::isInteger(ST->getMemoryVT()) &&
-         !MVT::isVector(ST->getMemoryVT()) &&
+  assert(ST->getMemoryVT().isInteger() &&
+         !ST->getMemoryVT().isVector() &&
          "Unaligned store of unknown type.");
   // Get the half-size VT
-  MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
-  int NumBits = MVT::getSizeInBits(NewStoredVT);
+  MVT NewStoredVT =
+    (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
+  int NumBits = NewStoredVT.getSizeInBits();
   int IncrementSize = NumBits / 8;
 
   // Divide the stored value in two parts.
@@ -628,16 +630,16 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
   int SVOffset = LD->getSrcValueOffset();
   SDOperand Chain = LD->getChain();
   SDOperand Ptr = LD->getBasePtr();
-  MVT::ValueType VT = LD->getValueType(0);
-  MVT::ValueType LoadedVT = LD->getMemoryVT();
-  if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) {
+  MVT VT = LD->getValueType(0);
+  MVT LoadedVT = LD->getMemoryVT();
+  if (VT.isFloatingPoint() || VT.isVector()) {
     // Expand to a (misaligned) integer load of the same size,
     // then bitconvert to floating point or vector.
-    MVT::ValueType intVT;
-    if (MVT::is128BitVector(LoadedVT) || 
+    MVT intVT;
+    if (LoadedVT.is128BitVector() ||
          LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
       intVT = MVT::i128;
-    else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
+    else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
       intVT = MVT::i64;
     else if (LoadedVT == MVT::f32)
       intVT = MVT::i32;
@@ -648,21 +650,20 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
                                     SVOffset, LD->isVolatile(), 
                                     LD->getAlignment());
     SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
-    if (MVT::isFloatingPoint(VT) && LoadedVT != VT)
+    if (VT.isFloatingPoint() && LoadedVT != VT)
       Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
 
     SDOperand Ops[] = { Result, Chain };
-    return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 
-                       Ops, 2);
+    return DAG.getMergeValues(Ops, 2);
   }
-  assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) &&
+  assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
          "Unaligned load of unsupported type.");
 
   // Compute the new VT that is half the size of the old one.  This is an
   // integer MVT.
-  unsigned NumBits = MVT::getSizeInBits(LoadedVT);
-  MVT::ValueType NewLoadedVT;
-  NewLoadedVT = MVT::getIntegerType(NumBits/2);
+  unsigned NumBits = LoadedVT.getSizeInBits();
+  MVT NewLoadedVT;
+  NewLoadedVT = MVT::getIntegerVT(NumBits/2);
   NumBits >>= 1;
   
   unsigned Alignment = LD->getAlignment();
@@ -702,7 +703,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
                              Hi.getValue(1));
 
   SDOperand Ops[] = { Result, TF };
-  return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
+  return DAG.getMergeValues(Ops, 2);
 }
 
 /// UnrollVectorOp - We know that the given vector has a legal type, however
@@ -710,23 +711,23 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
 /// no way of lowering.  "Unroll" the vector, splitting out the scalars and
 /// operating on each element individually.
 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
-  MVT::ValueType VT = Op.getValueType();
+  MVT VT = Op.getValueType();
   assert(isTypeLegal(VT) &&
          "Caller should expand or promote operands that are not legal!");
   assert(Op.Val->getNumValues() == 1 &&
          "Can't unroll a vector with multiple results!");
-  unsigned NE = MVT::getVectorNumElements(VT);
-  MVT::ValueType EltVT = MVT::getVectorElementType(VT);
+  unsigned NE = VT.getVectorNumElements();
+  MVT EltVT = VT.getVectorElementType();
 
   SmallVector<SDOperand, 8> Scalars;
   SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
   for (unsigned i = 0; i != NE; ++i) {
     for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
       SDOperand Operand = Op.getOperand(j);
-      MVT::ValueType OperandVT = Operand.getValueType();
-      if (MVT::isVector(OperandVT)) {
+      MVT OperandVT = Operand.getValueType();
+      if (OperandVT.isVector()) {
         // A vector operand; extract a single element.
-        MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
+        MVT OperandEltVT = OperandVT.getVectorElementType();
         Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
                                   OperandEltVT,
                                   Operand,
@@ -744,7 +745,7 @@ SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
 }
 
 /// GetFPLibCall - Return the right libcall for the given floating point type.
-static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
+static RTLIB::Libcall GetFPLibCall(MVT VT,
                                    RTLIB::Libcall Call_F32,
                                    RTLIB::Libcall Call_F64,
                                    RTLIB::Libcall Call_F80,
@@ -757,6 +758,50 @@ static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
     RTLIB::UNKNOWN_LIBCALL;
 }
 
+/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
+/// insertion index for the INSERT_VECTOR_ELT instruction.  In this case, it
+/// is necessary to spill the vector being inserted into to memory, perform
+/// the insert there, and then read the result back.
+SDOperand SelectionDAGLegalize::
+PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
+  SDOperand Tmp1 = Vec;
+  SDOperand Tmp2 = Val;
+  SDOperand Tmp3 = Idx;
+  
+  // If the target doesn't support this, we have to spill the input vector
+  // to a temporary stack slot, update the element, then reload it.  This is
+  // badness.  We could also load the value into a vector register (either
+  // with a "move to register" or "extload into register" instruction, then
+  // permute it into place, if the idx is a constant and if the idx is
+  // supported by the target.
+  MVT VT    = Tmp1.getValueType();
+  MVT EltVT = VT.getVectorElementType();
+  MVT IdxVT = Tmp3.getValueType();
+  MVT PtrVT = TLI.getPointerTy();
+  SDOperand StackPtr = DAG.CreateStackTemporary(VT);
+
+  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
+  int SPFI = StackPtrFI->getIndex();
+
+  // Store the vector.
+  SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
+                              PseudoSourceValue::getFixedStack(),
+                              SPFI);
+
+  // Truncate or zero extend offset to target pointer type.
+  unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
+  Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
+  // Add the offset to the index.
+  unsigned EltSize = EltVT.getSizeInBits()/8;
+  Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
+  SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
+  // Store the scalar value.
+  Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
+                         PseudoSourceValue::getFixedStack(), SPFI, EltVT);
+  // Load the updated vector.
+  return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI);
+}
+
 /// LegalizeOp - We know that the specified value has a legal type, and
 /// that its operands are legal.  Now ensure that the operation itself
 /// is legal, recursively ensuring that the operands' operations remain
@@ -783,7 +828,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
 
   // Note that LegalizeOp may be reentered even from single-use nodes, which
   // means that we always must cache transformed nodes.
-  DenseMap<SDOperandImpl, SDOperand>::iterator I = LegalizedNodes.find(Op);
+  DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
   if (I != LegalizedNodes.end()) return I->second;
 
   SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
@@ -806,7 +851,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
   case ISD::VALUETYPE:
   case ISD::SRCVALUE:
   case ISD::MEMOPERAND:
-  case ISD::STRING:
   case ISD::CONDCODE:
   case ISD::ARG_FLAGS:
     // Primitives must all be legal.
@@ -860,7 +904,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       Result = DAG.getConstant(0, TLI.getPointerTy());
     break;
   case ISD::FRAME_TO_ARGS_OFFSET: {
-    MVT::ValueType VT = Node->getValueType(0);
+    MVT VT = Node->getValueType(0);
     switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
@@ -875,7 +919,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     break;
   case ISD::EXCEPTIONADDR: {
     Tmp1 = LegalizeOp(Node->getOperand(0));
-    MVT::ValueType VT = Node->getValueType(0);
+    MVT VT = Node->getValueType(0);
     switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Expand: {
@@ -889,8 +933,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       // Fall Thru
     case TargetLowering::Legal: {
       SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
-      Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
-                           Ops, 2);
+      Result = DAG.getMergeValues(Ops, 2);
       break;
     }
     }
@@ -910,7 +953,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
   case ISD::EHSELECTION: {
     Tmp1 = LegalizeOp(Node->getOperand(0));
     Tmp2 = LegalizeOp(Node->getOperand(1));
-    MVT::ValueType VT = Node->getValueType(0);
+    MVT VT = Node->getValueType(0);
     switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Expand: {
@@ -924,8 +967,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       // Fall Thru
     case TargetLowering::Legal: {
       SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
-      Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
-                           Ops, 2);
+      Result = DAG.getMergeValues(Ops, 2);
       break;
     }
     }
@@ -943,7 +985,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     AddLegalizedOperand(Op.getValue(1), Tmp2);
     return Op.ResNo ? Tmp2 : Tmp1;
   case ISD::EH_RETURN: {
-    MVT::ValueType VT = Node->getValueType(0);
+    MVT VT = Node->getValueType(0);
     // The only "good" option for this node is to custom lower it.
     switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
     default: assert(0 && "This action is not supported at all!");
@@ -988,14 +1030,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
     return Result.getValue(Op.ResNo);
   case ISD::UNDEF: {
-    MVT::ValueType VT = Op.getValueType();
+    MVT VT = Op.getValueType();
     switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Expand:
-      if (MVT::isInteger(VT))
+      if (VT.isInteger())
         Result = DAG.getConstant(0, VT);
-      else if (MVT::isFloatingPoint(VT))
-        Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
+      else if (VT.isFloatingPoint())
+        Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
                                    VT);
       else
         assert(0 && "Unknown value type!");
@@ -1034,67 +1076,61 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     return Result.getValue(Op.ResNo);
   }    
 
-  case ISD::LOCATION:
-    assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
+  case ISD::DBG_STOPPOINT:
+    assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the input chain.
     
-    switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
+    switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
     case TargetLowering::Promote:
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Expand: {
       MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
       bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
-      bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
+      bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
       
+      const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
       if (MMI && (useDEBUG_LOC || useLABEL)) {
-        const std::string &FName =
-          cast<StringSDNode>(Node->getOperand(3))->getValue();
-        const std::string &DirName = 
-          cast<StringSDNode>(Node->getOperand(4))->getValue();
-        unsigned SrcFile = MMI->RecordSource(DirName, FName);
-
-        SmallVector<SDOperand, 8> Ops;
-        Ops.push_back(Tmp1);  // chain
-        SDOperand LineOp = Node->getOperand(1);
-        SDOperand ColOp = Node->getOperand(2);
+        const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
+        unsigned SrcFile = MMI->RecordSource(CompileUnit);
+
+        unsigned Line = DSP->getLine();
+        unsigned Col = DSP->getColumn();
         
         if (useDEBUG_LOC) {
-          Ops.push_back(LineOp);  // line #
-          Ops.push_back(ColOp);  // col #
-          Ops.push_back(DAG.getConstant(SrcFile, MVT::i32));  // source file id
-          Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
+          SDOperand Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
+                              DAG.getConstant(Col, MVT::i32),
+                              DAG.getConstant(SrcFile, MVT::i32) };
+          Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
         } else {
-          unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
-          unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
           unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
-          Ops.push_back(DAG.getConstant(ID, MVT::i32));
-          Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
-          Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
+          Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
         }
       } else {
         Result = Tmp1;  // chain
       }
       break;
     }
-    case TargetLowering::Legal:
-      if (Tmp1 != Node->getOperand(0) ||
-          getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
-        SmallVector<SDOperand, 8> Ops;
-        Ops.push_back(Tmp1);
-        if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
-          Ops.push_back(Node->getOperand(1));  // line # must be legal.
-          Ops.push_back(Node->getOperand(2));  // col # must be legal.
-        } else {
-          // Otherwise promote them.
-          Ops.push_back(PromoteOp(Node->getOperand(1)));
-          Ops.push_back(PromoteOp(Node->getOperand(2)));
-        }
-        Ops.push_back(Node->getOperand(3));  // filename must be legal.
-        Ops.push_back(Node->getOperand(4));  // working dir # must be legal.
-        Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
+    case TargetLowering::Legal: {
+      LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
+      if (Action == Legal && Tmp1 == Node->getOperand(0))
+        break;
+
+      SmallVector<SDOperand, 8> Ops;
+      Ops.push_back(Tmp1);
+      if (Action == Legal) {
+        Ops.push_back(Node->getOperand(1));  // line # must be legal.
+        Ops.push_back(Node->getOperand(2));  // col # must be legal.
+      } else {
+        // Otherwise promote them.
+        Ops.push_back(PromoteOp(Node->getOperand(1)));
+        Ops.push_back(PromoteOp(Node->getOperand(2)));
       }
+      Ops.push_back(Node->getOperand(3));  // filename must be legal.
+      Ops.push_back(Node->getOperand(4));  // working dir # must be legal.
+      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
       break;
     }
+    }
     break;
 
   case ISD::DECLARE:
@@ -1117,25 +1153,34 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
     switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
     default: assert(0 && "This action is not supported yet!");
-    case TargetLowering::Legal:
+    case TargetLowering::Legal: {
+      LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
       Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
-      Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the line #.
-      Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the col #.
-      Tmp4 = LegalizeOp(Node->getOperand(3));  // Legalize the source file id.
+      if (Action == Legal && Tmp1 == Node->getOperand(0))
+        break;
+      if (Action == Legal) {
+        Tmp2 = Node->getOperand(1);
+        Tmp3 = Node->getOperand(2);
+        Tmp4 = Node->getOperand(3);
+      } else {
+        Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the line #.
+        Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the col #.
+        Tmp4 = LegalizeOp(Node->getOperand(3));  // Legalize the source file id.
+      }
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
       break;
     }
+    }
     break;    
 
-  case ISD::LABEL:
-    assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
-    switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
+  case ISD::DBG_LABEL:
+  case ISD::EH_LABEL:
+    assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
+    switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Legal:
       Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
-      Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the label id.
-      Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the "flavor" operand.
-      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+      Result = DAG.UpdateNodeOperands(Result, Tmp1);
       break;
     case TargetLowering::Expand:
       Result = LegalizeOp(Node->getOperand(0));
@@ -1184,24 +1229,52 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     break;
   }
 
-  case ISD::ATOMIC_LCS:
-  case ISD::ATOMIC_LAS:
-  case ISD::ATOMIC_SWAP: {
-    assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
-            (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
-            (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
-           "Invalid Atomic node!");
-    int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
+  case ISD::ATOMIC_CMP_SWAP: {
+    unsigned int num_operands = 4;
+    assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
     SDOperand Ops[4];
-    for (int x = 0; x < num; ++x)
+    for (unsigned int x = 0; x < num_operands; ++x)
       Ops[x] = LegalizeOp(Node->getOperand(x));
-    Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
+    Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
     
+    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+      default: assert(0 && "This action is not supported yet!");
+      case TargetLowering::Custom:
+        Result = TLI.LowerOperation(Result, DAG);
+        break;
+      case TargetLowering::Legal:
+        break;
+    }
+    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
+    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
+    return Result.getValue(Op.ResNo);
+  }
+  case ISD::ATOMIC_LOAD_ADD:
+  case ISD::ATOMIC_LOAD_SUB:
+  case ISD::ATOMIC_LOAD_AND:
+  case ISD::ATOMIC_LOAD_OR:
+  case ISD::ATOMIC_LOAD_XOR:
+  case ISD::ATOMIC_LOAD_NAND:
+  case ISD::ATOMIC_LOAD_MIN:
+  case ISD::ATOMIC_LOAD_MAX:
+  case ISD::ATOMIC_LOAD_UMIN:
+  case ISD::ATOMIC_LOAD_UMAX:
+  case ISD::ATOMIC_SWAP: {
+    unsigned int num_operands = 3;
+    assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
+    SDOperand Ops[3];
+    for (unsigned int x = 0; x < num_operands; ++x)
+      Ops[x] = LegalizeOp(Node->getOperand(x));
+    Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
+
     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Result, DAG);
       break;
+    case TargetLowering::Expand:
+      Result = SDOperand(TLI.ReplaceNodeResults(Op.Val, DAG),0);
+      break;
     case TargetLowering::Legal:
       break;
     }
@@ -1209,7 +1282,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
     return Result.getValue(Op.ResNo);
   }
-
   case ISD::Constant: {
     ConstantSDNode *CN = cast<ConstantSDNode>(Node);
     unsigned opAction =
@@ -1377,13 +1449,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         // SCALAR_TO_VECTOR requires that the type of the value being inserted
         // match the element type of the vector being created.
         if (Tmp2.getValueType() == 
-            MVT::getVectorElementType(Op.getValueType())) {
+            Op.getValueType().getVectorElementType()) {
           SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 
                                         Tmp1.getValueType(), Tmp2);
           
-          unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
-          MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
-          MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
+          unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
+          MVT ShufMaskVT =
+            MVT::getIntVectorWithNumElements(NumElts);
+          MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
           
           // We generate a shuffle of InVec and ScVec, so the shuffle mask
           // should be 0,1,2,3,4,5... with the appropriate element replaced with
@@ -1404,40 +1477,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           break;
         }
       }
-      
-      // If the target doesn't support this, we have to spill the input vector
-      // to a temporary stack slot, update the element, then reload it.  This is
-      // badness.  We could also load the value into a vector register (either
-      // with a "move to register" or "extload into register" instruction, then
-      // permute it into place, if the idx is a constant and if the idx is
-      // supported by the target.
-      MVT::ValueType VT    = Tmp1.getValueType();
-      MVT::ValueType EltVT = MVT::getVectorElementType(VT);
-      MVT::ValueType IdxVT = Tmp3.getValueType();
-      MVT::ValueType PtrVT = TLI.getPointerTy();
-      SDOperand StackPtr = DAG.CreateStackTemporary(VT);
-
-      FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
-      int SPFI = StackPtrFI->getIndex();
-
-      // Store the vector.
-      SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
-                                  PseudoSourceValue::getFixedStack(),
-                                  SPFI);
-
-      // Truncate or zero extend offset to target pointer type.
-      unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
-      Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
-      // Add the offset to the index.
-      unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
-      Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
-      SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
-      // Store the scalar value.
-      Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
-                             PseudoSourceValue::getFixedStack(), SPFI, EltVT);
-      // Load the updated vector.
-      Result = DAG.getLoad(VT, Ch, StackPtr,
-                           PseudoSourceValue::getFixedStack(), SPFI);
+      Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
       break;
     }
     }
@@ -1487,9 +1527,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       }
       // FALLTHROUGH
     case TargetLowering::Expand: {
-      MVT::ValueType VT = Node->getValueType(0);
-      MVT::ValueType EltVT = MVT::getVectorElementType(VT);
-      MVT::ValueType PtrVT = TLI.getPointerTy();
+      MVT VT = Node->getValueType(0);
+      MVT EltVT = VT.getVectorElementType();
+      MVT PtrVT = TLI.getPointerTy();
       SDOperand Mask = Node->getOperand(2);
       unsigned NumElems = Mask.getNumOperands();
       SmallVector<SDOperand,8> Ops;
@@ -1513,8 +1553,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     }
     case TargetLowering::Promote: {
       // Change base type to a different vector type.
-      MVT::ValueType OVT = Node->getValueType(0);
-      MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+      MVT OVT = Node->getValueType(0);
+      MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
 
       // Cast the two input vectors.
       Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
@@ -1584,7 +1624,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     // process, no libcalls can/will be inserted, guaranteeing that no calls
     // can overlap.
     assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
-    SDOperand InCallSEQ = LastCALLSEQ_END;
     // Note that we are selecting this call!
     LastCALLSEQ_END = SDOperand(CallEnd, 0);
     IsLegalizingCall = true;
@@ -1599,7 +1638,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     // will cause this node to be legalized as well as handling libcalls right.
     if (LastCALLSEQ_END.Val != Node) {
       LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
-      DenseMap<SDOperandImpl, SDOperand>::iterator I = LegalizedNodes.find(Op);
+      DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
       assert(I != LegalizedNodes.end() &&
              "Legalizing the call start should have legalized this node!");
       return I->second;
@@ -1636,7 +1675,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
     return Result.getValue(Op.ResNo);
   case ISD::DYNAMIC_STACKALLOC: {
-    MVT::ValueType VT = Node->getValueType(0);
+    MVT VT = Node->getValueType(0);
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the size.
     Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the alignment.
@@ -1777,7 +1816,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       SDOperand Table = Result.getOperand(1);
       SDOperand Index = Result.getOperand(2);
 
-      MVT::ValueType PTy = TLI.getPointerTy();
+      MVT PTy = TLI.getPointerTy();
       MachineFunction &MF = DAG.getMachineFunction();
       unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
       Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
@@ -1896,7 +1935,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
 
     ISD::LoadExtType ExtType = LD->getExtensionType();
     if (ExtType == ISD::NON_EXTLOAD) {
-      MVT::ValueType VT = Node->getValueType(0);
+      MVT VT = Node->getValueType(0);
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
       Tmp3 = Result.getValue(0);
       Tmp4 = Result.getValue(1);
@@ -1908,7 +1947,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         // expand it.
         if (!TLI.allowsUnalignedMemoryAccesses()) {
           unsigned ABIAlignment = TLI.getTargetData()->
-            getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
+            getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
           if (LD->getAlignment() < ABIAlignment){
             Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
                                          TLI);
@@ -1928,9 +1967,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         break;
       case TargetLowering::Promote: {
         // Only promote a load of vector type to another.
-        assert(MVT::isVector(VT) && "Cannot promote this load!");
+        assert(VT.isVector() && "Cannot promote this load!");
         // Change base type to a different vector type.
-        MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
+        MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
 
         Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
                            LD->getSrcValueOffset(),
@@ -1946,13 +1985,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
       return Op.ResNo ? Tmp4 : Tmp3;
     } else {
-      MVT::ValueType SrcVT = LD->getMemoryVT();
-      unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
+      MVT SrcVT = LD->getMemoryVT();
+      unsigned SrcWidth = SrcVT.getSizeInBits();
       int SVOffset = LD->getSrcValueOffset();
       unsigned Alignment = LD->getAlignment();
       bool isVolatile = LD->isVolatile();
 
-      if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
+      if (SrcWidth != SrcVT.getStoreSizeInBits() &&
           // Some targets pretend to have an i1 loading operation, and actually
           // load an i8.  This trick is correct for ZEXTLOAD because the top 7
           // bits are guaranteed to be zero; it helps the optimizers understand
@@ -1964,8 +2003,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
            TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
         // Promote to a byte-sized load if not loading an integral number of
         // bytes.  For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
-        unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
-        MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
+        unsigned NewWidth = SrcVT.getStoreSizeInBits();
+        MVT NVT = MVT::getIntegerVT(NewWidth);
         SDOperand Ch;
 
         // The extra bits are guaranteed to be zero, since we stored them that
@@ -1993,7 +2032,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         Tmp2 = LegalizeOp(Ch);
       } else if (SrcWidth & (SrcWidth - 1)) {
         // If not loading a power-of-2 number of bits, expand as two loads.
-        assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
+        assert(SrcVT.isExtended() && !SrcVT.isVector() &&
                "Unsupported extload!");
         unsigned RoundWidth = 1 << Log2_32(SrcWidth);
         assert(RoundWidth < SrcWidth);
@@ -2001,8 +2040,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         assert(ExtraWidth < RoundWidth);
         assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
                "Load size not an integral number of bytes!");
-        MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
-        MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
+        MVT RoundVT = MVT::getIntegerVT(RoundWidth);
+        MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
         SDOperand Lo, Hi, Ch;
         unsigned IncrementSize;
 
@@ -2087,7 +2126,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
             // expand it.
             if (!TLI.allowsUnalignedMemoryAccesses()) {
               unsigned ABIAlignment = TLI.getTargetData()->
-                getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
+                getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
               if (LD->getAlignment() < ABIAlignment){
                 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
                                              TLI);
@@ -2137,14 +2176,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     }
   }
   case ISD::EXTRACT_ELEMENT: {
-    MVT::ValueType OpTy = Node->getOperand(0).getValueType();
+    MVT OpTy = Node->getOperand(0).getValueType();
     switch (getTypeAction(OpTy)) {
     default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
     case Legal:
       if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
         // 1 -> Hi
         Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
-                             DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 
+                             DAG.getConstant(OpTy.getSizeInBits()/2,
                                              TLI.getShiftAmountTy()));
         Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
       } else {
@@ -2209,7 +2248,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
         break;
       case Expand:
-        if (!MVT::isVector(Tmp2.getValueType())) {
+        if (!Tmp2.getValueType().isVector()) {
           SDOperand Lo, Hi;
           ExpandOp(Tmp2, Lo, Hi);
 
@@ -2225,12 +2264,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         } else {
           SDNode *InVal = Tmp2.Val;
           int InIx = Tmp2.ResNo;
-          unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
-          MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
+          unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
+          MVT EVT = InVal->getValueType(InIx).getVectorElementType();
           
           // Figure out if there is a simple type corresponding to this Vector
           // type.  If so, convert to the vector type.
-          MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+          MVT TVT = MVT::getVectorVT(EVT, NumElems);
           if (TLI.isTypeLegal(TVT)) {
             // Turn this into a return of the vector type.
             Tmp2 = LegalizeOp(Tmp2);
@@ -2278,7 +2317,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           break;
         case Expand: {
           SDOperand Lo, Hi;
-          assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
+          assert(!Node->getOperand(i).getValueType().isExtended() &&
                  "FIXME: TODO: implement returning non-legal vector types!");
           ExpandOp(Node->getOperand(i), Lo, Hi);
           NewValues.push_back(Lo);
@@ -2346,7 +2385,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
             Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
                                   SVOffset, isVolatile, Alignment);
             break;
-          } else if (getTypeAction(MVT::i32) == Legal) {
+          } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
             // Otherwise, if the target supports 32-bit registers, use 2 32-bit
             // stores.  If the target supports neither 32- nor 64-bits, this
             // xform is certainly not worth it.
@@ -2374,7 +2413,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 
                                         ST->getOffset());
 
-        MVT::ValueType VT = Tmp3.getValueType();
+        MVT VT = Tmp3.getValueType();
         switch (TLI.getOperationAction(ISD::STORE, VT)) {
         default: assert(0 && "This action is not supported yet!");
         case TargetLowering::Legal:
@@ -2382,7 +2421,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           // expand it.
           if (!TLI.allowsUnalignedMemoryAccesses()) {
             unsigned ABIAlignment = TLI.getTargetData()->
-              getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
+              getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
             if (ST->getAlignment() < ABIAlignment)
               Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
                                             TLI);
@@ -2393,7 +2432,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           if (Tmp1.Val) Result = Tmp1;
           break;
         case TargetLowering::Promote:
-          assert(MVT::isVector(VT) && "Unknown legal promote case!");
+          assert(VT.isVector() && "Unknown legal promote case!");
           Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 
                              TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
           Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
@@ -2418,16 +2457,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         // If this is a vector type, then we have to calculate the increment as
         // the product of the element size in bytes, and the number of elements
         // in the high half of the vector.
-        if (MVT::isVector(ST->getValue().getValueType())) {
+        if (ST->getValue().getValueType().isVector()) {
           SDNode *InVal = ST->getValue().Val;
           int InIx = ST->getValue().ResNo;
-          MVT::ValueType InVT = InVal->getValueType(InIx);
-          unsigned NumElems = MVT::getVectorNumElements(InVT);
-          MVT::ValueType EVT = MVT::getVectorElementType(InVT);
+          MVT InVT = InVal->getValueType(InIx);
+          unsigned NumElems = InVT.getVectorNumElements();
+          MVT EVT = InVT.getVectorElementType();
 
           // Figure out if there is a simple type corresponding to this Vector
           // type.  If so, convert to the vector type.
-          MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+          MVT TVT = MVT::getVectorVT(EVT, NumElems);
           if (TLI.isTypeLegal(TVT)) {
             // Turn this into a normal store of the vector type.
             Tmp3 = LegalizeOp(ST->getValue());
@@ -2446,12 +2485,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
             break;
           } else {
             SplitVectorOp(ST->getValue(), Lo, Hi);
-            IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 
-                            MVT::getSizeInBits(EVT)/8;
+            IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
+                            EVT.getSizeInBits()/8;
           }
         } else {
           ExpandOp(ST->getValue(), Lo, Hi);
-          IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
+          IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
 
           if (TLI.isBigEndian())
             std::swap(Lo, Hi);
@@ -2494,20 +2533,20 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
                                  SVOffset, MVT::i8, isVolatile, Alignment);
       }
 
-      MVT::ValueType StVT = ST->getMemoryVT();
-      unsigned StWidth = MVT::getSizeInBits(StVT);
+      MVT StVT = ST->getMemoryVT();
+      unsigned StWidth = StVT.getSizeInBits();
 
-      if (StWidth != MVT::getStoreSizeInBits(StVT)) {
+      if (StWidth != StVT.getStoreSizeInBits()) {
         // Promote to a byte-sized store with upper bits zero if not
         // storing an integral number of bytes.  For example, promote
         // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
-        MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
+        MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
         Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
         Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
                                    SVOffset, NVT, isVolatile, Alignment);
       } else if (StWidth & (StWidth - 1)) {
         // If not storing a power-of-2 number of bits, expand as two stores.
-        assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
+        assert(StVT.isExtended() && !StVT.isVector() &&
                "Unsupported truncstore!");
         unsigned RoundWidth = 1 << Log2_32(StWidth);
         assert(RoundWidth < StWidth);
@@ -2515,8 +2554,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         assert(ExtraWidth < RoundWidth);
         assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
                "Store size not an integral number of bytes!");
-        MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
-        MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
+        MVT RoundVT = MVT::getIntegerVT(RoundWidth);
+        MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
         SDOperand Lo, Hi;
         unsigned IncrementSize;
 
@@ -2569,7 +2608,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           // expand it.
           if (!TLI.allowsUnalignedMemoryAccesses()) {
             unsigned ABIAlignment = TLI.getTargetData()->
-              getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
+              getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
             if (ST->getAlignment() < ABIAlignment)
               Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
                                             TLI);
@@ -2718,13 +2757,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       }
       break;
     case TargetLowering::Promote: {
-      MVT::ValueType NVT =
+      MVT NVT =
         TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
       unsigned ExtOp, TruncOp;
-      if (MVT::isVector(Tmp2.getValueType())) {
+      if (Tmp2.getValueType().isVector()) {
         ExtOp   = ISD::BIT_CONVERT;
         TruncOp = ISD::BIT_CONVERT;
-      } else if (MVT::isInteger(Tmp2.getValueType())) {
+      } else if (Tmp2.getValueType().isInteger()) {
         ExtOp   = ISD::ANY_EXTEND;
         TruncOp = ISD::TRUNCATE;
       } else {
@@ -2804,23 +2843,23 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       // First step, figure out the appropriate operation to use.
       // Allow SETCC to not be supported for all legal data types
       // Mostly this targets FP
-      MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
-      MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
+      MVT NewInTy = Node->getOperand(0).getValueType();
+      MVT OldVT = NewInTy; OldVT = OldVT;
 
       // Scan for the appropriate larger type to use.
       while (1) {
-        NewInTy = (MVT::ValueType)(NewInTy+1);
+        NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
 
-        assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
+        assert(NewInTy.isInteger() == OldVT.isInteger() &&
                "Fell off of the edge of the integer world");
-        assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
+        assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
                "Fell off of the edge of the floating point world");
           
         // If the target supports SETCC of this type, use it.
         if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
           break;
       }
-      if (MVT::isInteger(NewInTy))
+      if (NewInTy.isInteger())
         assert(0 && "Cannot promote Legal Integer SETCC yet");
       else {
         Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
@@ -2835,128 +2874,29 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     case TargetLowering::Expand:
       // Expand a setcc node into a select_cc of the same condition, lhs, and
       // rhs that selects between const 1 (true) and const 0 (false).
-      MVT::ValueType VT = Node->getValueType(0);
+      MVT VT = Node->getValueType(0);
       Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 
                            DAG.getConstant(1, VT), DAG.getConstant(0, VT),
                            Tmp3);
       break;
     }
     break;
-  case ISD::MEMSET:
-  case ISD::MEMCPY:
-  case ISD::MEMMOVE: {
-    Tmp1 = LegalizeOp(Node->getOperand(0));      // Chain
-    Tmp2 = LegalizeOp(Node->getOperand(1));      // Pointer
-
-    if (Node->getOpcode() == ISD::MEMSET) {      // memset = ubyte
-      switch (getTypeAction(Node->getOperand(2).getValueType())) {
-      case Expand: assert(0 && "Cannot expand a byte!");
-      case Legal:
-        Tmp3 = LegalizeOp(Node->getOperand(2));
-        break;
-      case Promote:
-        Tmp3 = PromoteOp(Node->getOperand(2));
-        break;
-      }
-    } else {
-      Tmp3 = LegalizeOp(Node->getOperand(2));    // memcpy/move = pointer,
-    }
-
-    SDOperand Tmp4;
-    switch (getTypeAction(Node->getOperand(3).getValueType())) {
-    case Expand: {
-      // Length is too big, just take the lo-part of the length.
-      SDOperand HiPart;
-      ExpandOp(Node->getOperand(3), Tmp4, HiPart);
-      break;
-    }
-    case Legal:
-      Tmp4 = LegalizeOp(Node->getOperand(3));
-      break;
-    case Promote:
-      Tmp4 = PromoteOp(Node->getOperand(3));
-      break;
-    }
-
-    SDOperand Tmp5;
-    switch (getTypeAction(Node->getOperand(4).getValueType())) {  // uint
-    case Expand: assert(0 && "Cannot expand this yet!");
-    case Legal:
-      Tmp5 = LegalizeOp(Node->getOperand(4));
-      break;
-    case Promote:
-      Tmp5 = PromoteOp(Node->getOperand(4));
-      break;
-    }
-
-    SDOperand Tmp6;
-    switch (getTypeAction(Node->getOperand(5).getValueType())) {  // bool
-    case Expand: assert(0 && "Cannot expand this yet!");
-    case Legal:
-      Tmp6 = LegalizeOp(Node->getOperand(5));
-      break;
-    case Promote:
-      Tmp6 = PromoteOp(Node->getOperand(5));
-      break;
-    }
+  case ISD::VSETCC: {
+    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
+    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
+    SDOperand CC = Node->getOperand(2);
+    
+    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
 
-    switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
-    default: assert(0 && "This action not implemented for this operation!");
+    // Everything is legal, see if we should expand this op or something.
+    switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
+    default: assert(0 && "This action is not supported yet!");
+    case TargetLowering::Legal: break;
     case TargetLowering::Custom:
-      isCustom = true;
-      // FALLTHROUGH
-    case TargetLowering::Legal: {
-      SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
-      Result = DAG.UpdateNodeOperands(Result, Ops, 6);
-      if (isCustom) {
-        Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
-      }
-      break;
-    }
-    case TargetLowering::Expand: {
-      // Otherwise, the target does not support this operation.  Lower the
-      // operation to an explicit libcall as appropriate.
-      MVT::ValueType IntPtr = TLI.getPointerTy();
-      const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
-      TargetLowering::ArgListTy Args;
-      TargetLowering::ArgListEntry Entry;
-
-      const char *FnName = 0;
-      if (Node->getOpcode() == ISD::MEMSET) {
-        Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
-        Args.push_back(Entry);
-        // Extend the (previously legalized) ubyte argument to be an int value
-        // for the call.
-        if (Tmp3.getValueType() > MVT::i32)
-          Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
-        else
-          Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
-        Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
-        Args.push_back(Entry);
-        Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
-        Args.push_back(Entry);
-
-        FnName = "memset";
-      } else if (Node->getOpcode() == ISD::MEMCPY ||
-                 Node->getOpcode() == ISD::MEMMOVE) {
-        Entry.Ty = IntPtrTy;
-        Entry.Node = Tmp2; Args.push_back(Entry);
-        Entry.Node = Tmp3; Args.push_back(Entry);
-        Entry.Node = Tmp4; Args.push_back(Entry);
-        FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
-      } else {
-        assert(0 && "Unknown op!");
-      }
-
-      std::pair<SDOperand,SDOperand> CallResult =
-        TLI.LowerCallTo(Tmp1, Type::VoidTy,
-                        false, false, false, CallingConv::C, false,
-                        DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
-      Result = CallResult.second;
+      Tmp1 = TLI.LowerOperation(Result, DAG);
+      if (Tmp1.Val) Result = Tmp1;
       break;
     }
-    }
     break;
   }
 
@@ -3039,7 +2979,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       if (Tmp1.Val) Result = Tmp1;
       break;
     case TargetLowering::Expand: {
-      MVT::ValueType VT = Op.getValueType();
+      MVT VT = Op.getValueType();
  
       // See if multiply or divide can be lowered using two-result operations.
       SDVTList VTs = DAG.getVTList(VT, VT);
@@ -3108,11 +3048,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       }
       if (LC != RTLIB::UNKNOWN_LIBCALL) {
         SDOperand Dummy;
-        Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
+        Result = ExpandLibCall(LC, Node, isSigned, Dummy);
         break;
       }
 
-      assert(MVT::isVector(Node->getValueType(0)) &&
+      assert(Node->getValueType(0).isVector() &&
              "Cannot expand this binary operator!");
       // Expand the operation into a bunch of nasty scalar code.
       Result = LegalizeOp(UnrollVectorOp(Op));
@@ -3124,9 +3064,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       case ISD::AND:
       case ISD::OR:
       case ISD::XOR: {
-        MVT::ValueType OVT = Node->getValueType(0);
-        MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
-        assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
+        MVT OVT = Node->getValueType(0);
+        MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+        assert(OVT.isVector() && "Cannot promote this BinOp!");
         // Bit convert each of the values to the new type.
         Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
         Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
@@ -3184,7 +3124,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
           TargetLowering::Legal) {
         // Get the sign bit of the RHS.
-        MVT::ValueType IVT = 
+        MVT IVT =
           Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
         SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
         SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
@@ -3202,7 +3142,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       }
       
       // Otherwise, do bitwise ops!
-      MVT::ValueType NVT = 
+      MVT NVT =
         Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
       Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
       Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
@@ -3236,7 +3176,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     return Result;
     
   case ISD::BUILD_PAIR: {
-    MVT::ValueType PairTy = Node->getValueType(0);
+    MVT PairTy = Node->getValueType(0);
     // TODO: handle the case where the Lo and Hi operands are not of legal type
     Tmp1 = LegalizeOp(Node->getOperand(0));   // Lo
     Tmp2 = LegalizeOp(Node->getOperand(1));   // Hi
@@ -3252,7 +3192,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
       Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
       Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
-                         DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 
+                         DAG.getConstant(PairTy.getSizeInBits()/2,
                                          TLI.getShiftAmountTy()));
       Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
       break;
@@ -3281,7 +3221,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     case TargetLowering::Expand: {
       unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
       bool isSigned = DivOpc == ISD::SDIV;
-      MVT::ValueType VT = Node->getValueType(0);
+      MVT VT = Node->getValueType(0);
  
       // See if remainder can be lowered using two-result operations.
       SDVTList VTs = DAG.getVTList(VT, VT);
@@ -3296,14 +3236,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         break;
       }
 
-      if (MVT::isInteger(VT)) {
+      if (VT.isInteger()) {
         if (TLI.getOperationAction(DivOpc, VT) ==
             TargetLowering::Legal) {
           // X % Y -> X-X/Y*Y
           Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
           Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
           Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
-        } else if (MVT::isVector(VT)) {
+        } else if (VT.isVector()) {
           Result = LegalizeOp(UnrollVectorOp(Op));
         } else {
           assert(VT == MVT::i32 &&
@@ -3311,20 +3251,19 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
           RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
             ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
           SDOperand Dummy;
-          Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
+          Result = ExpandLibCall(LC, Node, isSigned, Dummy);
         }
       } else {
-        assert(MVT::isFloatingPoint(VT) &&
+        assert(VT.isFloatingPoint() &&
                "remainder op must have integer or floating-point type");
-        if (MVT::isVector(VT)) {
+        if (VT.isVector()) {
           Result = LegalizeOp(UnrollVectorOp(Op));
         } else {
           // Floating point mod -> fmod libcall.
           RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
                                            RTLIB::REM_F80, RTLIB::REM_PPCF128);
           SDOperand Dummy;
-          Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
-                                 false/*sign irrelevant*/, Dummy);
+          Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
         }
       }
       break;
@@ -3335,7 +3274,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
     Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
 
-    MVT::ValueType VT = Node->getValueType(0);
+    MVT VT = Node->getValueType(0);
     switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
@@ -3359,7 +3298,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
       // Increment the pointer, VAList, to the next vaarg
       Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 
-                         DAG.getConstant(MVT::getSizeInBits(VT)/8, 
+                         DAG.getConstant(VT.getSizeInBits()/8,
                                          TLI.getPointerTy()));
       // Store the incremented VAList to the legalized pointer
       Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
@@ -3400,8 +3339,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       // output, returning the chain.
       const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
       const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
-      Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
-      Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
+      Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
+      Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
       break;
     }
     break;
@@ -3477,9 +3416,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       Result = DAG.UpdateNodeOperands(Result, Tmp1);
       break;
     case TargetLowering::Promote: {
-      MVT::ValueType OVT = Tmp1.getValueType();
-      MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
-      unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
+      MVT OVT = Tmp1.getValueType();
+      MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+      unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
 
       Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
       Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
@@ -3510,8 +3449,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       }
       break;
     case TargetLowering::Promote: {
-      MVT::ValueType OVT = Tmp1.getValueType();
-      MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+      MVT OVT = Tmp1.getValueType();
+      MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
 
       // Zero extend the argument.
       Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
@@ -3524,16 +3463,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       case ISD::CTTZ:
         //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
         Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
-                            DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
+                            DAG.getConstant(NVT.getSizeInBits(), NVT),
                             ISD::SETEQ);
         Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
-                             DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
+                             DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
         break;
       case ISD::CTLZ:
         // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
         Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
-                             DAG.getConstant(MVT::getSizeInBits(NVT) -
-                                             MVT::getSizeInBits(OVT), NVT));
+                             DAG.getConstant(NVT.getSizeInBits() -
+                                             OVT.getSizeInBits(), NVT));
         break;
       }
       break;
@@ -3573,7 +3512,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         break;
       case ISD::FABS: {
         // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
-        MVT::ValueType VT = Node->getValueType(0);
+        MVT VT = Node->getValueType(0);
         Tmp2 = DAG.getConstantFP(0.0, VT);
         Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
                             ISD::SETUGT);
@@ -3584,10 +3523,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       case ISD::FSQRT:
       case ISD::FSIN:
       case ISD::FCOS: {
-        MVT::ValueType VT = Node->getValueType(0);
+        MVT VT = Node->getValueType(0);
 
         // Expand unsupported unary vector operators by unrolling them.
-        if (MVT::isVector(VT)) {
+        if (VT.isVector()) {
           Result = LegalizeOp(UnrollVectorOp(Op));
           break;
         }
@@ -3609,8 +3548,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         default: assert(0 && "Unreachable!");
         }
         SDOperand Dummy;
-        Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
-                               false/*sign irrelevant*/, Dummy);
+        Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
         break;
       }
       }
@@ -3618,10 +3556,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     }
     break;
   case ISD::FPOWI: {
-    MVT::ValueType VT = Node->getValueType(0);
+    MVT VT = Node->getValueType(0);
 
     // Expand unsupported unary vector operators by unrolling them.
-    if (MVT::isVector(VT)) {
+    if (VT.isVector()) {
       Result = LegalizeOp(UnrollVectorOp(Op));
       break;
     }
@@ -3630,25 +3568,24 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
                                      RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
     SDOperand Dummy;
-    Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
-                           false/*sign irrelevant*/, Dummy);
+    Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
     break;
   }
   case ISD::BIT_CONVERT:
     if (!isTypeLegal(Node->getOperand(0).getValueType())) {
       Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
                                 Node->getValueType(0));
-    } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
+    } else if (Op.getOperand(0).getValueType().isVector()) {
       // The input has to be a vector type, we have to either scalarize it, pack
       // it, or convert it based on whether the input vector type is legal.
       SDNode *InVal = Node->getOperand(0).Val;
       int InIx = Node->getOperand(0).ResNo;
-      unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
-      MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
+      unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
+      MVT EVT = InVal->getValueType(InIx).getVectorElementType();
     
       // Figure out if there is a simple type corresponding to this Vector
       // type.  If so, convert to the vector type.
-      MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+      MVT TVT = MVT::getVectorVT(EVT, NumElems);
       if (TLI.isTypeLegal(TVT)) {
         // Turn this into a bit convert of the vector input.
         Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 
@@ -3775,11 +3712,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       case TargetLowering::Expand:
         if (Node->getOpcode() == ISD::FP_TO_UINT) {
           SDOperand True, False;
-          MVT::ValueType VT =  Node->getOperand(0).getValueType();
-          MVT::ValueType NVT = Node->getValueType(0);
+          MVT VT =  Node->getOperand(0).getValueType();
+          MVT NVT = Node->getValueType(0);
           const uint64_t zero[] = {0, 0};
-          APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
-          APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
+          APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
+          APInt x = APInt::getSignBit(NVT.getSizeInBits());
           (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
           Tmp2 = DAG.getConstantFP(apf, VT);
           Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
@@ -3799,8 +3736,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       }
       break;
     case Expand: {
-      MVT::ValueType VT = Op.getValueType();
-      MVT::ValueType OVT = Node->getOperand(0).getValueType();
+      MVT VT = Op.getValueType();
+      MVT OVT = Node->getOperand(0).getValueType();
       // Convert ppcf128 to i32
       if (OVT == MVT::ppcf128 && VT == MVT::i32) {
         if (Node->getOpcode() == ISD::FP_TO_SINT) {
@@ -3836,6 +3773,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
             LC = RTLIB::FPTOSINT_F32_I32;
           else if (OVT == MVT::f64)
             LC = RTLIB::FPTOSINT_F64_I32;
+          else if (OVT == MVT::f80)
+            LC = RTLIB::FPTOSINT_F80_I32;
+          else if (OVT == MVT::ppcf128)
+            LC = RTLIB::FPTOSINT_PPCF128_I32;
           else
             assert(0 && "Unexpected i32-to-fp conversion!");
         } else if (VT == MVT::i64) {
@@ -3905,8 +3846,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       default: assert(0 && "Unreachable!");
       }
       SDOperand Dummy;
-      Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
-                             false/*sign irrelevant*/, Dummy);
+      Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
       break;
     }
     case Promote:
@@ -3918,8 +3858,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     break;
 
   case ISD::FP_EXTEND: {
-    MVT::ValueType DstVT = Op.getValueType();
-    MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
+    MVT DstVT = Op.getValueType();
+    MVT SrcVT = Op.getOperand(0).getValueType();
     if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
       // The only other way we can lower this is to turn it into a STORE,
       // LOAD pair, targetting a temporary location (a stack slot).
@@ -3940,8 +3880,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     break;
   }
   case ISD::FP_ROUND: {
-    MVT::ValueType DstVT = Op.getValueType();
-    MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
+    MVT DstVT = Op.getValueType();
+    MVT SrcVT = Op.getOperand(0).getValueType();
     if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
       if (SrcVT == MVT::ppcf128) {
         SDOperand Lo;
@@ -3977,14 +3917,12 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     case Expand: assert(0 && "Shouldn't need to expand other operators here!");
     case Legal:
       Tmp1 = LegalizeOp(Node->getOperand(0));
+      Result = DAG.UpdateNodeOperands(Result, Tmp1);
       if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
           TargetLowering::Custom) {
-        Tmp2 = TLI.LowerOperation(Result, DAG);
-        if (Tmp2.Val) {
-          Tmp1 = Tmp2;
-        }
+        Tmp1 = TLI.LowerOperation(Result, DAG);
+        if (Tmp1.Val) Result = Tmp1;
       }
-      Result = DAG.UpdateNodeOperands(Result, Tmp1);
       break;
     case Promote:
       switch (Node->getOpcode()) {
@@ -4011,7 +3949,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
   case ISD::FP_ROUND_INREG:
   case ISD::SIGN_EXTEND_INREG: {
     Tmp1 = LegalizeOp(Node->getOperand(0));
-    MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
+    MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
 
     // If this operation is not supported, convert it to a shl/shr or load/store
     // pair.
@@ -4025,8 +3963,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
         // NOTE: we could fall back on load/store here too for targets without
         // SAR.  However, it is doubtful that any exist.
-        unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
-                            MVT::getSizeInBits(ExtraVT);
+        unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
+                            ExtraVT.getSizeInBits();
         SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
         Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
                              Node->getOperand(0), ShiftCst);
@@ -4065,8 +4003,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
     return Op.ResNo ? Tmp1 : Result;
   }
-   case ISD::FLT_ROUNDS_: {
-    MVT::ValueType VT = Node->getValueType(0);
+  case ISD::FLT_ROUNDS_: {
+    MVT VT = Node->getValueType(0);
     switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
     default: assert(0 && "This action not supported for this op yet!");
     case TargetLowering::Custom:
@@ -4078,9 +4016,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
       Result = DAG.getConstant(1, VT);
       break;
     }
+    break;
   }
   case ISD::TRAP: {
-    MVT::ValueType VT = Node->getValueType(0);
+    MVT VT = Node->getValueType(0);
     switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
     default: assert(0 && "This action not supported for this op yet!");
     case TargetLowering::Legal:
@@ -4125,18 +4064,18 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
 /// have the correct bits for the low portion of the register, but no guarantee
 /// is made about the top bits: it may be zero, sign-extended, or garbage.
 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
-  MVT::ValueType VT = Op.getValueType();
-  MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
+  MVT VT = Op.getValueType();
+  MVT NVT = TLI.getTypeToTransformTo(VT);
   assert(getTypeAction(VT) == Promote &&
          "Caller should expand or legalize operands that are not promotable!");
-  assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
+  assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
          "Cannot promote to smaller type!");
 
   SDOperand Tmp1, Tmp2, Tmp3;
   SDOperand Result;
   SDNode *Node = Op.Val;
 
-  DenseMap<SDOperandImpl, SDOperand>::iterator I = PromotedNodes.find(Op);
+  DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
   if (I != PromotedNodes.end()) return I->second;
 
   switch (Node->getOpcode()) {
@@ -4176,9 +4115,9 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     switch (getTypeAction(Node->getOperand(0).getValueType())) {
     case Legal:
       Result = LegalizeOp(Node->getOperand(0));
-      assert(Result.getValueType() >= NVT &&
+      assert(Result.getValueType().bitsGE(NVT) &&
              "This truncation doesn't make sense!");
-      if (Result.getValueType() > NVT)    // Truncate to NVT instead of VT
+      if (Result.getValueType().bitsGT(NVT))    // Truncate to NVT instead of VT
         Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
       break;
     case Promote:
@@ -4336,22 +4275,35 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     break;
   }
     
-  case ISD::ATOMIC_LCS: {
+  case ISD::ATOMIC_CMP_SWAP: {
+    AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
     Tmp2 = PromoteOp(Node->getOperand(2));
     Tmp3 = PromoteOp(Node->getOperand(3));
-    Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 
-                           Node->getOperand(1), Tmp2, Tmp3,
-                           cast<AtomicSDNode>(Node)->getVT());
+    Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 
+                           AtomNode->getBasePtr(), Tmp2, Tmp3,
+                           AtomNode->getSrcValue(),
+                           AtomNode->getAlignment());
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
     break;
   }
-  case ISD::ATOMIC_LAS:
+  case ISD::ATOMIC_LOAD_ADD:
+  case ISD::ATOMIC_LOAD_SUB:
+  case ISD::ATOMIC_LOAD_AND:
+  case ISD::ATOMIC_LOAD_OR:
+  case ISD::ATOMIC_LOAD_XOR:
+  case ISD::ATOMIC_LOAD_NAND:
+  case ISD::ATOMIC_LOAD_MIN:
+  case ISD::ATOMIC_LOAD_MAX:
+  case ISD::ATOMIC_LOAD_UMIN:
+  case ISD::ATOMIC_LOAD_UMAX:
   case ISD::ATOMIC_SWAP: {
+    AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
     Tmp2 = PromoteOp(Node->getOperand(2));
-    Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 
-                           Node->getOperand(1), Tmp2,
-                           cast<AtomicSDNode>(Node)->getVT());
+    Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 
+                           AtomNode->getBasePtr(), Tmp2,
+                           AtomNode->getSrcValue(),
+                           AtomNode->getAlignment());
     // Remember that we legalized the chain.
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
     break;
@@ -4394,7 +4346,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     // These operators require that their input be sign extended.
     Tmp1 = PromoteOp(Node->getOperand(0));
     Tmp2 = PromoteOp(Node->getOperand(1));
-    if (MVT::isInteger(NVT)) {
+    if (NVT.isInteger()) {
       Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
                          DAG.getValueType(VT));
       Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
@@ -4403,7 +4355,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
 
     // Perform FP_ROUND: this is probably overly pessimistic.
-    if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
+    if (NVT.isFloatingPoint() && NoExcessFPPrecision)
       Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
                            DAG.getValueType(VT));
     break;
@@ -4434,7 +4386,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     // These operators require that their input be zero extended.
     Tmp1 = PromoteOp(Node->getOperand(0));
     Tmp2 = PromoteOp(Node->getOperand(1));
-    assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
+    assert(NVT.isInteger() && "Operators don't apply to FP!");
     Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
     Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
     Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
@@ -4463,13 +4415,13 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     Tmp2 = Node->getOperand(1);   // Get the pointer.
     if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
       Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
-      Result = TLI.CustomPromoteOperation(Tmp3, DAG);
+      Result = TLI.LowerOperation(Tmp3, DAG);
     } else {
       const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
       SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
       // Increment the pointer, VAList, to the next vaarg
       Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 
-                         DAG.getConstant(MVT::getSizeInBits(VT)/8, 
+                         DAG.getConstant(VT.getSizeInBits()/8,
                                          TLI.getPointerTy()));
       // Store the incremented VAList to the legalized pointer
       Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
@@ -4494,11 +4446,19 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
     break;
   }
-  case ISD::SELECT:
+  case ISD::SELECT: {
     Tmp2 = PromoteOp(Node->getOperand(1));   // Legalize the op0
     Tmp3 = PromoteOp(Node->getOperand(2));   // Legalize the op1
-    Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
+
+    MVT VT2 = Tmp2.getValueType();
+    assert(VT2 == Tmp3.getValueType()
+           && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
+    // Ensure that the resulting node is at least the same size as the operands'
+    // value types, because we cannot assume that TLI.getSetCCValueType() is
+    // constant.
+    Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
     break;
+  }
   case ISD::SELECT_CC:
     Tmp2 = PromoteOp(Node->getOperand(2));   // True
     Tmp3 = PromoteOp(Node->getOperand(3));   // False
@@ -4510,8 +4470,8 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
     Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
     Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
-                         DAG.getConstant(MVT::getSizeInBits(NVT) -
-                                         MVT::getSizeInBits(VT),
+                         DAG.getConstant(NVT.getSizeInBits() -
+                                         VT.getSizeInBits(),
                                          TLI.getShiftAmountTy()));
     break;
   case ISD::CTPOP:
@@ -4528,16 +4488,16 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
     case ISD::CTTZ:
       // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
       Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
-                          DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
+                          DAG.getConstant(NVT.getSizeInBits(), NVT),
                           ISD::SETEQ);
       Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
-                           DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
+                           DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
       break;
     case ISD::CTLZ:
       //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
       Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
-                           DAG.getConstant(MVT::getSizeInBits(NVT) -
-                                           MVT::getSizeInBits(VT), NVT));
+                           DAG.getConstant(NVT.getSizeInBits() -
+                                           VT.getSizeInBits(), NVT));
       break;
     }
     break;
@@ -4570,8 +4530,8 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
   SDOperand Vec = Op.getOperand(0);
   SDOperand Idx = Op.getOperand(1);
   
-  MVT::ValueType TVT = Vec.getValueType();
-  unsigned NumElems = MVT::getVectorNumElements(TVT);
+  MVT TVT = Vec.getValueType();
+  unsigned NumElems = TVT.getVectorNumElements();
   
   switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
   default: assert(0 && "This action is not supported yet!");
@@ -4620,12 +4580,11 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
     SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
 
     // Add the offset to the index.
-    unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
+    unsigned EltSize = Op.getValueType().getSizeInBits()/8;
     Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
                       DAG.getConstant(EltSize, Idx.getValueType()));
 
-    if (MVT::getSizeInBits(Idx.getValueType()) >
-        MVT::getSizeInBits(TLI.getPointerTy()))
+    if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
       Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
     else
       Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
@@ -4645,9 +4604,9 @@ SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
   SDOperand Vec = Op.getOperand(0);
   SDOperand Idx = LegalizeOp(Op.getOperand(1));
   
-  unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
+  unsigned NumElems = Vec.getValueType().getVectorNumElements();
   
-  if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
+  if (NumElems == Op.getValueType().getVectorNumElements()) {
     // This must be an access of the desired vector length.  Return it.
     return Vec;
   }
@@ -4688,9 +4647,9 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
     Tmp2 = PromoteOp(RHS);   // RHS
 
     // If this is an FP compare, the operands have already been extended.
-    if (MVT::isInteger(LHS.getValueType())) {
-      MVT::ValueType VT = LHS.getValueType();
-      MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
+    if (LHS.getValueType().isInteger()) {
+      MVT VT = LHS.getValueType();
+      MVT NVT = TLI.getTypeToTransformTo(VT);
 
       // Otherwise, we have to insert explicit sign or zero extends.  Note
       // that we could insert sign extends for ALL conditions, but zero extend
@@ -4723,10 +4682,10 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
     }
     break;
   case Expand: {
-    MVT::ValueType VT = LHS.getValueType();
+    MVT VT = LHS.getValueType();
     if (VT == MVT::f32 || VT == MVT::f64) {
       // Expand into one or more soft-fp libcall(s).
-      RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
+      RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
       switch (cast<CondCodeSDNode>(CC)->get()) {
       case ISD::SETEQ:
       case ISD::SETOEQ:
@@ -4783,25 +4742,24 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
         default: assert(0 && "Unsupported FP setcc!");
         }
       }
-      
+
       SDOperand Dummy;
-      Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
-                           DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 
+      SDOperand Ops[2] = { LHS, RHS };
+      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
                            false /*sign irrelevant*/, Dummy);
       Tmp2 = DAG.getConstant(0, MVT::i32);
       CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
       if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
         Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
                            CC);
-        LHS = ExpandLibCall(TLI.getLibcallName(LC2),
-                            DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 
+        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
                             false /*sign irrelevant*/, Dummy);
         Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
                            DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
         Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
         Tmp2 = SDOperand();
       }
-      LHS = Tmp1;
+      LHS = LegalizeOp(Tmp1);
       RHS = Tmp2;
       return;
     }
@@ -4926,38 +4884,44 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
 /// a load from the stack slot to DestVT, extending it if needed.
 /// The resultant code need not be legal.
 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
-                                                 MVT::ValueType SlotVT, 
-                                                 MVT::ValueType DestVT) {
+                                                 MVT SlotVT,
+                                                 MVT DestVT) {
   // Create the stack frame object.
-  SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
-
+  unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
+                                          SrcOp.getValueType().getTypeForMVT());
+  SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
+  
   FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
   int SPFI = StackPtrFI->getIndex();
-
-  unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
-  unsigned SlotSize = MVT::getSizeInBits(SlotVT);
-  unsigned DestSize = MVT::getSizeInBits(DestVT);
+  
+  unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
+  unsigned SlotSize = SlotVT.getSizeInBits();
+  unsigned DestSize = DestVT.getSizeInBits();
+  unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
+                                                        DestVT.getTypeForMVT());
   
   // Emit a store to the stack slot.  Use a truncstore if the input value is
   // later than DestVT.
   SDOperand Store;
+  
   if (SrcSize > SlotSize)
     Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
-                              PseudoSourceValue::getFixedStack(),
-                              SPFI, SlotVT);
+                              PseudoSourceValue::getFixedStack(), SPFI, SlotVT, 
+                              false, SrcAlign);
   else {
     assert(SrcSize == SlotSize && "Invalid store");
     Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
-                         PseudoSourceValue::getFixedStack(),
-                         SPFI, SlotVT);
+                         PseudoSourceValue::getFixedStack(), SPFI,
+                         false, SrcAlign);
   }
   
   // Result is a load from the stack slot.
   if (SlotSize == DestSize)
-    return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
+    return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
   
   assert(SlotSize < DestSize && "Unknown extension!");
-  return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
+  return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
+                        false, DestAlign);
 }
 
 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
@@ -5020,19 +4984,19 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
   
   // If all elements are constants, create a load from the constant pool.
   if (isConstant) {
-    MVT::ValueType VT = Node->getValueType(0);
-    const Type *OpNTy = 
-      MVT::getTypeForValueType(Node->getOperand(0).getValueType());
+    MVT VT = Node->getValueType(0);
     std::vector<Constant*> CV;
     for (unsigned i = 0, e = NumElems; i != e; ++i) {
       if (ConstantFPSDNode *V = 
           dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
-        CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
+        CV.push_back(ConstantFP::get(V->getValueAPF()));
       } else if (ConstantSDNode *V = 
-                 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
-        CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
+                   dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
+        CV.push_back(ConstantInt::get(V->getAPIntValue()));
       } else {
         assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
+        const Type *OpNTy = 
+          Node->getOperand(0).getValueType().getTypeForMVT();
         CV.push_back(UndefValue::get(OpNTy));
       }
     }
@@ -5044,9 +5008,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
   
   if (SplatValue.Val) {   // Splat of one value?
     // Build the shuffle constant vector: <0, 0, 0, 0>
-    MVT::ValueType MaskVT = 
-      MVT::getIntVectorWithNumElements(NumElems);
-    SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
+    MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
+    SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
     std::vector<SDOperand> ZeroVec(NumElems, Zero);
     SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
                                       &ZeroVec[0], ZeroVec.size());
@@ -5082,8 +5045,8 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
       std::swap(Val1, Val2);
     
     // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
-    MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
-    MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT);
+    MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
+    MVT MaskEltVT = MaskVT.getVectorElementType();
     std::vector<SDOperand> MaskVec(NumElems);
 
     // Set elements of the shuffle mask for Val1.
@@ -5117,14 +5080,13 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
   // Otherwise, we can't handle this case efficiently.  Allocate a sufficiently
   // aligned object on the stack, store each element into it, then load
   // the result as a vector.
-  MVT::ValueType VT = Node->getValueType(0);
+  MVT VT = Node->getValueType(0);
   // Create the stack frame object.
   SDOperand FIPtr = DAG.CreateStackTemporary(VT);
   
   // Emit a store of each element to the stack slot.
   SmallVector<SDOperand, 8> Stores;
-  unsigned TypeByteSize = 
-    MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
+  unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
   // Store (in the right endianness) the elements to memory.
   for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
     // Ignore undef elements.
@@ -5158,7 +5120,7 @@ void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
   ExpandOp(Op, LHSL, LHSH);
 
   SDOperand Ops[] = { LHSL, LHSH, Amt };
-  MVT::ValueType VT = LHSL.getValueType();
+  MVT VT = LHSL.getValueType();
   Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
   Hi = Lo.getValue(1);
 }
@@ -5173,12 +5135,12 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
   assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
          "This is not a shift!");
 
-  MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
+  MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
   SDOperand ShAmt = LegalizeOp(Amt);
-  MVT::ValueType ShTy = ShAmt.getValueType();
-  unsigned ShBits = MVT::getSizeInBits(ShTy);
-  unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
-  unsigned NVTBits = MVT::getSizeInBits(NVT);
+  MVT ShTy = ShAmt.getValueType();
+  unsigned ShBits = ShTy.getSizeInBits();
+  unsigned VTBits = Op.getValueType().getSizeInBits();
+  unsigned NVTBits = NVT.getSizeInBits();
 
   // Handle the case when Amt is an immediate.
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
@@ -5318,7 +5280,7 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
 // does not fit into a register, return the lo part and set the hi part to the
 // by-reg argument.  If it does fit into a single register, return the result
 // and leave the Hi part unset.
-SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
+SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
                                               bool isSigned, SDOperand &Hi) {
   assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   // The input chain to this libcall is the entry node of the function. 
@@ -5329,17 +5291,18 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
   TargetLowering::ArgListTy Args;
   TargetLowering::ArgListEntry Entry;
   for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
-    MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
-    const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
+    MVT ArgVT = Node->getOperand(i).getValueType();
+    const Type *ArgTy = ArgVT.getTypeForMVT();
     Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 
     Entry.isSExt = isSigned;
     Entry.isZExt = !isSigned;
     Args.push_back(Entry);
   }
-  SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
+  SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
+                                           TLI.getPointerTy());
 
   // Splice the libcall in wherever FindInputOutputChains tells us to.
-  const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
+  const Type *RetTy = Node->getValueType(0).getTypeForMVT();
   std::pair<SDOperand,SDOperand> CallInfo =
     TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
                     false, Callee, Args, DAG);
@@ -5365,11 +5328,12 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
 ///
 SDOperand SelectionDAGLegalize::
-ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
-  MVT::ValueType SourceVT = Source.getValueType();
+ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) {
+  MVT SourceVT = Source.getValueType();
   bool ExpandSource = getTypeAction(SourceVT) == Expand;
 
-  if (!isSigned) {
+  // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
+  if (!isSigned && SourceVT != MVT::i32) {
     // The integer value loaded will be incorrectly if the 'sign bit' of the
     // incoming integer is set.  To handle this, we dynamically test to see if
     // it is set, and, if so, add a fudge factor.
@@ -5403,7 +5367,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
     if (DestTy == MVT::f32)
       FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
                                PseudoSourceValue::getConstantPool(), 0);
-    else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
+    else if (DestTy.bitsGT(MVT::f32))
       // FIXME: Avoid the extend by construction the right constantpool?
       FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
                                   CPIdx,
@@ -5412,12 +5376,12 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
     else 
       assert(0 && "Unexpected conversion");
 
-    MVT::ValueType SCVT = SignedConv.getValueType();
+    MVT SCVT = SignedConv.getValueType();
     if (SCVT != DestTy) {
       // Destination type needs to be expanded as well. The FADD now we are
       // constructing will be expanded into a libcall.
-      if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
-        assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy));
+      if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
+        assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
         SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
                                  SignedConv, SignedConv.getValue(1));
       }
@@ -5486,8 +5450,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
   assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
   Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
   SDOperand HiPart;
-  SDOperand Result = ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
-                                   HiPart);
+  SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
   if (Result.getValueType() != DestTy && HiPart.Val)
     Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
   return Result;
@@ -5499,7 +5462,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
 /// legal for the target.
 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
                                                      SDOperand Op0,
-                                                     MVT::ValueType DestVT) {
+                                                     MVT DestVT) {
   if (Op0.getValueType() == MVT::i32) {
     // simple 32-bit [signed|unsigned] integer to float/double expansion
     
@@ -5545,10 +5508,10 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
     if (DestVT == MVT::f64) {
       // do nothing
       Result = Sub;
-    } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
+    } else if (DestVT.bitsLT(MVT::f64)) {
       Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
                            DAG.getIntPtrConstant(0));
-    } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
+    } else if (DestVT.bitsGT(MVT::f64)) {
       Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
     }
     return Result;
@@ -5567,7 +5530,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   // as a negative number.  To counteract this, the dynamic code adds an
   // offset depending on the data type.
   uint64_t FF;
-  switch (Op0.getValueType()) {
+  switch (Op0.getValueType().getSimpleVT()) {
   default: assert(0 && "Unsupported integer type!");
   case MVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
   case MVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
@@ -5600,17 +5563,17 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
 /// operation that takes a larger input.
 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
-                                                      MVT::ValueType DestVT,
+                                                      MVT DestVT,
                                                       bool isSigned) {
   // First step, figure out the appropriate *INT_TO_FP operation to use.
-  MVT::ValueType NewInTy = LegalOp.getValueType();
+  MVT NewInTy = LegalOp.getValueType();
 
   unsigned OpToUse = 0;
 
   // Scan for the appropriate larger type to use.
   while (1) {
-    NewInTy = (MVT::ValueType)(NewInTy+1);
-    assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
+    NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
+    assert(NewInTy.isInteger() && "Ran out of possibilities!");
 
     // If the target supports SINT_TO_FP of this type, use it.
     switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
@@ -5655,17 +5618,17 @@ SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
 /// operation that returns a larger result.
 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
-                                                      MVT::ValueType DestVT,
+                                                      MVT DestVT,
                                                       bool isSigned) {
   // First step, figure out the appropriate FP_TO*INT operation to use.
-  MVT::ValueType NewOutTy = DestVT;
+  MVT NewOutTy = DestVT;
 
   unsigned OpToUse = 0;
 
   // Scan for the appropriate larger type to use.
   while (1) {
-    NewOutTy = (MVT::ValueType)(NewOutTy+1);
-    assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
+    NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
+    assert(NewOutTy.isInteger() && "Ran out of possibilities!");
 
     // If the target supports FP_TO_SINT returning this type, use it.
     switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
@@ -5699,15 +5662,15 @@ SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
   
   // Okay, we found the operation and type to use.
   SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
-  
+
   // If the operation produces an invalid type, it must be custom lowered.  Use
   // the target lowering hooks to expand it.  Just keep the low part of the
   // expanded operation, we know that we're truncating anyway.
   if (getTypeAction(NewOutTy) == Expand) {
-    Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
+    Operation = SDOperand(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
     assert(Operation.Val && "Didn't return anything");
   }
-  
+
   // Truncate the result of the extended FP_TO_*INT operation to the desired
   // size.
   return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
@@ -5716,10 +5679,10 @@ SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
 ///
 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
-  MVT::ValueType VT = Op.getValueType();
-  MVT::ValueType SHVT = TLI.getShiftAmountTy();
+  MVT VT = Op.getValueType();
+  MVT SHVT = TLI.getShiftAmountTy();
   SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
-  switch (VT) {
+  switch (VT.getSimpleVT()) {
   default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
   case MVT::i16:
     Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
@@ -5771,9 +5734,9 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
       0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
       0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
     };
-    MVT::ValueType VT = Op.getValueType();
-    MVT::ValueType ShVT = TLI.getShiftAmountTy();
-    unsigned len = MVT::getSizeInBits(VT);
+    MVT VT = Op.getValueType();
+    MVT ShVT = TLI.getShiftAmountTy();
+    unsigned len = VT.getSizeInBits();
     for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
       //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
       SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
@@ -5794,9 +5757,9 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
     // return popcount(~x);
     //
     // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
-    MVT::ValueType VT = Op.getValueType();
-    MVT::ValueType ShVT = TLI.getShiftAmountTy();
-    unsigned len = MVT::getSizeInBits(VT);
+    MVT VT = Op.getValueType();
+    MVT ShVT = TLI.getShiftAmountTy();
+    unsigned len = VT.getSizeInBits();
     for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
       SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
       Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
@@ -5809,7 +5772,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
     // unless the target has ctlz but not ctpop, in which case we use:
     // { return 32 - nlz(~x & (x-1)); }
     // see also http://www.hackersdelight.org/HDcode/ntz.cc
-    MVT::ValueType VT = Op.getValueType();
+    MVT VT = Op.getValueType();
     SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
     SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
                        DAG.getNode(ISD::XOR, VT, Op, Tmp2),
@@ -5818,7 +5781,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
     if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
         TLI.isOperationLegal(ISD::CTLZ, VT))
       return DAG.getNode(ISD::SUB, VT,
-                         DAG.getConstant(MVT::getSizeInBits(VT), VT),
+                         DAG.getConstant(VT.getSizeInBits(), VT),
                          DAG.getNode(ISD::CTLZ, VT, Tmp3));
     return DAG.getNode(ISD::CTPOP, VT, Tmp3);
   }
@@ -5831,16 +5794,15 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
 /// ExpandedNodes map is filled in for any results that are expanded, and the
 /// Lo/Hi values are returned.
 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
-  MVT::ValueType VT = Op.getValueType();
-  MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
+  MVT VT = Op.getValueType();
+  MVT NVT = TLI.getTypeToTransformTo(VT);
   SDNode *Node = Op.Val;
   assert(getTypeAction(VT) == Expand && "Not an expanded type!");
-  assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
-         MVT::isVector(VT)) &&
-         "Cannot expand to FP value or to larger int value!");
+  assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
+         VT.isVector()) && "Cannot expand to FP value or to larger int value!");
 
   // See if we already expanded it.
-  DenseMap<SDOperandImpl, std::pair<SDOperand, SDOperand> >::iterator I
+  DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
     = ExpandedNodes.find(Op);
   if (I != ExpandedNodes.end()) {
     Lo = I->second.first;
@@ -5883,12 +5845,11 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     Lo  = ExpandEXTRACT_VECTOR_ELT(Op);
     return ExpandOp(Lo, Lo, Hi);
   case ISD::UNDEF:
-    NVT = TLI.getTypeToExpandTo(VT);
     Lo = DAG.getNode(ISD::UNDEF, NVT);
     Hi = DAG.getNode(ISD::UNDEF, NVT);
     break;
   case ISD::Constant: {
-    unsigned NVTBits = MVT::getSizeInBits(NVT);
+    unsigned NVTBits = NVT.getSizeInBits();
     const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
     Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
     Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
@@ -5937,7 +5898,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     // The high part gets the sign extension from the lo-part.  This handles
     // things like sextinreg V:i64 from i8.
     Hi = DAG.getNode(ISD::SRA, NVT, Lo,
-                     DAG.getConstant(MVT::getSizeInBits(NVT)-1,
+                     DAG.getConstant(NVT.getSizeInBits()-1,
                                      TLI.getShiftAmountTy()));
     break;
 
@@ -5960,7 +5921,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
   case ISD::CTLZ: {
     // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
     ExpandOp(Node->getOperand(0), Lo, Hi);
-    SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
+    SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
     SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
     SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
                                         ISD::SETNE);
@@ -5975,7 +5936,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
   case ISD::CTTZ: {
     // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
     ExpandOp(Node->getOperand(0), Lo, Hi);
-    SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
+    SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
     SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
     SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
                                         ISD::SETNE);
@@ -6024,7 +5985,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
       }
 
       // Increment the pointer to the other half.
-      unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
+      unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
       Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
                         DAG.getIntPtrConstant(IncrementSize));
       SVOffset += IncrementSize;
@@ -6042,7 +6003,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
       if (TLI.isBigEndian())
         std::swap(Lo, Hi);
     } else {
-      MVT::ValueType EVT = LD->getMemoryVT();
+      MVT EVT = LD->getMemoryVT();
 
       if ((VT == MVT::f64 && EVT == MVT::f32) ||
           (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
@@ -6069,7 +6030,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
       if (ExtType == ISD::SEXTLOAD) {
         // The high part is obtained by SRA'ing all but one of the bits of the
         // lo part.
-        unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
+        unsigned LoSize = Lo.getValueType().getSizeInBits();
         Hi = DAG.getNode(ISD::SRA, NVT, Lo,
                          DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
       } else if (ExtType == ISD::ZEXTLOAD) {
@@ -6129,7 +6090,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
 
     // The high part is obtained by SRA'ing all but one of the bits of the lo
     // part.
-    unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
+    unsigned LoSize = Lo.getValueType().getSizeInBits();
     Hi = DAG.getNode(ISD::SRA, NVT, Lo,
                      DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
     break;
@@ -6178,7 +6139,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
 
     // If source operand will be expanded to the same type as VT, i.e.
     // i64 <- f64, i32 <- f32, expand the source operand instead.
-    MVT::ValueType VT0 = Node->getOperand(0).getValueType();
+    MVT VT0 = Node->getOperand(0).getValueType();
     if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
       ExpandOp(Node->getOperand(0), Lo, Hi);
       break;
@@ -6204,7 +6165,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     break;
   }
 
-  case ISD::ATOMIC_LCS: {
+  case ISD::ATOMIC_CMP_SWAP: {
     SDOperand Tmp = TLI.LowerOperation(Op, DAG);
     assert(Tmp.Val && "Node must be custom expanded!");
     ExpandOp(Tmp.getValue(0), Lo, Hi);
@@ -6246,8 +6207,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
         LC = RTLIB::FPTOSINT_F80_I64;
       else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
         LC = RTLIB::FPTOSINT_PPCF128_I64;
-      Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
-                         false/*sign irrelevant*/, Hi);
+      Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
     } else if (VT == MVT::i128) {
       if (Node->getOperand(0).getValueType() == MVT::f32)
         LC = RTLIB::FPTOSINT_F32_I128;
@@ -6257,8 +6217,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
         LC = RTLIB::FPTOSINT_F80_I128;
       else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
         LC = RTLIB::FPTOSINT_PPCF128_I128;
-      Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
-                         false/*sign irrelevant*/, Hi);
+      Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
     } else {
       assert(0 && "Unexpected uint-to-fp conversion!");
     }
@@ -6293,8 +6252,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
         LC = RTLIB::FPTOUINT_F80_I64;
       else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
         LC = RTLIB::FPTOUINT_PPCF128_I64;
-      Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
-                         false/*sign irrelevant*/, Hi);
+      Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
     } else if (VT == MVT::i128) {
       if (Node->getOperand(0).getValueType() == MVT::f32)
         LC = RTLIB::FPTOUINT_F32_I128;
@@ -6304,8 +6262,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
         LC = RTLIB::FPTOUINT_F80_I128;
       else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
         LC = RTLIB::FPTOUINT_PPCF128_I128;
-      Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
-                         false/*sign irrelevant*/, Hi);
+      Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
     } else {
       assert(0 && "Unexpected uint-to-fp conversion!");
     }
@@ -6358,8 +6315,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     }
 
     // Otherwise, emit a libcall.
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
-                       false/*left shift=unsigned*/, Hi);
+    Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
     break;
   }
 
@@ -6391,8 +6347,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     }
 
     // Otherwise, emit a libcall.
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
-                       true/*ashr is signed*/, Hi);
+    Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
     break;
   }
 
@@ -6424,8 +6379,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     }
 
     // Otherwise, emit a libcall.
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
-                       false/*lshr is unsigned*/, Hi);
+    Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
     break;
   }
 
@@ -6434,9 +6388,9 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     // If the target wants to custom expand this, let them.
     if (TLI.getOperationAction(Node->getOpcode(), VT) ==
             TargetLowering::Custom) {
-      Op = TLI.LowerOperation(Op, DAG);
-      if (Op.Val) {
-        ExpandOp(Op, Lo, Hi);
+      SDOperand Result = TLI.LowerOperation(Op, DAG);
+      if (Result.Val) {
+        ExpandOp(Result, Lo, Hi);
         break;
       }
     }
@@ -6582,49 +6536,48 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
     }
 
     // If nothing else, we can make a libcall.
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
-                       false/*sign irrelevant*/, Hi);
+    Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
     break;
   }
   case ISD::SDIV:
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
+    Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
     break;
   case ISD::UDIV:
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
+    Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
     break;
   case ISD::SREM:
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
+    Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
     break;
   case ISD::UREM:
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
+    Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
     break;
 
   case ISD::FADD:
-    Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
-                                                       RTLIB::ADD_F64,
-                                                       RTLIB::ADD_F80,
-                                                       RTLIB::ADD_PPCF128)),
+    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
+                                        RTLIB::ADD_F64,
+                                        RTLIB::ADD_F80,
+                                        RTLIB::ADD_PPCF128),
                        Node, false, Hi);
     break;
   case ISD::FSUB:
-    Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
-                                                       RTLIB::SUB_F64,
-                                                       RTLIB::SUB_F80,
-                                                       RTLIB::SUB_PPCF128)),
+    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
+                                        RTLIB::SUB_F64,
+                                        RTLIB::SUB_F80,
+                                        RTLIB::SUB_PPCF128),
                        Node, false, Hi);
     break;
   case ISD::FMUL:
-    Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
-                                                       RTLIB::MUL_F64,
-                                                       RTLIB::MUL_F80,
-                                                       RTLIB::MUL_PPCF128)),
+    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
+                                        RTLIB::MUL_F64,
+                                        RTLIB::MUL_F80,
+                                        RTLIB::MUL_PPCF128),
                        Node, false, Hi);
     break;
   case ISD::FDIV:
-    Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
-                                                       RTLIB::DIV_F64,
-                                                       RTLIB::DIV_F80,
-                                                       RTLIB::DIV_PPCF128)),
+    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
+                                        RTLIB::DIV_F64,
+                                        RTLIB::DIV_F80,
+                                        RTLIB::DIV_PPCF128),
                        Node, false, Hi);
     break;
   case ISD::FP_EXTEND:
@@ -6639,16 +6592,16 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
       Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
       break;
     }
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
+    Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi);
     break;
   case ISD::FP_ROUND:
-    Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
+    Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi);
     break;
   case ISD::FPOWI:
-    Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
-                                                       RTLIB::POWI_F64,
-                                                       RTLIB::POWI_F80,
-                                                       RTLIB::POWI_PPCF128)),
+    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
+                                        RTLIB::POWI_F64,
+                                        RTLIB::POWI_F80,
+                                        RTLIB::POWI_PPCF128),
                        Node, false, Hi);
     break;
   case ISD::FSQRT:
@@ -6670,7 +6623,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
       break;
     default: assert(0 && "Unreachable!");
     }
-    Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
+    Lo = ExpandLibCall(LC, Node, false, Hi);
     break;
   }
   case ISD::FABS: {
@@ -6720,7 +6673,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP: {
     bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
-    MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
+    MVT SrcVT = Node->getOperand(0).getValueType();
 
     // Promote the operand if needed.  Do this before checking for
     // ppcf128 so conversions of i16 and i8 work.
@@ -6797,7 +6750,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
   }
 
   // Remember in a map if the values will be reused later.
-  bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
+  bool isNew =
+    ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
   assert(isNew && "Value already expanded?!?");
 }
 
@@ -6805,18 +6759,18 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
 /// two smaller values, still of vector type.
 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
                                          SDOperand &Hi) {
-  assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
+  assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
   SDNode *Node = Op.Val;
-  unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
+  unsigned NumElements = Op.getValueType().getVectorNumElements();
   assert(NumElements > 1 && "Cannot split a single element vector!");
 
-  MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
+  MVT NewEltVT = Op.getValueType().getVectorElementType();
 
   unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
   unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
 
-  MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
-  MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
+  MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
+  MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
 
   // See if we already split it.
   std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
@@ -6842,22 +6796,29 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
     Hi = Node->getOperand(1);
     break;
   case ISD::INSERT_VECTOR_ELT: {
-    SplitVectorOp(Node->getOperand(0), Lo, Hi);
-    unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
-    SDOperand ScalarOp = Node->getOperand(1);
-    if (Index < NewNumElts_Lo)
-      Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
-                       DAG.getIntPtrConstant(Index));
-    else
-      Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
-                       DAG.getIntPtrConstant(Index - NewNumElts_Lo));
+    if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
+      SplitVectorOp(Node->getOperand(0), Lo, Hi);
+      unsigned Index = Idx->getValue();
+      SDOperand ScalarOp = Node->getOperand(1);
+      if (Index < NewNumElts_Lo)
+        Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
+                         DAG.getIntPtrConstant(Index));
+      else
+        Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
+                         DAG.getIntPtrConstant(Index - NewNumElts_Lo));
+      break;
+    }
+    SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
+                                                   Node->getOperand(1),
+                                                   Node->getOperand(2));
+    SplitVectorOp(Tmp, Lo, Hi);
     break;
   }
   case ISD::VECTOR_SHUFFLE: {
     // Build the low part.
     SDOperand Mask = Node->getOperand(2);
     SmallVector<SDOperand, 8> Ops;
-    MVT::ValueType PtrVT = TLI.getPointerTy();
+    MVT PtrVT = TLI.getPointerTy();
     
     // Insert all of the elements from the input that are needed.  We use 
     // buildvector of extractelement here because the input vectors will have
@@ -6932,7 +6893,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
     SplitVectorOp(Node->getOperand(1), LL, LH);
     SplitVectorOp(Node->getOperand(2), RL, RH);
 
-    if (MVT::isVector(Cond.getValueType())) {
+    if (Cond.getValueType().isVector()) {
       // Handle a vector merge.
       SDOperand CL, CH;
       SplitVectorOp(Cond, CL, CH);
@@ -6945,6 +6906,30 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
     }
     break;
   }
+  case ISD::SELECT_CC: {
+    SDOperand CondLHS = Node->getOperand(0);
+    SDOperand CondRHS = Node->getOperand(1);
+    SDOperand CondCode = Node->getOperand(4);
+    
+    SDOperand LL, LH, RL, RH;
+    SplitVectorOp(Node->getOperand(2), LL, LH);
+    SplitVectorOp(Node->getOperand(3), RL, RH);
+    
+    // Handle a simple select with vector operands.
+    Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
+                     LL, RL, CondCode);
+    Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 
+                     LH, RH, CondCode);
+    break;
+  }
+  case ISD::VSETCC: {
+    SDOperand LL, LH, RL, RH;
+    SplitVectorOp(Node->getOperand(0), LL, LH);
+    SplitVectorOp(Node->getOperand(1), RL, RH);
+    Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
+    Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
+    break;
+  }
   case ISD::ADD:
   case ISD::SUB:
   case ISD::MUL:
@@ -7006,7 +6991,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
     bool isVolatile = LD->isVolatile();
 
     Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
-    unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
+    unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8;
     Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
                       DAG.getIntPtrConstant(IncrementSize));
     SVOffset += IncrementSize;
@@ -7026,8 +7011,8 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
     // We know the result is a vector.  The input may be either a vector or a
     // scalar value.
     SDOperand InOp = Node->getOperand(0);
-    if (!MVT::isVector(InOp.getValueType()) ||
-        MVT::getVectorNumElements(InOp.getValueType()) == 1) {
+    if (!InOp.getValueType().isVector() ||
+        InOp.getValueType().getVectorNumElements() == 1) {
       // The input is a scalar or single-element vector.
       // Lower to a store/load so that it can be split.
       // FIXME: this could be improved probably.
@@ -7061,11 +7046,10 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
 /// (e.g. v1f32), convert it into the equivalent operation that returns a
 /// scalar (e.g. f32) value.
 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
-  assert(MVT::isVector(Op.getValueType()) &&
-         "Bad ScalarizeVectorOp invocation!");
+  assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
   SDNode *Node = Op.Val;
-  MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
-  assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
+  MVT NewVT = Op.getValueType().getVectorElementType();
+  assert(Op.getValueType().getVectorNumElements() == 1);
   
   // See if we already scalarized it.
   std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
@@ -7153,14 +7137,35 @@ SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
     Result = Node->getOperand(0);
     assert(Result.getValueType() == NewVT);
     break;
-  case ISD::BIT_CONVERT:
-    Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
+  case ISD::BIT_CONVERT: {
+    SDOperand Op0 = Op.getOperand(0);
+    if (Op0.getValueType().getVectorNumElements() == 1)
+      Op0 = ScalarizeVectorOp(Op0);
+    Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
     break;
+  }
   case ISD::SELECT:
     Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
                          ScalarizeVectorOp(Op.getOperand(1)),
                          ScalarizeVectorOp(Op.getOperand(2)));
     break;
+  case ISD::SELECT_CC:
+    Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 
+                         Node->getOperand(1),
+                         ScalarizeVectorOp(Op.getOperand(2)),
+                         ScalarizeVectorOp(Op.getOperand(3)),
+                         Node->getOperand(4));
+    break;
+  case ISD::VSETCC: {
+    SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
+    SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
+    Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
+                         Op.getOperand(2));
+    Result = DAG.getNode(ISD::SELECT, NewVT, Result,
+                         DAG.getConstant(-1ULL, NewVT),
+                         DAG.getConstant(0ULL, NewVT));
+    break;
+  }
   }
 
   if (TLI.isTypeLegal(NewVT))