X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FLegalizeDAG.cpp;h=4b9236db4677d43c7fb912ca631e3b1388e8207c;hb=bf304c20651b80309af4c0fb3a14c0d73eaa984f;hp=78e640f46b8fcd284163d68521966af44b29dc42;hpb=6518c6ed7ea609696304bbbe848342cacd001f12;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 78e640f46b8..4b9236db467 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -115,15 +115,14 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize { LegalizedNodes.insert(std::make_pair(To, To)); } void AddPromotedOperand(SDOperand From, SDOperand To) { - bool isNew = PromotedNodes.insert(std::make_pair(From, To)); + bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; assert(isNew && "Got into the map somehow?"); // If someone requests legalization of the new node, return itself. LegalizedNodes.insert(std::make_pair(To, To)); } public: - - SelectionDAGLegalize(SelectionDAG &DAG); + explicit SelectionDAGLegalize(SelectionDAG &DAG); /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of @@ -548,8 +547,11 @@ SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); - } else if (SizeDiff < 0) - SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); + } else if (SizeDiff < 0) { + SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); + SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, + DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); + } // Clear the sign bit of first operand. SDOperand Mask2 = (VT == MVT::f64) @@ -652,7 +654,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); SDOperand Ops[] = { Result, Chain }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); + return DAG.getMergeValues(Ops, 2); } assert(LoadedVT.isInteger() && !LoadedVT.isVector() && "Unaligned load of unsupported type."); @@ -701,7 +703,7 @@ SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, Hi.getValue(1)); SDOperand Ops[] = { Result, TF }; - return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); + return DAG.getMergeValues(Ops, 2); } /// UnrollVectorOp - We know that the given vector has a legal type, however @@ -778,13 +780,11 @@ PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { MVT PtrVT = TLI.getPointerTy(); SDOperand StackPtr = DAG.CreateStackTemporary(VT); - FrameIndexSDNode *StackPtrFI = cast(StackPtr.Val); - int SPFI = StackPtrFI->getIndex(); + int SPFI = cast(StackPtr.Val)->getIndex(); // Store the vector. SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, - PseudoSourceValue::getFixedStack(), - SPFI); + PseudoSourceValue::getFixedStack(SPFI), 0); // Truncate or zero extend offset to target pointer type. unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; @@ -795,9 +795,10 @@ PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); // Store the scalar value. Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, - PseudoSourceValue::getFixedStack(), SPFI, EltVT); + PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); // Load the updated vector. - return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI); + return DAG.getLoad(VT, Ch, StackPtr, + PseudoSourceValue::getFixedStack(SPFI), 0); } /// LegalizeOp - We know that the specified value has a legal type, and @@ -931,7 +932,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Fall Thru case TargetLowering::Legal: { SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; - Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); + Result = DAG.getMergeValues(Ops, 2); break; } } @@ -965,7 +966,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // Fall Thru case TargetLowering::Legal: { SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; - Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); + Result = DAG.getMergeValues(Ops, 2); break; } } @@ -1095,12 +1096,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { unsigned Col = DSP->getColumn(); if (useDEBUG_LOC) { - SmallVector Ops; - Ops.push_back(Tmp1); // chain - Ops.push_back(DAG.getConstant(Line, MVT::i32)); // line # - Ops.push_back(DAG.getConstant(Col, MVT::i32)); // col # - Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id - Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); + SDOperand Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), + DAG.getConstant(Col, MVT::i32), + DAG.getConstant(SrcFile, MVT::i32) }; + Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); } else { unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); @@ -1110,25 +1109,27 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; } - case TargetLowering::Legal: - if (Tmp1 != Node->getOperand(0) || - getTypeAction(Node->getOperand(1).getValueType()) == Promote) { - SmallVector Ops; - Ops.push_back(Tmp1); - if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { - Ops.push_back(Node->getOperand(1)); // line # must be legal. - Ops.push_back(Node->getOperand(2)); // col # must be legal. - } else { - // Otherwise promote them. - Ops.push_back(PromoteOp(Node->getOperand(1))); - Ops.push_back(PromoteOp(Node->getOperand(2))); - } - Ops.push_back(Node->getOperand(3)); // filename must be legal. - Ops.push_back(Node->getOperand(4)); // working dir # must be legal. - Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); + case TargetLowering::Legal: { + LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); + if (Action == Legal && Tmp1 == Node->getOperand(0)) + break; + + SmallVector Ops; + Ops.push_back(Tmp1); + if (Action == Legal) { + Ops.push_back(Node->getOperand(1)); // line # must be legal. + Ops.push_back(Node->getOperand(2)); // col # must be legal. + } else { + // Otherwise promote them. + Ops.push_back(PromoteOp(Node->getOperand(1))); + Ops.push_back(PromoteOp(Node->getOperand(2))); } + Ops.push_back(Node->getOperand(3)); // filename must be legal. + Ops.push_back(Node->getOperand(4)); // working dir # must be legal. + Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); break; } + } break; case ISD::DECLARE: @@ -1151,14 +1152,24 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Legal: + case TargetLowering::Legal: { + LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. - Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. - Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. + if (Action == Legal && Tmp1 == Node->getOperand(0)) + break; + if (Action == Legal) { + Tmp2 = Node->getOperand(1); + Tmp3 = Node->getOperand(2); + Tmp4 = Node->getOperand(3); + } else { + Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. + Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. + Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. + } Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); break; } + } break; case ISD::DBG_LABEL: @@ -1236,7 +1247,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); return Result.getValue(Op.ResNo); - } + } case ISD::ATOMIC_LOAD_ADD: case ISD::ATOMIC_LOAD_SUB: case ISD::ATOMIC_LOAD_AND: @@ -1254,14 +1265,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { for (unsigned int x = 0; x < num_operands; ++x) Ops[x] = LegalizeOp(Node->getOperand(x)); Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); - + switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Custom: Result = TLI.LowerOperation(Result, DAG); break; case TargetLowering::Expand: - Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0); + Result = SDOperand(TLI.ReplaceNodeResults(Op.Val, DAG),0); break; case TargetLowering::Legal: break; @@ -1269,7 +1280,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); return Result.getValue(Op.ResNo); - } + } case ISD::Constant: { ConstantSDNode *CN = cast(Node); unsigned opAction = @@ -3761,6 +3772,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { LC = RTLIB::FPTOSINT_F32_I32; else if (OVT == MVT::f64) LC = RTLIB::FPTOSINT_F64_I32; + else if (OVT == MVT::f80) + LC = RTLIB::FPTOSINT_F80_I32; + else if (OVT == MVT::ppcf128) + LC = RTLIB::FPTOSINT_PPCF128_I32; else assert(0 && "Unexpected i32-to-fp conversion!"); } else if (VT == MVT::i64) { @@ -4399,7 +4414,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { Tmp2 = Node->getOperand(1); // Get the pointer. if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); - Result = TLI.CustomPromoteOperation(Tmp3, DAG); + Result = TLI.LowerOperation(Tmp3, DAG); } else { const Value *V = cast(Node->getOperand(2))->getValue(); SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); @@ -4728,23 +4743,22 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, } SDOperand Dummy; - Tmp1 = ExpandLibCall(LC1, - DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, + SDOperand Ops[2] = { LHS, RHS }; + Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val, false /*sign irrelevant*/, Dummy); Tmp2 = DAG.getConstant(0, MVT::i32); CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); if (LC2 != RTLIB::UNKNOWN_LIBCALL) { Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC); - LHS = ExpandLibCall(LC2, - DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, + LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val, false /*sign irrelevant*/, Dummy); Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); Tmp2 = SDOperand(); } - LHS = Tmp1; + LHS = LegalizeOp(Tmp1); RHS = Tmp2; return; } @@ -4872,35 +4886,41 @@ SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT) { // Create the stack frame object. - SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); - + unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( + SrcOp.getValueType().getTypeForMVT()); + SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); + FrameIndexSDNode *StackPtrFI = cast(FIPtr); int SPFI = StackPtrFI->getIndex(); - + unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); unsigned SlotSize = SlotVT.getSizeInBits(); unsigned DestSize = DestVT.getSizeInBits(); + unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( + DestVT.getTypeForMVT()); // Emit a store to the stack slot. Use a truncstore if the input value is // later than DestVT. SDOperand Store; + if (SrcSize > SlotSize) Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, - PseudoSourceValue::getFixedStack(), - SPFI, SlotVT); + PseudoSourceValue::getFixedStack(SPFI), 0, + SlotVT, false, SrcAlign); else { assert(SrcSize == SlotSize && "Invalid store"); Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, - PseudoSourceValue::getFixedStack(), - SPFI); + PseudoSourceValue::getFixedStack(SPFI), 0, + false, SrcAlign); } // Result is a load from the stack slot. if (SlotSize == DestSize) - return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); + return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign); assert(SlotSize < DestSize && "Unknown extension!"); - return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); + return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT, + false, DestAlign); } SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { @@ -4912,9 +4932,9 @@ SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { int SPFI = StackPtrFI->getIndex(); SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, - PseudoSourceValue::getFixedStack(), SPFI); + PseudoSourceValue::getFixedStack(SPFI), 0); return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, - PseudoSourceValue::getFixedStack(), SPFI); + PseudoSourceValue::getFixedStack(SPFI), 0); } @@ -5641,15 +5661,15 @@ SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, // Okay, we found the operation and type to use. SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); - + // If the operation produces an invalid type, it must be custom lowered. Use // the target lowering hooks to expand it. Just keep the low part of the // expanded operation, we know that we're truncating anyway. if (getTypeAction(NewOutTy) == Expand) { - Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); + Operation = SDOperand(TLI.ReplaceNodeResults(Operation.Val, DAG), 0); assert(Operation.Val && "Didn't return anything"); } - + // Truncate the result of the extended FP_TO_*INT operation to the desired // size. return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); @@ -6729,7 +6749,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ } // Remember in a map if the values will be reused later. - bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); + bool isNew = + ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; assert(isNew && "Value already expanded?!?"); } @@ -6994,16 +7015,16 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, // The input is a scalar or single-element vector. // Lower to a store/load so that it can be split. // FIXME: this could be improved probably. - SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); - FrameIndexSDNode *FI = cast(Ptr.Val); + unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( + Op.getValueType().getTypeForMVT()); + SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); + int FI = cast(Ptr.Val)->getIndex(); SDOperand St = DAG.getStore(DAG.getEntryNode(), InOp, Ptr, - PseudoSourceValue::getFixedStack(), - FI->getIndex()); + PseudoSourceValue::getFixedStack(FI), 0); InOp = DAG.getLoad(Op.getValueType(), St, Ptr, - PseudoSourceValue::getFixedStack(), - FI->getIndex()); + PseudoSourceValue::getFixedStack(FI), 0); } // Split the vector and convert each of the pieces now. SplitVectorOp(InOp, Lo, Hi);