X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FLegalizeDAG.cpp;h=96b427bd8067a186aa383dedeffa44939798d6cd;hb=f9410141f703f4e8a6aba717617ef958249f6d13;hp=f7798945293a3b9e55ba067bc05711bc48cddac8;hpb=99a6cb92d173c142073416c81efe6d3daeb80b49;p=oota-llvm.git

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index f7798945293..96b427bd806 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -163,7 +163,7 @@ private:
 
   /// ExpandOp - Expand the specified SDValue into its two component pieces
   /// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this,
-  /// the LegalizeNodes map is filled in for any results that are not expanded,
+  /// the LegalizedNodes map is filled in for any results that are not expanded,
   /// the ExpandedNodes map is filled in for any results that are expanded, and
   /// the Lo/Hi values are returned.   This applies to integer types and Vector
   /// types.
@@ -193,6 +193,11 @@ private:
                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
 
   void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
+  void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
+  void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
+    LegalizeSetCCOperands(LHS, RHS, CC);
+    LegalizeSetCCCondCode(VT, LHS, RHS, CC);
+  }
     
   SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
                           SDValue &Hi);
@@ -249,7 +254,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
           if (InOp.getOpcode() == ISD::UNDEF)
             Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
           else {
-            unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
+            unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
             Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
           }
         }
@@ -260,7 +265,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
     break;
   }
   }
-  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
+  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
 }
 
 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
@@ -280,11 +285,10 @@ void SelectionDAGLegalize::LegalizeDAG() {
   // practice however, this causes us to run out of stack space on large basic
   // blocks.  To avoid this problem, compute an ordering of the nodes where each
   // node is only legalized after all of its operands are legalized.
-  std::vector<SDNode *> TopOrder;
-  unsigned N = DAG.AssignTopologicalOrder(TopOrder);
-  for (unsigned i = N; i != 0; --i)
-    HandleOp(SDValue(TopOrder[i-1], 0));
-  TopOrder.clear();
+  DAG.AssignTopologicalOrder();
+  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
+       E = prior(DAG.allnodes_end()); I != next(E); ++I)
+    HandleOp(SDValue(I, 0));
 
   // Finally, it's possible the root changed.  Get the new root.
   SDValue OldRoot = DAG.getRoot();
@@ -350,7 +354,7 @@ static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
   
   assert(Node->getOperand(0).getValueType() == MVT::Other &&
          "Node doesn't have a token chain argument!");
-  return FindCallStartFromCallEnd(Node->getOperand(0).Val);
+  return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
 }
 
 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
@@ -387,7 +391,7 @@ bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
   bool OperandsLeadToDest = false;
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
     OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
-      LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
+      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
 
   if (OperandsLeadToDest) {
     NodesLeadingTo.insert(N);
@@ -442,11 +446,11 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
   // an FP extending load is the same cost as a normal load (such as on the x87
   // fp stack or PPC FP unit).
   MVT VT = CFP->getValueType(0);
-  ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
+  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
   if (!UseCP) {
     if (VT!=MVT::f64 && VT!=MVT::f32)
       assert(0 && "Invalid type expansion");
-    return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
+    return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
                            (VT == MVT::f64) ? MVT::i64 : MVT::i32);
   }
 
@@ -457,7 +461,7 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
     if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
         // Only do this if the target has a native EXTLOAD instruction from
         // smaller type.
-        TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
+        TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
         TLI.ShouldShrinkFPConstant(OrigVT)) {
       const Type *SType = SVT.getTypeForMVT();
       LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
@@ -467,12 +471,13 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
   }
 
   SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
+  unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
   if (Extend)
     return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
                           CPIdx, PseudoSourceValue::getConstantPool(),
-                          0, VT);
+                          0, VT, false, Alignment);
   return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
-                     PseudoSourceValue::getConstantPool(), 0);
+                     PseudoSourceValue::getConstantPool(), 0, false, Alignment);
 }
 
 
@@ -667,7 +672,7 @@ SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
   MVT VT = Op.getValueType();
   assert(isTypeLegal(VT) &&
          "Caller should expand or promote operands that are not legal!");
-  assert(Op.Val->getNumValues() == 1 &&
+  assert(Op.getNode()->getNumValues() == 1 &&
          "Can't unroll a vector with multiple results!");
   unsigned NE = VT.getVectorNumElements();
   MVT EltVT = VT.getVectorElementType();
@@ -733,7 +738,7 @@ PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
   MVT PtrVT = TLI.getPointerTy();
   SDValue StackPtr = DAG.CreateStackTemporary(VT);
 
-  int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
+  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
 
   // Store the vector.
   SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
@@ -764,7 +769,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
   
   assert(isTypeLegal(Op.getValueType()) &&
          "Caller should expand or promote operands that are not legal!");
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
 
   // If this operation defines any values that cannot be represented in a
   // register on this target, make sure to expand or promote them.
@@ -839,7 +844,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Op, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       // FALLTHROUGH if the target doesn't want to lower this op after all.
     case TargetLowering::Legal:
       break;
@@ -850,7 +855,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     // The only option for these nodes is to custom lower them.  If the target
     // does not custom lower them, then return zero.
     Tmp1 = TLI.LowerOperation(Op, DAG);
-    if (Tmp1.Val) 
+    if (Tmp1.getNode()) 
       Result = Tmp1;
     else
       Result = DAG.getConstant(0, TLI.getPointerTy());
@@ -861,7 +866,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal:
       Result = DAG.getConstant(0, VT);
@@ -881,7 +886,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       break;
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal: {
       SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
@@ -890,9 +895,9 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     }
     }
     }
-    if (Result.Val->getNumValues() == 1) break;
+    if (Result.getNode()->getNumValues() == 1) break;
 
-    assert(Result.Val->getNumValues() == 2 &&
+    assert(Result.getNode()->getNumValues() == 2 &&
            "Cannot return more than two values!");
 
     // Since we produced two values, make sure to remember that we
@@ -915,7 +920,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       break;
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal: {
       SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
@@ -924,9 +929,9 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     }
     }
     }
-    if (Result.Val->getNumValues() == 1) break;
+    if (Result.getNode()->getNumValues() == 1) break;
 
-    assert(Result.Val->getNumValues() == 2 &&
+    assert(Result.getNode()->getNumValues() == 2 &&
            "Cannot return more than two values!");
 
     // Since we produced two values, make sure to remember that we
@@ -943,7 +948,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     default: assert(0 && "This action is not supported at all!");
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal:
       // Target does not know, how to lower this, lower to noop
@@ -1012,13 +1017,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 
         TargetLowering::Custom) {
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) Result = Tmp3;
+      if (Tmp3.getNode()) Result = Tmp3;
     }
 
-    if (Result.Val->getNumValues() == 1) break;
+    if (Result.getNode()->getNumValues() == 1) break;
 
     // Must have return value and chain result.
-    assert(Result.Val->getNumValues() == 2 &&
+    assert(Result.getNode()->getNumValues() == 2 &&
            "Cannot return more than two values!");
 
     // Since loads produce two values, make sure to remember that we 
@@ -1181,7 +1186,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     break;
   }
 
-  case ISD::ATOMIC_CMP_SWAP: {
+  case ISD::ATOMIC_CMP_SWAP_8:
+  case ISD::ATOMIC_CMP_SWAP_16:
+  case ISD::ATOMIC_CMP_SWAP_32:
+  case ISD::ATOMIC_CMP_SWAP_64: {
     unsigned int num_operands = 4;
     assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
     SDValue Ops[4];
@@ -1201,17 +1209,50 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
     return Result.getValue(Op.getResNo());
   }
-  case ISD::ATOMIC_LOAD_ADD:
-  case ISD::ATOMIC_LOAD_SUB:
-  case ISD::ATOMIC_LOAD_AND:
-  case ISD::ATOMIC_LOAD_OR:
-  case ISD::ATOMIC_LOAD_XOR:
-  case ISD::ATOMIC_LOAD_NAND:
-  case ISD::ATOMIC_LOAD_MIN:
-  case ISD::ATOMIC_LOAD_MAX:
-  case ISD::ATOMIC_LOAD_UMIN:
-  case ISD::ATOMIC_LOAD_UMAX:
-  case ISD::ATOMIC_SWAP: {
+  case ISD::ATOMIC_LOAD_ADD_8:
+  case ISD::ATOMIC_LOAD_SUB_8:
+  case ISD::ATOMIC_LOAD_AND_8:
+  case ISD::ATOMIC_LOAD_OR_8:
+  case ISD::ATOMIC_LOAD_XOR_8:
+  case ISD::ATOMIC_LOAD_NAND_8:
+  case ISD::ATOMIC_LOAD_MIN_8:
+  case ISD::ATOMIC_LOAD_MAX_8:
+  case ISD::ATOMIC_LOAD_UMIN_8:
+  case ISD::ATOMIC_LOAD_UMAX_8:
+  case ISD::ATOMIC_SWAP_8: 
+  case ISD::ATOMIC_LOAD_ADD_16:
+  case ISD::ATOMIC_LOAD_SUB_16:
+  case ISD::ATOMIC_LOAD_AND_16:
+  case ISD::ATOMIC_LOAD_OR_16:
+  case ISD::ATOMIC_LOAD_XOR_16:
+  case ISD::ATOMIC_LOAD_NAND_16:
+  case ISD::ATOMIC_LOAD_MIN_16:
+  case ISD::ATOMIC_LOAD_MAX_16:
+  case ISD::ATOMIC_LOAD_UMIN_16:
+  case ISD::ATOMIC_LOAD_UMAX_16:
+  case ISD::ATOMIC_SWAP_16:
+  case ISD::ATOMIC_LOAD_ADD_32:
+  case ISD::ATOMIC_LOAD_SUB_32:
+  case ISD::ATOMIC_LOAD_AND_32:
+  case ISD::ATOMIC_LOAD_OR_32:
+  case ISD::ATOMIC_LOAD_XOR_32:
+  case ISD::ATOMIC_LOAD_NAND_32:
+  case ISD::ATOMIC_LOAD_MIN_32:
+  case ISD::ATOMIC_LOAD_MAX_32:
+  case ISD::ATOMIC_LOAD_UMIN_32:
+  case ISD::ATOMIC_LOAD_UMAX_32:
+  case ISD::ATOMIC_SWAP_32:
+  case ISD::ATOMIC_LOAD_ADD_64:
+  case ISD::ATOMIC_LOAD_SUB_64:
+  case ISD::ATOMIC_LOAD_AND_64:
+  case ISD::ATOMIC_LOAD_OR_64:
+  case ISD::ATOMIC_LOAD_XOR_64:
+  case ISD::ATOMIC_LOAD_NAND_64:
+  case ISD::ATOMIC_LOAD_MIN_64:
+  case ISD::ATOMIC_LOAD_MAX_64:
+  case ISD::ATOMIC_LOAD_UMIN_64:
+  case ISD::ATOMIC_LOAD_UMAX_64:
+  case ISD::ATOMIC_SWAP_64: {
     unsigned int num_operands = 3;
     assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
     SDValue Ops[3];
@@ -1224,9 +1265,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Result, DAG);
       break;
-    case TargetLowering::Expand:
-      Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0);
-      break;
     case TargetLowering::Legal:
       break;
     }
@@ -1244,7 +1282,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
     if (opAction == TargetLowering::Custom) {
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val)
+      if (Tmp1.getNode())
         Result = Tmp1;
     }
     break;
@@ -1262,7 +1300,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       break;
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Result = Tmp3;
         break;
       }
@@ -1308,27 +1346,27 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
   case ISD::CALL:
     // The only option for this is to custom lower it.
     Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
-    assert(Tmp3.Val && "Target didn't custom lower this node!");
+    assert(Tmp3.getNode() && "Target didn't custom lower this node!");
     // A call within a calling sequence must be legalized to something
     // other than the normal CALLSEQ_END.  Violating this gets Legalize
     // into an infinite loop.
     assert ((!IsLegalizingCall ||
              Node->getOpcode() != ISD::CALL ||
-             Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
+             Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
             "Nested CALLSEQ_START..CALLSEQ_END not supported.");
 
     // The number of incoming and outgoing values should match; unless the final
     // outgoing value is a flag.
-    assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
-            (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
-             Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
+    assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
+            (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
+             Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
                MVT::Flag)) &&
            "Lowering call/formal_arguments produced unexpected # results!");
     
     // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
     // remember that we legalized all of them, so it doesn't get relegalized.
-    for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
-      if (Tmp3.Val->getValueType(i) == MVT::Flag)
+    for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
+      if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
         continue;
       Tmp1 = LegalizeOp(Tmp3.getValue(i));
       if (Op.getResNo() == i)
@@ -1340,7 +1378,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Tmp1 = LegalizeOp(Node->getOperand(0));
       ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
       assert(idx && "Operand must be a constant");
-      Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+      Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
     }
     break;
@@ -1349,7 +1387,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Tmp2 = LegalizeOp(Node->getOperand(1));      
       ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
       assert(idx && "Operand must be a constant");
-      Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
+      Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
     }
     break;      
@@ -1358,13 +1396,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     default: assert(0 && "This action is not supported yet!");
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Result = Tmp3;
         break;
       }
       // FALLTHROUGH
     case TargetLowering::Expand:
-      Result = ExpandBUILD_VECTOR(Result.Val);
+      Result = ExpandBUILD_VECTOR(Result.getNode());
       break;
     }
     break;
@@ -1389,7 +1427,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       break;
     case TargetLowering::Custom:
       Tmp4 = TLI.LowerOperation(Result, DAG);
-      if (Tmp4.Val) {
+      if (Tmp4.getNode()) {
         Result = Tmp4;
         break;
       }
@@ -1415,7 +1453,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           // elt 0 of the RHS.
           SmallVector<SDValue, 8> ShufOps;
           for (unsigned i = 0; i != NumElts; ++i) {
-            if (i != InsertPos->getValue())
+            if (i != InsertPos->getZExtValue())
               ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
             else
               ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
@@ -1449,7 +1487,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       break;
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Result = Tmp3;
         break;
       }
@@ -1473,7 +1511,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       break;
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Result = Tmp3;
         break;
       }
@@ -1491,7 +1529,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
         } else {
           assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
-          unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
+          unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
           if (Idx < NumElems)
             Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
                                       DAG.getConstant(Idx, PtrVT)));
@@ -1514,7 +1552,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       
       // Convert the shuffle mask to the right # elements.
       Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
-      assert(Tmp3.Val && "Shuffle not legal?");
+      assert(Tmp3.getNode() && "Shuffle not legal?");
       Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
       Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
       break;
@@ -1544,7 +1582,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     // are inserted *before* the CALLSEQ_START.
     {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
     for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
-      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
+      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
                                    NodesLeadingTo);
     }
 
@@ -1588,7 +1626,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
   case ISD::CALLSEQ_END:
     // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
     // will cause this node to be legalized as well as handling libcalls right.
-    if (LastCALLSEQ_END.Val != Node) {
+    if (LastCALLSEQ_END.getNode() != Node) {
       LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
       DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
       assert(I != LegalizedNodes.end() &&
@@ -1645,13 +1683,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
       // Chain the dynamic stack allocation so that it doesn't modify the stack
       // pointer when other instructions are using the stack.
-      Chain = DAG.getCALLSEQ_START(Chain,
-                                   DAG.getConstant(0, TLI.getPointerTy()));
+      Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
 
       SDValue Size  = Tmp2.getOperand(1);
       SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
       Chain = SP.getValue(1);
-      unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
+      unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
       unsigned StackAlign =
         TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
       if (Align > StackAlign)
@@ -1660,11 +1697,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size);       // Value
       Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1);     // Output chain
 
-      Tmp2 =
-        DAG.getCALLSEQ_END(Chain,
-                           DAG.getConstant(0, TLI.getPointerTy()),
-                           DAG.getConstant(0, TLI.getPointerTy()),
-                           SDValue());
+      Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
+                                DAG.getIntPtrConstant(0, true), SDValue());
 
       Tmp1 = LegalizeOp(Tmp1);
       Tmp2 = LegalizeOp(Tmp2);
@@ -1672,7 +1706,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     }
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Tmp1, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Tmp1 = LegalizeOp(Tmp3);
         Tmp2 = LegalizeOp(Tmp3.getValue(1));
       }
@@ -1698,7 +1732,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
     bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
     for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
-      unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
+      unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
       for (++i; NumVals; ++i, --NumVals) {
         SDValue Op = LegalizeOp(Ops[i]);
         if (Op != Ops[i]) {
@@ -1761,7 +1795,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Expand: {
       SDValue Chain = Result.getOperand(0);
@@ -1830,7 +1864,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Expand:
       // Expand brcond's setcc into its constituent parts and create a BR_CC
@@ -1857,13 +1891,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     Tmp3 = Node->getOperand(3);              // RHS
     Tmp4 = Node->getOperand(1);              // CC
 
-    LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
+    LegalizeSetCC(Node->getValueType(0), Tmp2, Tmp3, Tmp4);
     LastCALLSEQ_END = DAG.getEntryNode();
 
-    // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
+    // If we didn't get both a LHS and RHS back from LegalizeSetCC,
     // the LHS is a legal SETCC itself.  In this case, we need to compare
     // the result against zero to select between true and false values.
-    if (Tmp3.Val == 0) {
+    if (Tmp3.getNode() == 0) {
       Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
       Tmp4 = DAG.getCondCode(ISD::SETNE);
     }
@@ -1876,7 +1910,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp4 = TLI.LowerOperation(Result, DAG);
-      if (Tmp4.Val) Result = Tmp4;
+      if (Tmp4.getNode()) Result = Tmp4;
       break;
     }
     break;
@@ -1901,7 +1935,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           unsigned ABIAlignment = TLI.getTargetData()->
             getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
           if (LD->getAlignment() < ABIAlignment){
-            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
+            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
                                          TLI);
             Tmp3 = Result.getOperand(0);
             Tmp4 = Result.getOperand(1);
@@ -1912,7 +1946,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         break;
       case TargetLowering::Custom:
         Tmp1 = TLI.LowerOperation(Tmp3, DAG);
-        if (Tmp1.Val) {
+        if (Tmp1.getNode()) {
           Tmp3 = LegalizeOp(Tmp1);
           Tmp4 = LegalizeOp(Tmp1.getValue(1));
         }
@@ -1952,7 +1986,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           // nice to have an effective generic way of getting these benefits...
           // Until such a way is found, don't insist on promoting i1 here.
           (SrcVT != MVT::i1 ||
-           TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
+           TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
         // Promote to a byte-sized load if not loading an integral number of
         // bytes.  For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
         unsigned NewWidth = SrcVT.getStoreSizeInBits();
@@ -2057,7 +2091,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         Tmp1 = LegalizeOp(Result);
         Tmp2 = LegalizeOp(Ch);
       } else {
-        switch (TLI.getLoadXAction(ExtType, SrcVT)) {
+        switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
         default: assert(0 && "This action is not supported yet!");
         case TargetLowering::Custom:
           isCustom = true;
@@ -2069,7 +2103,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
           if (isCustom) {
             Tmp3 = TLI.LowerOperation(Result, DAG);
-            if (Tmp3.Val) {
+            if (Tmp3.getNode()) {
               Tmp1 = LegalizeOp(Tmp3);
               Tmp2 = LegalizeOp(Tmp3.getValue(1));
             }
@@ -2080,7 +2114,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
               unsigned ABIAlignment = TLI.getTargetData()->
                 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
               if (LD->getAlignment() < ABIAlignment){
-                Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
+                Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
                                              TLI);
                 Tmp1 = Result.getOperand(0);
                 Tmp2 = Result.getOperand(1);
@@ -2132,7 +2166,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     switch (getTypeAction(OpTy)) {
     default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
     case Legal:
-      if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
+      if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
         // 1 -> Hi
         Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
                              DAG.getConstant(OpTy.getSizeInBits()/2,
@@ -2147,7 +2181,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case Expand:
       // Get both the low and high parts.
       ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
-      if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
+      if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
         Result = Tmp2;  // 1 -> Hi
       else
         Result = Tmp1;  // 0 -> Lo
@@ -2208,13 +2242,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           if (TLI.isBigEndian())
             std::swap(Lo, Hi);
           
-          if (Hi.Val)
+          if (Hi.getNode())
             Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
           else
             Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
           Result = LegalizeOp(Result);
         } else {
-          SDNode *InVal = Tmp2.Val;
+          SDNode *InVal = Tmp2.getNode();
           int InIx = Tmp2.getResNo();
           unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
           MVT EVT = InVal->getValueType(InIx).getVectorElementType();
@@ -2274,7 +2308,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           ExpandOp(Node->getOperand(i), Lo, Hi);
           NewValues.push_back(Lo);
           NewValues.push_back(Node->getOperand(i+1));
-          if (Hi.Val) {
+          if (Hi.getNode()) {
             NewValues.push_back(Hi);
             NewValues.push_back(Node->getOperand(i+1));
           }
@@ -2299,7 +2333,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       case TargetLowering::Legal: break;
       case TargetLowering::Custom:
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
         break;
       }
     }
@@ -2324,7 +2358,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         if (CFP->getValueType(0) == MVT::f32 && 
             getTypeAction(MVT::i32) == Legal) {
           Tmp3 = DAG.getConstant(CFP->getValueAPF().
-                                          convertToAPInt().zextOrTrunc(32),
+                                          bitcastToAPInt().zextOrTrunc(32),
                                   MVT::i32);
           Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
                                 SVOffset, isVolatile, Alignment);
@@ -2332,7 +2366,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         } else if (CFP->getValueType(0) == MVT::f64) {
           // If this target supports 64-bit registers, do a single 64-bit store.
           if (getTypeAction(MVT::i64) == Legal) {
-            Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
+            Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
                                      zextOrTrunc(64), MVT::i64);
             Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
                                   SVOffset, isVolatile, Alignment);
@@ -2341,7 +2375,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
             // Otherwise, if the target supports 32-bit registers, use 2 32-bit
             // stores.  If the target supports neither 32- nor 64-bits, this
             // xform is certainly not worth it.
-            const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
+            const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
             SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
             SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
             if (TLI.isBigEndian()) std::swap(Lo, Hi);
@@ -2375,13 +2409,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
             unsigned ABIAlignment = TLI.getTargetData()->
               getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
             if (ST->getAlignment() < ABIAlignment)
-              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
+              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
                                             TLI);
           }
           break;
         case TargetLowering::Custom:
           Tmp1 = TLI.LowerOperation(Result, DAG);
-          if (Tmp1.Val) Result = Tmp1;
+          if (Tmp1.getNode()) Result = Tmp1;
           break;
         case TargetLowering::Promote:
           assert(VT.isVector() && "Unknown legal promote case!");
@@ -2410,7 +2444,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         // the product of the element size in bytes, and the number of elements
         // in the high half of the vector.
         if (ST->getValue().getValueType().isVector()) {
-          SDNode *InVal = ST->getValue().Val;
+          SDNode *InVal = ST->getValue().getNode();
           int InIx = ST->getValue().getResNo();
           MVT InVT = InVal->getValueType(InIx);
           unsigned NumElems = InVT.getVectorNumElements();
@@ -2437,21 +2471,21 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
             break;
           } else {
             SplitVectorOp(ST->getValue(), Lo, Hi);
-            IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
+            IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
                             EVT.getSizeInBits()/8;
           }
         } else {
           ExpandOp(ST->getValue(), Lo, Hi);
-          IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
+          IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
 
-          if (TLI.isBigEndian())
+          if (Hi.getNode() && TLI.isBigEndian())
             std::swap(Lo, Hi);
         }
 
         Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
                           SVOffset, isVolatile, Alignment);
 
-        if (Hi.Val == NULL) {
+        if (Hi.getNode() == NULL) {
           // Must be int <-> float one-to-one expansion.
           Result = Lo;
           break;
@@ -2562,7 +2596,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
             unsigned ABIAlignment = TLI.getTargetData()->
               getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
             if (ST->getAlignment() < ABIAlignment)
-              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
+              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
                                             TLI);
           }
           break;
@@ -2596,7 +2630,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp3 = TLI.LowerOperation(Result, DAG);
-      if (Tmp3.Val) {
+      if (Tmp3.getNode()) {
         Tmp1 = LegalizeOp(Tmp3);
         Tmp2 = LegalizeOp(Tmp3.getValue(1));
       }
@@ -2631,7 +2665,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Expand:
       // Expand to CopyToReg if the target set 
@@ -2694,7 +2728,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom: {
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     }
     case TargetLowering::Expand:
@@ -2743,12 +2777,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     Tmp4 = LegalizeOp(Node->getOperand(3));   // False
     SDValue CC = Node->getOperand(4);
     
-    LegalizeSetCCOperands(Tmp1, Tmp2, CC);
+    LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, CC);
     
-    // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
+    // If we didn't get both a LHS and RHS back from LegalizeSetCC,
     // the LHS is a legal SETCC itself.  In this case, we need to compare
     // the result against zero to select between true and false values.
-    if (Tmp2.Val == 0) {
+    if (Tmp2.getNode() == 0) {
       Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
       CC = DAG.getCondCode(ISD::SETNE);
     }
@@ -2760,7 +2794,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     }
     break;
@@ -2769,12 +2803,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     Tmp1 = Node->getOperand(0);
     Tmp2 = Node->getOperand(1);
     Tmp3 = Node->getOperand(2);
-    LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
+    LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
     
     // If we had to Expand the SetCC operands into a SELECT node, then it may 
     // not always be possible to return a true LHS & RHS.  In this case, just 
     // return the value we legalized, returned in the LHS
-    if (Tmp2.Val == 0) {
+    if (Tmp2.getNode() == 0) {
       Result = Tmp1;
       break;
     }
@@ -2788,7 +2822,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
       if (isCustom) {
         Tmp4 = TLI.LowerOperation(Result, DAG);
-        if (Tmp4.Val) Result = Tmp4;
+        if (Tmp4.getNode()) Result = Tmp4;
       }
       break;
     case TargetLowering::Promote: {
@@ -2846,7 +2880,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     }
     break;
@@ -2870,7 +2904,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) {
+      if (Tmp1.getNode()) {
         SDValue Tmp2, RetVal(0, 0);
         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
           Tmp2 = LegalizeOp(Tmp1.getValue(i));
@@ -2878,7 +2912,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           if (i == Op.getResNo())
             RetVal = Tmp2;
         }
-        assert(RetVal.Val && "Illegal result number");
+        assert(RetVal.getNode() && "Illegal result number");
         return RetVal;
       }
       break;
@@ -2938,7 +2972,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) {
+      if (Tmp1.getNode()) {
         Result = Tmp1;
         break;
       }
@@ -2968,28 +3002,32 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           OpToUse = ISD::UMUL_LOHI;
         }
         if (OpToUse) {
-          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
+          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
           break;
         }
       }
       if (Node->getOpcode() == ISD::MULHS &&
           TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
-        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
+        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
+                         1);
         break;
       }
       if (Node->getOpcode() == ISD::MULHU && 
           TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
-        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
+        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
+                         1);
         break;
       }
       if (Node->getOpcode() == ISD::SDIV &&
           TLI.isOperationLegal(ISD::SDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
+        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
+                         0);
         break;
       }
       if (Node->getOpcode() == ISD::UDIV &&
           TLI.isOperationLegal(ISD::UDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
+        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
+                         0);
         break;
       }
 
@@ -3005,6 +3043,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           isSigned = Node->getOpcode() == ISD::SDIV;
         }
         break;
+      case ISD::MUL:
+        if (VT == MVT::i32)
+          LC = RTLIB::MUL_I32;
+        break;
       case ISD::FPOW:
         LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
                           RTLIB::POW_PPCF128);
@@ -3077,7 +3119,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     default: assert(0 && "Operation not supported");
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Legal: break;
     case TargetLowering::Expand: {
@@ -3180,7 +3222,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand: {
@@ -3192,12 +3234,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       SDVTList VTs = DAG.getVTList(VT, VT);
       if (Node->getOpcode() == ISD::SREM &&
           TLI.isOperationLegal(ISD::SDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
+        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
         break;
       }
       if (Node->getOpcode() == ISD::UREM &&
           TLI.isOperationLegal(ISD::UDIVREM, VT)) {
-        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
+        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
         break;
       }
 
@@ -3252,7 +3294,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
 
       if (isCustom) {
         Tmp2 = TLI.LowerOperation(Result, DAG);
-        if (Tmp2.Val) {
+        if (Tmp2.getNode()) {
           Result = LegalizeOp(Tmp2);
           Tmp1 = LegalizeOp(Tmp2.getValue(1));
         }
@@ -3296,7 +3338,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
                                       Node->getOperand(3), Node->getOperand(4));
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand:
@@ -3323,7 +3365,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Tmp1, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand:
@@ -3343,7 +3385,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     case TargetLowering::Legal: break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     }
     break;
@@ -3361,7 +3403,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       break;
     case TargetLowering::Custom:
       Tmp1 = TLI.LowerOperation(Result, DAG);
-      if (Tmp1.Val) Result = Tmp1;
+      if (Tmp1.getNode()) Result = Tmp1;
       break;
     case TargetLowering::Promote:
       assert(0 && "Do not know how to promote ROTL/ROTR");
@@ -3408,7 +3450,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
           TargetLowering::Custom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) {
+        if (Tmp1.getNode()) {
           Result = Tmp1;
         }
       }
@@ -3454,6 +3496,11 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
   case ISD::FSQRT:
   case ISD::FSIN:
   case ISD::FCOS:
+  case ISD::FLOG:
+  case ISD::FLOG2:
+  case ISD::FLOG10:
+  case ISD::FEXP:
+  case ISD::FEXP2:
   case ISD::FTRUNC:
   case ISD::FFLOOR:
   case ISD::FCEIL:
@@ -3469,7 +3516,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       Result = DAG.UpdateNodeOperands(Result, Tmp1);
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand:
@@ -3490,14 +3537,19 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
         break;
       }
+      case ISD::FSQRT:
+      case ISD::FSIN:
+      case ISD::FCOS: 
+      case ISD::FLOG:
+      case ISD::FLOG2:
+      case ISD::FLOG10:
+      case ISD::FEXP:
+      case ISD::FEXP2:
       case ISD::FTRUNC:
       case ISD::FFLOOR:
       case ISD::FCEIL:
       case ISD::FRINT:
-      case ISD::FNEARBYINT:
-      case ISD::FSQRT:
-      case ISD::FSIN:
-      case ISD::FCOS: {
+      case ISD::FNEARBYINT: {
         MVT VT = Node->getValueType(0);
 
         // Expand unsupported unary vector operators by unrolling them.
@@ -3520,6 +3572,26 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
                             RTLIB::COS_F80, RTLIB::COS_PPCF128);
           break;
+        case ISD::FLOG:
+          LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
+                            RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
+          break;
+        case ISD::FLOG2:
+          LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
+                            RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
+          break;
+        case ISD::FLOG10:
+          LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
+                            RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
+          break;
+        case ISD::FEXP:
+          LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
+                            RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
+          break;
+        case ISD::FEXP2:
+          LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
+                            RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
+          break;
         case ISD::FTRUNC:
           LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
                             RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
@@ -3540,6 +3612,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
           LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
                             RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
           break;
+      break;
         default: assert(0 && "Unreachable!");
         }
         SDValue Dummy;
@@ -3573,7 +3646,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     } else if (Op.getOperand(0).getValueType().isVector()) {
       // The input has to be a vector type, we have to either scalarize it, pack
       // it, or convert it based on whether the input vector type is legal.
-      SDNode *InVal = Node->getOperand(0).Val;
+      SDNode *InVal = Node->getOperand(0).getNode();
       int InIx = Node->getOperand(0).getResNo();
       unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
       MVT EVT = InVal->getValueType(InIx).getVectorElementType();
@@ -3654,7 +3727,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         Result = DAG.UpdateNodeOperands(Result, Tmp1);
         if (isCustom) {
           Tmp1 = TLI.LowerOperation(Result, DAG);
-          if (Tmp1.Val) Result = Tmp1;
+          if (Tmp1.getNode()) Result = Tmp1;
         }
         break;
       case TargetLowering::Promote:
@@ -3796,7 +3869,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
           TargetLowering::Custom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case Promote:
@@ -3868,7 +3941,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     Result = DAG.UpdateNodeOperands(Result, Ops, 6);
     // The only option for this node is to custom lower it.
     Result = TLI.LowerOperation(Result, DAG);
-    assert(Result.Val && "Should always custom lower!");
+    assert(Result.getNode() && "Should always custom lower!");
 
     // Since trampoline produces two values, make sure to remember that we
     // legalized both of them.
@@ -3884,7 +3957,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
     default: assert(0 && "This action not supported for this op yet!");
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Legal:
       // If this operation is not supported, lower it to constant 1
@@ -3903,7 +3976,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       break;
     case TargetLowering::Custom:
       Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) break;
+      if (Result.getNode()) break;
       // Fall Thru
     case TargetLowering::Expand:
       // If this operation is not supported, lower it to 'abort()' call
@@ -3911,7 +3984,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       TargetLowering::ArgListTy Args;
       std::pair<SDValue,SDValue> CallResult =
         TLI.LowerCallTo(Tmp1, Type::VoidTy,
-                        false, false, false, CallingConv::C, false,
+                        false, false, false, false, CallingConv::C, false,
                         DAG.getExternalSymbol("abort", TLI.getPointerTy()),
                         Args, DAG);
       Result = CallResult.second;
@@ -3948,7 +4021,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
 
   SDValue Tmp1, Tmp2, Tmp3;
   SDValue Result;
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
 
   DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
   if (I != PromotedNodes.end()) return I->second;
@@ -4127,6 +4200,11 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
     // precision, and these operations don't modify precision at all.
     break;
 
+  case ISD::FLOG:
+  case ISD::FLOG2:
+  case ISD::FLOG10:
+  case ISD::FEXP:
+  case ISD::FEXP2:
   case ISD::FSQRT:
   case ISD::FSIN:
   case ISD::FCOS:
@@ -4143,19 +4221,26 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
                            DAG.getValueType(VT));
     break;
 
+  case ISD::FPOW:
   case ISD::FPOWI: {
-    // Promote f32 powi to f64 powi.  Note that this could insert a libcall
+    // Promote f32 pow(i) to f64 pow(i).  Note that this could insert a libcall
     // directly as well, which may be better.
     Tmp1 = PromoteOp(Node->getOperand(0));
+    Tmp2 = Node->getOperand(1);
+    if (Node->getOpcode() == ISD::FPOW)
+      Tmp2 = PromoteOp(Tmp2);
     assert(Tmp1.getValueType() == NVT);
-    Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
+    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
     if (NoExcessFPPrecision)
       Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
                            DAG.getValueType(VT));
     break;
   }
     
-  case ISD::ATOMIC_CMP_SWAP: {
+  case ISD::ATOMIC_CMP_SWAP_8:
+  case ISD::ATOMIC_CMP_SWAP_16:
+  case ISD::ATOMIC_CMP_SWAP_32:
+  case ISD::ATOMIC_CMP_SWAP_64: {
     AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
     Tmp2 = PromoteOp(Node->getOperand(2));
     Tmp3 = PromoteOp(Node->getOperand(3));
@@ -4167,17 +4252,50 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
     AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
     break;
   }
-  case ISD::ATOMIC_LOAD_ADD:
-  case ISD::ATOMIC_LOAD_SUB:
-  case ISD::ATOMIC_LOAD_AND:
-  case ISD::ATOMIC_LOAD_OR:
-  case ISD::ATOMIC_LOAD_XOR:
-  case ISD::ATOMIC_LOAD_NAND:
-  case ISD::ATOMIC_LOAD_MIN:
-  case ISD::ATOMIC_LOAD_MAX:
-  case ISD::ATOMIC_LOAD_UMIN:
-  case ISD::ATOMIC_LOAD_UMAX:
-  case ISD::ATOMIC_SWAP: {
+  case ISD::ATOMIC_LOAD_ADD_8:
+  case ISD::ATOMIC_LOAD_SUB_8:
+  case ISD::ATOMIC_LOAD_AND_8:
+  case ISD::ATOMIC_LOAD_OR_8:
+  case ISD::ATOMIC_LOAD_XOR_8:
+  case ISD::ATOMIC_LOAD_NAND_8:
+  case ISD::ATOMIC_LOAD_MIN_8:
+  case ISD::ATOMIC_LOAD_MAX_8:
+  case ISD::ATOMIC_LOAD_UMIN_8:
+  case ISD::ATOMIC_LOAD_UMAX_8:
+  case ISD::ATOMIC_SWAP_8: 
+  case ISD::ATOMIC_LOAD_ADD_16:
+  case ISD::ATOMIC_LOAD_SUB_16:
+  case ISD::ATOMIC_LOAD_AND_16:
+  case ISD::ATOMIC_LOAD_OR_16:
+  case ISD::ATOMIC_LOAD_XOR_16:
+  case ISD::ATOMIC_LOAD_NAND_16:
+  case ISD::ATOMIC_LOAD_MIN_16:
+  case ISD::ATOMIC_LOAD_MAX_16:
+  case ISD::ATOMIC_LOAD_UMIN_16:
+  case ISD::ATOMIC_LOAD_UMAX_16:
+  case ISD::ATOMIC_SWAP_16:
+  case ISD::ATOMIC_LOAD_ADD_32:
+  case ISD::ATOMIC_LOAD_SUB_32:
+  case ISD::ATOMIC_LOAD_AND_32:
+  case ISD::ATOMIC_LOAD_OR_32:
+  case ISD::ATOMIC_LOAD_XOR_32:
+  case ISD::ATOMIC_LOAD_NAND_32:
+  case ISD::ATOMIC_LOAD_MIN_32:
+  case ISD::ATOMIC_LOAD_MAX_32:
+  case ISD::ATOMIC_LOAD_UMIN_32:
+  case ISD::ATOMIC_LOAD_UMAX_32:
+  case ISD::ATOMIC_SWAP_32:
+  case ISD::ATOMIC_LOAD_ADD_64:
+  case ISD::ATOMIC_LOAD_SUB_64:
+  case ISD::ATOMIC_LOAD_AND_64:
+  case ISD::ATOMIC_LOAD_OR_64:
+  case ISD::ATOMIC_LOAD_XOR_64:
+  case ISD::ATOMIC_LOAD_NAND_64:
+  case ISD::ATOMIC_LOAD_MIN_64:
+  case ISD::ATOMIC_LOAD_MAX_64:
+  case ISD::ATOMIC_LOAD_UMIN_64:
+  case ISD::ATOMIC_LOAD_UMAX_64:
+  case ISD::ATOMIC_SWAP_64: {
     AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
     Tmp2 = PromoteOp(Node->getOperand(2));
     Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 
@@ -4389,7 +4507,7 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
     break;
   }
 
-  assert(Result.Val && "Didn't set a result!");
+  assert(Result.getNode() && "Didn't set a result!");
 
   // Make sure the result is itself legal.
   Result = LegalizeOp(Result);
@@ -4419,7 +4537,7 @@ SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
     Vec = LegalizeOp(Vec);
     Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
     SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
-    if (Tmp3.Val)
+    if (Tmp3.getNode())
       return Tmp3;
     break;
   }
@@ -4442,11 +4560,11 @@ SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
     ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
     SDValue Lo, Hi;
     SplitVectorOp(Vec, Lo, Hi);
-    if (CIdx->getValue() < NumLoElts) {
+    if (CIdx->getZExtValue() < NumLoElts) {
       Vec = Lo;
     } else {
       Vec = Hi;
-      Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
+      Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
                             Idx.getValueType());
     }
   
@@ -4494,11 +4612,12 @@ SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
   ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
   SDValue Lo, Hi;
   SplitVectorOp(Vec, Lo, Hi);
-  if (CIdx->getValue() < NumElems/2) {
+  if (CIdx->getZExtValue() < NumElems/2) {
     Vec = Lo;
   } else {
     Vec = Hi;
-    Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
+    Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
+                          Idx.getValueType());
   }
   
   // It's now an extract from the appropriate high or low part.  Recurse.
@@ -4557,6 +4676,8 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
                            DAG.getValueType(VT));
         Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
                            DAG.getValueType(VT));
+        Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
+        Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
         break;
       }
     }
@@ -4625,14 +4746,14 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
 
       SDValue Dummy;
       SDValue Ops[2] = { LHS, RHS };
-      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
+      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
                            false /*sign irrelevant*/, Dummy);
       Tmp2 = DAG.getConstant(0, MVT::i32);
       CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
       if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
         Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
                            CC);
-        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
+        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
                             false /*sign irrelevant*/, Dummy);
         Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
                            DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
@@ -4651,14 +4772,16 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
 
     if (VT==MVT::ppcf128) {
       // FIXME:  This generated code sucks.  We want to generate
-      //         FCMP crN, hi1, hi2
+      //         FCMPU crN, hi1, hi2
       //         BNE crN, L:
-      //         FCMP crN, lo1, lo2
+      //         FCMPU crN, lo1, lo2
       // The following can be improved, but not that much.
-      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
+      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 
+                                                         ISD::SETOEQ);
       Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
       Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
-      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
+      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 
+                                                         ISD::SETUNE);
       Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
       Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
       Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
@@ -4719,16 +4842,16 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
       TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
       Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
                                LowCC, false, DagCombineInfo);
-      if (!Tmp1.Val)
+      if (!Tmp1.getNode())
         Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
       Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                                CCCode, false, DagCombineInfo);
-      if (!Tmp2.Val)
+      if (!Tmp2.getNode())
         Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
                            RHSHi,CC);
       
-      ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
-      ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
+      ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
+      ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
       if ((Tmp1C && Tmp1C->isNullValue()) ||
           (Tmp2C && Tmp2C->isNullValue() &&
            (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
@@ -4744,7 +4867,7 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
       } else {
         Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                                    ISD::SETEQ, false, DagCombineInfo);
-        if (!Result.Val)
+        if (!Result.getNode())
           Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
                               ISD::SETEQ);
         Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
@@ -4759,6 +4882,50 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
   RHS = Tmp2;
 }
 
+/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
+/// condition code CC on the current target. This routine assumes LHS and rHS
+/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
+/// illegal condition code into AND / OR of multiple SETCC values.
+void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
+                                                 SDValue &LHS, SDValue &RHS,
+                                                 SDValue &CC) {
+  MVT OpVT = LHS.getValueType();
+  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
+  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
+  default: assert(0 && "Unknown condition code action!");
+  case TargetLowering::Legal:
+    // Nothing to do.
+    break;
+  case TargetLowering::Expand: {
+    ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
+    unsigned Opc = 0;
+    switch (CCCode) {
+    default: assert(0 && "Don't know how to expand this condition!"); abort();
+    case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO;  Opc = ISD::AND; break;
+    case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO;  Opc = ISD::AND; break;
+    case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO;  Opc = ISD::AND; break;
+    case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO;  Opc = ISD::AND; break;
+    case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO;  Opc = ISD::AND; break;
+    case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO;  Opc = ISD::AND; break;
+    case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
+    case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
+    case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
+    case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
+    case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
+    case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
+    // FIXME: Implement more expansions.
+    }
+
+    SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
+    SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
+    LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
+    RHS = SDValue();
+    CC  = SDValue();
+    break;
+  }
+  }
+}
+
 /// EmitStackConvert - Emit a store/load combination to the stack.  This stores
 /// SrcOp to a stack slot of type SlotVT, truncating it if needed.  It then does
 /// a load from the stack slot to DestVT, extending it if needed.
@@ -4869,10 +5036,10 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
     for (unsigned i = 0, e = NumElems; i != e; ++i) {
       if (ConstantFPSDNode *V = 
           dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
-        CV.push_back(ConstantFP::get(V->getValueAPF()));
+        CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
       } else if (ConstantSDNode *V = 
                    dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
-        CV.push_back(ConstantInt::get(V->getAPIntValue()));
+        CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
       } else {
         assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
         const Type *OpNTy = 
@@ -4882,11 +5049,13 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
     }
     Constant *CP = ConstantVector::get(CV);
     SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
+    unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
     return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
-                       PseudoSourceValue::getConstantPool(), 0);
+                       PseudoSourceValue::getConstantPool(), 0,
+                       false, Alignment);
   }
   
-  if (SplatValue.Val) {   // Splat of one value?
+  if (SplatValue.getNode()) {   // Splat of one value?
     // Build the shuffle constant vector: <0, 0, 0, 0>
     MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
     SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
@@ -5023,8 +5192,8 @@ bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
   unsigned NVTBits = NVT.getSizeInBits();
 
   // Handle the case when Amt is an immediate.
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
-    unsigned Cst = CN->getValue();
+  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
+    unsigned Cst = CN->getZExtValue();
     // Expand the incoming operand to be shifted, so that we have its parts
     SDValue InL, InH;
     ExpandOp(Op, InL, InH);
@@ -5184,8 +5353,8 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
   // Splice the libcall in wherever FindInputOutputChains tells us to.
   const Type *RetTy = Node->getValueType(0).getTypeForMVT();
   std::pair<SDValue,SDValue> CallInfo =
-    TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
-                    false, Callee, Args, DAG);
+    TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
+                    CallingConv::C, false, Callee, Args, DAG);
 
   // Legalize the call sequence, starting with the chain.  This will advance
   // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
@@ -5220,14 +5389,14 @@ LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
       // FALLTHROUGH
     case TargetLowering::Legal:
       Tmp1 = LegalizeOp(Op);
-      if (Result.Val)
+      if (Result.getNode())
         Result = DAG.UpdateNodeOperands(Result, Tmp1);
       else
         Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
                              DestTy, Tmp1);
       if (isCustom) {
         Tmp1 = TLI.LowerOperation(Result, DAG);
-        if (Tmp1.Val) Result = Tmp1;
+        if (Tmp1.getNode()) Result = Tmp1;
       }
       break;
     case TargetLowering::Expand:
@@ -5250,7 +5419,7 @@ LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
       Tmp1 = DAG.getZeroExtendInReg(Tmp1,
                                     Op.getValueType());
     }
-    if (Result.Val)
+    if (Result.getNode())
       Result = DAG.UpdateNodeOperands(Result, Tmp1);
     else
       Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
@@ -5285,7 +5454,8 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
                                        DestTy.getVectorNumElements() / 2);
     SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
     SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
-    return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult));
+    return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
+                                  HiResult));
   }
 
   // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
@@ -5303,6 +5473,22 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
       Hi = Source;
     }
 
+    // Check to see if the target has a custom way to lower this.  If so, use it.
+    // (Note we've already expanded the operand in this case.)
+    switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
+    default: assert(0 && "This action not implemented for this operation!");
+    case TargetLowering::Legal:
+    case TargetLowering::Expand:
+      break;   // This case is handled below.
+    case TargetLowering::Custom: {
+      SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
+                                                    Source), DAG);
+      if (NV.getNode())
+        return LegalizeOp(NV);
+      break;   // The target decided this was legal after all
+    }
+    }
+
     // If this is unsigned, and not supported, first perform the conversion to
     // signed, then adjust the result if the sign bit is set.
     SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
@@ -5318,17 +5504,20 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
     static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
 
     SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
+    unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
     CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
+    Alignment = std::min(Alignment, 4u);
     SDValue FudgeInReg;
     if (DestTy == MVT::f32)
       FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
-                               PseudoSourceValue::getConstantPool(), 0);
+                               PseudoSourceValue::getConstantPool(), 0,
+                               false, Alignment);
     else if (DestTy.bitsGT(MVT::f32))
       // FIXME: Avoid the extend by construction the right constantpool?
       FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
                                   CPIdx,
                                   PseudoSourceValue::getConstantPool(), 0,
-                                  MVT::f32);
+                                  MVT::f32, false, Alignment);
     else 
       assert(0 && "Unexpected conversion");
 
@@ -5355,7 +5544,7 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
   case TargetLowering::Custom: {
     SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
                                                   Source), DAG);
-    if (NV.Val)
+    if (NV.getNode())
       return LegalizeOp(NV);
     break;   // The target decided this was legal after all
   }
@@ -5376,8 +5565,8 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
 
   Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
   SDValue HiPart;
-  SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
-  if (Result.getValueType() != DestTy && HiPart.Val)
+  SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
+  if (Result.getValueType() != DestTy && HiPart.getNode())
     Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
   return Result;
 }
@@ -5467,17 +5656,20 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
   static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
 
   SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
+  unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
   CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
+  Alignment = std::min(Alignment, 4u);
   SDValue FudgeInReg;
   if (DestVT == MVT::f32)
     FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
-                             PseudoSourceValue::getConstantPool(), 0);
+                             PseudoSourceValue::getConstantPool(), 0,
+                             false, Alignment);
   else {
     FudgeInReg =
       LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
                                 DAG.getEntryNode(), CPIdx,
                                 PseudoSourceValue::getConstantPool(), 0,
-                                MVT::f32));
+                                MVT::f32, false, Alignment));
   }
 
   return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
@@ -5593,8 +5785,8 @@ SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
   // the target lowering hooks to expand it.  Just keep the low part of the
   // expanded operation, we know that we're truncating anyway.
   if (getTypeAction(NewOutTy) == Expand) {
-    Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
-    assert(Operation.Val && "Didn't return anything");
+    Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
+    assert(Operation.getNode() && "Didn't return anything");
   }
 
   // Truncate the result of the extended FP_TO_*INT operation to the desired
@@ -5716,13 +5908,13 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
 
 /// ExpandOp - Expand the specified SDValue into its two component pieces
 /// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this, the
-/// LegalizeNodes map is filled in for any results that are not expanded, the
+/// LegalizedNodes map is filled in for any results that are not expanded, the
 /// ExpandedNodes map is filled in for any results that are expanded, and the
 /// Lo/Hi values are returned.
 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
   MVT VT = Op.getValueType();
   MVT NVT = TLI.getTypeToTransformTo(VT);
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
   assert(getTypeAction(VT) == Expand && "Not an expanded type!");
   assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
          VT.isVector()) && "Cannot expand to FP value or to larger int value!");
@@ -5748,9 +5940,9 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
       Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
       SDValue Result = TLI.LowerOperation(
         DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
-      assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
-      Lo = Result.Val->getOperand(0);
-      Hi = Result.Val->getOperand(1);
+      assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
+      Lo = Result.getNode()->getOperand(0);
+      Hi = Result.getNode()->getOperand(1);
       break;
     }
     // fall through
@@ -5762,7 +5954,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     abort();
   case ISD::EXTRACT_ELEMENT:
     ExpandOp(Node->getOperand(0), Lo, Hi);
-    if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
+    if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
       return ExpandOp(Hi, Lo, Hi);
     return ExpandOp(Lo, Lo, Hi);
   case ISD::EXTRACT_VECTOR_ELT:
@@ -5784,7 +5976,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
   case ISD::ConstantFP: {
     ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
     if (CFP->getValueType(0) == MVT::ppcf128) {
-      APInt api = CFP->getValueAPF().convertToAPInt();
+      APInt api = CFP->getValueAPF().bitcastToAPInt();
       Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
                              MVT::f64);
       Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 
@@ -6073,7 +6265,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     }
 
     // Turn this into a load/store pair by default.
-    if (Tmp.Val == 0)
+    if (Tmp.getNode() == 0)
       Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
     
     ExpandOp(Tmp, Lo, Hi);
@@ -6085,23 +6277,45 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
                  TargetLowering::Custom &&
            "Must custom expand ReadCycleCounter");
     SDValue Tmp = TLI.LowerOperation(Op, DAG);
-    assert(Tmp.Val && "Node must be custom expanded!");
+    assert(Tmp.getNode() && "Node must be custom expanded!");
     ExpandOp(Tmp.getValue(0), Lo, Hi);
     AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
                         LegalizeOp(Tmp.getValue(1)));
     break;
   }
 
-  case ISD::ATOMIC_CMP_SWAP: {
+  case ISD::ATOMIC_CMP_SWAP_64: {
+    // This operation does not need a loop.
     SDValue Tmp = TLI.LowerOperation(Op, DAG);
-    assert(Tmp.Val && "Node must be custom expanded!");
+    assert(Tmp.getNode() && "Node must be custom expanded!");
     ExpandOp(Tmp.getValue(0), Lo, Hi);
     AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
                         LegalizeOp(Tmp.getValue(1)));
     break;
   }
 
-
+  case ISD::ATOMIC_LOAD_ADD_64:
+  case ISD::ATOMIC_LOAD_SUB_64:
+  case ISD::ATOMIC_LOAD_AND_64:
+  case ISD::ATOMIC_LOAD_OR_64:
+  case ISD::ATOMIC_LOAD_XOR_64:
+  case ISD::ATOMIC_LOAD_NAND_64:
+  case ISD::ATOMIC_SWAP_64: {
+    // These operations require a loop to be generated.  We can't do that yet,
+    // so substitute a target-dependent pseudo and expand that later.
+    SDValue In2Lo, In2Hi, In2;
+    ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
+    In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
+    AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
+    SDValue Replace = 
+      DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
+                    Anode->getSrcValue(), Anode->getAlignment());
+    SDValue Result = TLI.LowerOperation(Replace, DAG);
+    ExpandOp(Result.getValue(0), Lo, Hi);
+    // Remember that we legalized the chain.
+    AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
+    break;
+  }
 
     // These operators cannot be expanded directly, emit them as calls to
     // library functions.
@@ -6118,7 +6332,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
 
       // Now that the custom expander is done, expand the result, which is still
       // VT.
-      if (Op.Val) {
+      if (Op.getNode()) {
         ExpandOp(Op, Lo, Hi);
         break;
       }
@@ -6143,7 +6357,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
       Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
 
       // Now that the custom expander is done, expand the result.
-      if (Op.Val) {
+      if (Op.getNode()) {
         ExpandOp(Op, Lo, Hi);
         break;
       }
@@ -6162,7 +6376,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
       SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
       Op = TLI.LowerOperation(Op, DAG);
-      if (Op.Val) {
+      if (Op.getNode()) {
         // Now that the custom expander is done, expand the result, which is
         // still VT.
         ExpandOp(Op, Lo, Hi);
@@ -6212,7 +6426,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
       SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
       Op = TLI.LowerOperation(Op, DAG);
-      if (Op.Val) {
+      if (Op.getNode()) {
         // Now that the custom expander is done, expand the result, which is
         // still VT.
         ExpandOp(Op, Lo, Hi);
@@ -6244,7 +6458,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
       SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
       Op = TLI.LowerOperation(Op, DAG);
-      if (Op.Val) {
+      if (Op.getNode()) {
         // Now that the custom expander is done, expand the result, which is
         // still VT.
         ExpandOp(Op, Lo, Hi);
@@ -6276,12 +6490,11 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     if (TLI.getOperationAction(Node->getOpcode(), VT) ==
             TargetLowering::Custom) {
       SDValue Result = TLI.LowerOperation(Op, DAG);
-      if (Result.Val) {
+      if (Result.getNode()) {
         ExpandOp(Result, Lo, Hi);
         break;
       }
     }
-    
     // Expand the subcomponents.
     SDValue LHSL, LHSH, RHSL, RHSH;
     ExpandOp(Node->getOperand(0), LHSL, LHSH);
@@ -6292,16 +6505,55 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     LoOps[1] = RHSL;
     HiOps[0] = LHSH;
     HiOps[1] = RHSH;
-    if (Node->getOpcode() == ISD::ADD) {
-      Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
-      HiOps[2] = Lo.getValue(1);
-      Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
+
+    //cascaded check to see if any smaller size has a a carry flag.
+    unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
+    bool hasCarry = false;
+    for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
+      MVT AVT = MVT::getIntegerVT(BitSize);
+      if (TLI.isOperationLegal(OpV, AVT)) {
+        hasCarry = true;
+        break;
+      }
+    }
+
+    if(hasCarry) {
+      if (Node->getOpcode() == ISD::ADD) {
+        Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
+        HiOps[2] = Lo.getValue(1);
+        Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
+      } else {
+        Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
+        HiOps[2] = Lo.getValue(1);
+        Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
+      }
+      break;
     } else {
-      Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
-      HiOps[2] = Lo.getValue(1);
-      Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
+      if (Node->getOpcode() == ISD::ADD) {
+        Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
+        Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
+        SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
+                                    Lo, LoOps[0], ISD::SETULT);
+        SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
+                                     DAG.getConstant(1, NVT), 
+                                     DAG.getConstant(0, NVT));
+        SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
+                                    Lo, LoOps[1], ISD::SETULT);
+        SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
+                                    DAG.getConstant(1, NVT), 
+                                    Carry1);
+        Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
+      } else {
+        Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
+        Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
+        SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
+        SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
+                                     DAG.getConstant(1, NVT), 
+                                     DAG.getConstant(0, NVT));
+        Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
+      }
+      break;
     }
-    break;
   }
     
   case ISD::ADDC:
@@ -6349,7 +6601,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     // If the target wants to custom expand this, let them.
     if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
       SDValue New = TLI.LowerOperation(Op, DAG);
-      if (New.Val) {
+      if (New.getNode()) {
         ExpandOp(New, Lo, Hi);
         break;
       }
@@ -6374,7 +6626,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
         if (HasUMUL_LOHI) {
           // We can emit a umul_lohi.
           Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
-          Hi = SDValue(Lo.Val, 1);
+          Hi = SDValue(Lo.getNode(), 1);
           break;
         }
         if (HasMULHU) {
@@ -6389,7 +6641,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
         if (HasSMUL_LOHI) {
           // We can emit a smul_lohi.
           Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
-          Hi = SDValue(Lo.Val, 1);
+          Hi = SDValue(Lo.getNode(), 1);
           break;
         }
         if (HasMULHS) {
@@ -6491,21 +6743,21 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
     Lo = ExpandLibCall(LC, Node, true, Hi);
     break;
   }
-  case ISD::FPOWI:
-    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
-                                        RTLIB::POWI_F64,
-                                        RTLIB::POWI_F80,
-                                        RTLIB::POWI_PPCF128),
-                       Node, false, Hi);
-    break;
+  case ISD::FSQRT:
+  case ISD::FSIN:
+  case ISD::FCOS: 
+  case ISD::FLOG:
+  case ISD::FLOG2:
+  case ISD::FLOG10:
+  case ISD::FEXP:
+  case ISD::FEXP2:
   case ISD::FTRUNC:
   case ISD::FFLOOR:
   case ISD::FCEIL:
   case ISD::FRINT:
   case ISD::FNEARBYINT:
-  case ISD::FSQRT:
-  case ISD::FSIN:
-  case ISD::FCOS: {
+  case ISD::FPOW:
+  case ISD::FPOWI: {
     RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
     switch(Node->getOpcode()) {
     case ISD::FSQRT:
@@ -6520,6 +6772,26 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
       LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
                         RTLIB::COS_F80, RTLIB::COS_PPCF128);
       break;
+    case ISD::FLOG:
+      LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
+                        RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
+      break;
+    case ISD::FLOG2:
+      LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
+                        RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
+      break;
+    case ISD::FLOG10:
+      LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
+                        RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
+      break;
+    case ISD::FEXP:
+      LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
+                        RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
+      break;
+    case ISD::FEXP2:
+      LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
+                        RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
+      break;
     case ISD::FTRUNC:
       LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
                         RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
@@ -6540,6 +6812,14 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
       LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
                         RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
       break;
+    case ISD::FPOW:
+      LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
+                        RTLIB::POW_PPCF128);
+      break;
+    case ISD::FPOWI:
+      LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
+                        RTLIB::POWI_PPCF128);
+      break;
     default: assert(0 && "Unreachable!");
     }
     Lo = ExpandLibCall(LC, Node, false, Hi);
@@ -6602,7 +6882,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
         ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
                       DAG.getValueType(SrcVT))
         : DAG.getZeroExtendInReg(Tmp, SrcVT);
-      Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
+      Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
       SrcVT = Node->getOperand(0).getValueType();
     }
 
@@ -6663,7 +6943,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
   // is a type that requires multi-step expansion.
   if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
     Lo = LegalizeOp(Lo);
-    if (Hi.Val)
+    if (Hi.getNode())
       // Don't legalize the high part if it is expanded to a single node.
       Hi = LegalizeOp(Hi);
   }
@@ -6679,7 +6959,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
                                          SDValue &Hi) {
   assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
   unsigned NumElements = Op.getValueType().getVectorNumElements();
   assert(NumElements > 1 && "Cannot split a single element vector!");
 
@@ -6717,7 +6997,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
   case ISD::INSERT_VECTOR_ELT: {
     if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
       SplitVectorOp(Node->getOperand(0), Lo, Hi);
-      unsigned Index = Idx->getValue();
+      unsigned Index = Idx->getZExtValue();
       SDValue ScalarOp = Node->getOperand(1);
       if (Index < NewNumElts_Lo)
         Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
@@ -6748,7 +7028,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
         Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
         continue;
       }
-      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
+      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
       SDValue InVec = Node->getOperand(0);
       if (Idx >= NumElements) {
         InVec = Node->getOperand(1);
@@ -6766,7 +7046,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
         Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
         continue;
       }
-      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
+      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
       SDValue InVec = Node->getOperand(0);
       if (Idx >= NumElements) {
         InVec = Node->getOperand(1);
@@ -6890,6 +7170,11 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
   case ISD::FSQRT:
   case ISD::FSIN:
   case ISD::FCOS:
+  case ISD::FLOG:
+  case ISD::FLOG2:
+  case ISD::FLOG10:
+  case ISD::FEXP:
+  case ISD::FEXP2:
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::SINT_TO_FP:
@@ -6957,7 +7242,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
       unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
                                             Op.getValueType().getTypeForMVT());
       SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
-      int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
+      int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
 
       SDValue St = DAG.getStore(DAG.getEntryNode(),
                                   InOp, Ptr,
@@ -6985,7 +7270,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
 /// scalar (e.g. f32) value.
 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
   assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
-  SDNode *Node = Op.Val;
+  SDNode *Node = Op.getNode();
   MVT NewVT = Op.getValueType().getVectorElementType();
   assert(Op.getValueType().getVectorNumElements() == 1);
   
@@ -7026,6 +7311,11 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
   case ISD::FSQRT:
   case ISD::FSIN:
   case ISD::FCOS:
+  case ISD::FLOG:
+  case ISD::FLOG2:
+  case ISD::FLOG10:
+  case ISD::FEXP:
+  case ISD::FEXP2:
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::SINT_TO_FP:
@@ -7084,7 +7374,7 @@ SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
   case ISD::VECTOR_SHUFFLE: {
     // Figure out if the scalar is the LHS or RHS and return it.
     SDValue EltNum = Node->getOperand(2).getOperand(0);
-    if (cast<ConstantSDNode>(EltNum)->getValue())
+    if (cast<ConstantSDNode>(EltNum)->getZExtValue())
       Result = ScalarizeVectorOp(Node->getOperand(1));
     else
       Result = ScalarizeVectorOp(Node->getOperand(0));