X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FLegalizeIntegerTypes.cpp;h=20cfc77e022a60e40e7b95e29ef38f6c542be630;hb=9bed0f58eb7f5e9e22d062f3880a5fabfdd0dfdd;hp=0db87e9e6a2bcf769bfe73deb7e6ac783e561c06;hpb=5ac319ac7125b009adddcc49294d2e040c4a91e5;p=oota-llvm.git

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 0db87e9e6a2..20cfc77e022 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1454,21 +1454,35 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
   }
 
   // Otherwise, emit a libcall.
-  assert(VT == MVT::i64 && "Unsupported shift!");
-
-  RTLIB::Libcall LC;
+  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
   bool isSigned;
   if (N->getOpcode() == ISD::SHL) {
-    LC = RTLIB::SHL_I64;
     isSigned = false; /*sign irrelevant*/
+    if (VT == MVT::i32)
+      LC = RTLIB::SHL_I32;
+    else if (VT == MVT::i64)
+      LC = RTLIB::SHL_I64;
+    else if (VT == MVT::i128)
+      LC = RTLIB::SHL_I128;
   } else if (N->getOpcode() == ISD::SRL) {
-    LC = RTLIB::SRL_I64;
     isSigned = false;
+    if (VT == MVT::i32)
+      LC = RTLIB::SRL_I32;
+    else if (VT == MVT::i64)
+      LC = RTLIB::SRL_I64;
+    else if (VT == MVT::i128)
+      LC = RTLIB::SRL_I128;
   } else {
     assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
-    LC = RTLIB::SRA_I64;
     isSigned = true;
+    if (VT == MVT::i32)
+      LC = RTLIB::SRA_I32;
+    else if (VT == MVT::i64)
+      LC = RTLIB::SRA_I64;
+    else if (VT == MVT::i128)
+      LC = RTLIB::SRA_I128;
   }
+  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
 
   SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
   SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
@@ -1542,6 +1556,13 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
     } else if (Amt == NVTBits) {
       Lo = DAG.getConstant(0, NVT);
       Hi = InL;
+    } else if (Amt == 1) {
+      // Emit this X << 1 as X+X.
+      SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
+      SDOperand LoOps[2] = { InL, InL };
+      Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
+      SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) };
+      Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
     } else {
       Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
       Hi = DAG.getNode(ISD::OR, NVT,
@@ -1750,11 +1771,12 @@ SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
 }
 
 SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source,
-                                                     MVT DestTy) {
+                                                   MVT DestTy) {
   // We know the destination is legal, but that the input needs to be expanded.
   MVT SourceVT = Source.getValueType();
 
   // Check to see if the target has a custom way to lower this.  If so, use it.
+  // This can trigger when called from ExpandIntOp_UINT_TO_FP.
   switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
   default: assert(0 && "This action not implemented for this operation!");
   case TargetLowering::Legal:
@@ -1768,13 +1790,24 @@ SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source,
   }
 
   RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
-  if (SourceVT == MVT::i64) {
+  if (SourceVT == MVT::i32) {
+    if (DestTy == MVT::f32)
+      LC = RTLIB::SINTTOFP_I32_F32;
+    else if (DestTy == MVT::f64)
+      LC = RTLIB::SINTTOFP_I32_F64;
+    else if (DestTy == MVT::f80)
+      LC = RTLIB::SINTTOFP_I32_F80;
+    else if (DestTy == MVT::ppcf128)
+      LC = RTLIB::SINTTOFP_I32_PPCF128;
+  } else if (SourceVT == MVT::i64) {
     if (DestTy == MVT::f32)
       LC = RTLIB::SINTTOFP_I64_F32;
-    else {
-      assert(DestTy == MVT::f64 && "Unknown fp value type!");
+    else if (DestTy == MVT::f64)
       LC = RTLIB::SINTTOFP_I64_F64;
-    }
+    else if (DestTy == MVT::f80)
+      LC = RTLIB::SINTTOFP_I64_F80;
+    else if (DestTy == MVT::ppcf128)
+      LC = RTLIB::SINTTOFP_I64_PPCF128;
   } else if (SourceVT == MVT::i128) {
     if (DestTy == MVT::f32)
       LC = RTLIB::SINTTOFP_I128_F32;
@@ -1782,16 +1815,12 @@ SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source,
       LC = RTLIB::SINTTOFP_I128_F64;
     else if (DestTy == MVT::f80)
       LC = RTLIB::SINTTOFP_I128_F80;
-    else {
-      assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
+    else if (DestTy == MVT::ppcf128)
       LC = RTLIB::SINTTOFP_I128_PPCF128;
-    }
-  } else {
-    assert(0 && "Unknown int value type!");
   }
-
   assert(LC != RTLIB::UNKNOWN_LIBCALL &&
          "Don't know how to expand this SINT_TO_FP!");
+
   return MakeLibCall(LC, DestTy, &Source, 1, true);
 }