X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FLegalizeIntegerTypes.cpp;h=650f02ca8ac529f0f17c6bef17bb36b102e5f866;hb=9a6b92de4c2207b427f3b9cd67cd122dafc5b6c6;hp=d4be998be5ed32d4d5d0db868549680059da085a;hpb=ee4c619b3b28a42078fc8033e5dccd42fc6edd42;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index d4be998be5e..650f02ca8ac 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -59,6 +59,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; case ISD::Constant: Result = PromoteIntRes_Constant(N); break; + case ISD::CONVERT_RNDSAT: + Result = PromoteIntRes_CONVERT_RNDSAT(N); break; case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; @@ -157,19 +159,14 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { // Sign-extend the new bits, and continue the assertion. - MVT OldVT = N->getValueType(0); - SDValue Op = GetPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::AssertSext, Op.getValueType(), - DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, - DAG.getValueType(OldVT)), N->getOperand(1)); + SDValue Op = SExtPromotedInteger(N->getOperand(0)); + return DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { // Zero the new bits, and continue the assertion. - MVT OldVT = N->getValueType(0); - SDValue Op = GetPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::AssertZext, Op.getValueType(), - DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1)); + SDValue Op = ZExtPromotedInteger(N->getOperand(0)); + return DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { @@ -206,7 +203,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { case Legal: break; case PromoteInteger: - if (OutVT.getSizeInBits() == NInVT.getSizeInBits()) + if (OutVT.bitsEq(NInVT)) // The input promotes to the same size. Convert the promoted value. return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); break; @@ -267,17 +264,29 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { // matter in theory which one we pick, but this tends to give better code? unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), - SDValue(N, 0)); + SDValue(N, 0)); assert(isa(Result) && "Didn't constant fold ext?"); return Result; } +SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { + ISD::CvtCode CvtCode = cast(N)->getCvtCode(); + assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || + CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || + CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && + "can only promote integers"); + MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); + return DAG.getConvertRndSat(OutVT, N->getOperand(0), + N->getOperand(1), N->getOperand(2), + N->getOperand(3), N->getOperand(4), CvtCode); +} + SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { - SDValue Op = GetPromotedInteger(N->getOperand(0)); + // Zero extend to the promoted type and do the count there. + SDValue Op = ZExtPromotedInteger(N->getOperand(0)); MVT OVT = N->getValueType(0); MVT NVT = Op.getValueType(); - // Zero extend to the promoted type and do the count there. - Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); + Op = DAG.getNode(ISD::CTLZ, NVT, Op); // Subtract off the extra leading bits in the bigger type. return DAG.getNode(ISD::SUB, NVT, Op, DAG.getConstant(NVT.getSizeInBits() - @@ -285,11 +294,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { - SDValue Op = GetPromotedInteger(N->getOperand(0)); - MVT OVT = N->getValueType(0); - MVT NVT = Op.getValueType(); // Zero extend to the promoted type and do the count there. - return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); + SDValue Op = ZExtPromotedInteger(N->getOperand(0)); + return DAG.getNode(ISD::CTPOP, Op.getValueType(), Op); } SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { @@ -340,8 +347,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { // Hi if it was odd. SDValue Lo = Elt; SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, - DAG.getConstant(OldVT.getSizeInBits(), - TLI.getShiftAmountTy())); + DAG.getConstant(OldVT.getSizeInBits(), + TLI.getShiftAmountTy())); if (TLI.isBigEndian()) std::swap(Lo, Hi); @@ -350,22 +357,27 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { - unsigned NewOpc = N->getOpcode(); MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + unsigned NewOpc = N->getOpcode(); // If we're promoting a UINT to a larger size, check to see if the new node // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since // we can use that instead. This allows us to generate better code for // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not // legal, such as PowerPC. - if (N->getOpcode() == ISD::FP_TO_UINT) { - if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && - (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || - TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)) - NewOpc = ISD::FP_TO_SINT; - } + if (N->getOpcode() == ISD::FP_TO_UINT && + !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && + TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) + NewOpc = ISD::FP_TO_SINT; - return DAG.getNode(NewOpc, NVT, N->getOperand(0)); + SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); + + // Assert that the converted value fits in the original type. If it doesn't + // (eg: because the value being converted is too big), then the result of the + // original operation was undefined anyway, so the assert is still correct. + return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? + ISD::AssertZext : ISD::AssertSext, + NVT, Res, DAG.getValueType(N->getValueType(0))); } SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { @@ -373,8 +385,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { SDValue Res = GetPromotedInteger(N->getOperand(0)); - assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() && - "Extension doesn't make sense!"); + assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); // If the result and operand types are the same after promotion, simplify // to an in-register extension. @@ -412,14 +423,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { // Sign extend the input. - SDValue LHS = GetPromotedInteger(N->getOperand(0)); - SDValue RHS = GetPromotedInteger(N->getOperand(1)); - MVT VT = N->getValueType(0); - LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, - DAG.getValueType(VT)); - RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, - DAG.getValueType(VT)); - + SDValue LHS = SExtPromotedInteger(N->getOperand(0)); + SDValue RHS = SExtPromotedInteger(N->getOperand(1)); return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); } @@ -446,8 +451,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { // Convert to the expected type. MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - assert(NVT.getSizeInBits() <= SVT.getSizeInBits() && - "Integer type overpromoted?"); + assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); return DAG.getNode(ISD::TRUNCATE, NVT, SetCC); } @@ -473,11 +477,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { // The input value must be properly sign extended. - MVT VT = N->getValueType(0); - MVT NVT = TLI.getTypeToTransformTo(VT); - SDValue Res = GetPromotedInteger(N->getOperand(0)); - Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); - return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); + SDValue Res = SExtPromotedInteger(N->getOperand(0)); + return DAG.getNode(ISD::SRA, Res.getValueType(), Res, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { @@ -489,6 +490,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Res; switch (getTypeAction(N->getOperand(0).getValueType())) { @@ -502,24 +504,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { break; } - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() && - "Truncation doesn't make sense!"); - if (Res.getValueType() == NVT) - return Res; - // Truncate to NVT instead of VT return DAG.getNode(ISD::TRUNCATE, NVT, Res); } SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { // Zero extend the input. - SDValue LHS = GetPromotedInteger(N->getOperand(0)); - SDValue RHS = GetPromotedInteger(N->getOperand(1)); - MVT VT = N->getValueType(0); - LHS = DAG.getZeroExtendInReg(LHS, VT); - RHS = DAG.getZeroExtendInReg(RHS, VT); - + SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); + SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); } @@ -532,29 +524,37 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { SDValue Ptr = N->getOperand(1); // Get the pointer. MVT VT = N->getValueType(0); - const Value *V = cast(N->getOperand(2))->getValue(); - SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0); + MVT RegVT = TLI.getRegisterType(VT); + unsigned NumRegs = TLI.getNumRegisters(VT); + // The argument is passed as NumRegs registers of type RegVT. - // Increment the arg pointer, VAList, to the next vaarg - // FIXME: should the ABI size be used for the increment? Think of - // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or - // integers of unusual size (such MVT::i1, which gives an increment - // of zero here!). - unsigned Increment = VT.getSizeInBits() / 8; - SDValue Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, - DAG.getIntPtrConstant(Increment)); + SmallVector Parts(NumRegs); + for (unsigned i = 0; i < NumRegs; ++i) { + Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); + Chain = Parts[i].getValue(1); + } - // Store the incremented VAList to the pointer. - Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0); + // Handle endianness of the load. + if (TLI.isBigEndian()) + std::reverse(Parts.begin(), Parts.end()); - // Load the actual argument out of the arg pointer VAList. - Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp, - VAList, NULL, 0, VT); + // Assemble the parts in the promoted type. + MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]); + for (unsigned i = 1; i < NumRegs; ++i) { + SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]); + // Shift it to the right position and "or" it in. + Part = DAG.getNode(ISD::SHL, NVT, Part, + DAG.getConstant(i * RegVT.getSizeInBits(), + TLI.getShiftAmountTy())); + Res = DAG.getNode(ISD::OR, NVT, Res, Part); + } - // Legalized the chain result - switch anything that used the old chain to + // Modified the chain result - switch anything that used the old chain to // use the new one. - ReplaceValueWith(SDValue(N, 1), Tmp.getValue(1)); - return Tmp; + ReplaceValueWith(SDValue(N, 1), Chain); + + return Res; } @@ -589,8 +589,8 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; - case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; - case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; + case ISD::CONVERT_RNDSAT: + Res = PromoteIntOp_CONVERT_RNDSAT(N); break; case ISD::INSERT_VECTOR_ELT: Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; @@ -598,13 +598,12 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; + case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; case ISD::STORE: Res = PromoteIntOp_STORE(cast(N), OpNo); break; case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; + case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; - - case ISD::SINT_TO_FP: - case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; } } @@ -630,16 +629,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { /// shared among BR_CC, SELECT_CC, and SETCC handlers. void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, ISD::CondCode CCCode) { - MVT VT = NewLHS.getValueType(); - - // Get the promoted values. - NewLHS = GetPromotedInteger(NewLHS); - NewRHS = GetPromotedInteger(NewRHS); - - // Otherwise, we have to insert explicit sign or zero extends. Note - // that we could insert sign extends for ALL conditions, but zero extend - // is cheaper on many machines (an AND instead of two shifts), so prefer - // it. + // We have to insert explicit sign or zero extends. Note that we could + // insert sign extends for ALL conditions, but zero extend is cheaper on + // many machines (an AND instead of two shifts), so prefer it. switch (CCCode) { default: assert(0 && "Unknown integer comparison!"); case ISD::SETEQ: @@ -651,17 +643,15 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, // ALL of these operations will work if we either sign or zero extend // the operands (including the unsigned comparisons!). Zero extend is // usually a simpler/cheaper operation, so prefer it. - NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); - NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); + NewLHS = ZExtPromotedInteger(NewLHS); + NewRHS = ZExtPromotedInteger(NewRHS); break; case ISD::SETGE: case ISD::SETGT: case ISD::SETLT: case ISD::SETLE: - NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, - DAG.getValueType(VT)); - NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, - DAG.getValueType(VT)); + NewLHS = SExtPromotedInteger(NewLHS); + NewRHS = SExtPromotedInteger(NewRHS); break; } } @@ -688,12 +678,25 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { assert(OpNo == 1 && "only know how to promote condition"); SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. - // The top bits of the promoted condition are not necessarily zero, ensure - // that the value is properly zero extended. - unsigned BitWidth = Cond.getValueSizeInBits(); - if (!DAG.MaskedValueIsZero(Cond, - APInt::getHighBitsSet(BitWidth, BitWidth-1))) - Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); + // Make sure the extra bits coming from type promotion conform to + // getSetCCResultContents. + unsigned CondBits = Cond.getValueSizeInBits(); + switch (TLI.getSetCCResultContents()) { + default: + assert(false && "Unknown SetCCResultValue!"); + case TargetLowering::UndefinedSetCCResult: + // The promoted value, which may contain rubbish in the upper bits, is fine. + break; + case TargetLowering::ZeroOrOneSetCCResult: + if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) + Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); + break; + case TargetLowering::ZeroOrNegativeOneSetCCResult: + if (DAG.ComputeNumSignBits(Cond) != CondBits) + Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond, + DAG.getValueType(MVT::i1)); + break; + } // The chain (Op#0) and basic block destination (Op#2) are always legal types. return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, @@ -703,11 +706,10 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { // Since the result type is legal, the operands must promote to it. MVT OVT = N->getOperand(0).getValueType(); - SDValue Lo = GetPromotedInteger(N->getOperand(0)); + SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); SDValue Hi = GetPromotedInteger(N->getOperand(1)); assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); - Lo = DAG.getZeroExtendInReg(Lo, OVT); Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, DAG.getConstant(OVT.getSizeInBits(), TLI.getShiftAmountTy())); @@ -748,15 +750,16 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); } -SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { - SDValue Op = GetPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); -} - -SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { - SDValue Op = GetPromotedInteger(N->getOperand(0)); - return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, - DAG.getIntPtrConstant(0)); +SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { + ISD::CvtCode CvtCode = cast(N)->getCvtCode(); + assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || + CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || + CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && + "can only promote integer arguments"); + SDValue InOp = GetPromotedInteger(N->getOperand(0)); + return DAG.getConvertRndSat(N->getValueType(0), InOp, + N->getOperand(1), N->getOperand(2), + N->getOperand(3), N->getOperand(4), CvtCode); } SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, @@ -777,24 +780,11 @@ SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, assert(OpNo == 2 && "Different operand and result vector types?"); // Promote the index. - SDValue Idx = N->getOperand(2); - Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); + SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), N->getOperand(1), Idx); } -SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { - SDValue In = GetPromotedInteger(N->getOperand(0)); - MVT OpVT = N->getOperand(0).getValueType(); - if (N->getOpcode() == ISD::UINT_TO_FP) - In = DAG.getZeroExtendInReg(In, OpVT); - else - In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), - In, DAG.getValueType(OpVT)); - - return DAG.UpdateNodeOperands(SDValue(N, 0), In); -} - SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { SDValue NewOps[6]; NewOps[0] = N->getOperand(0); @@ -819,8 +809,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { // around the problem. MVT SVT = TLI.getSetCCResultType(N->getOperand(1)); assert(isTypeLegal(SVT) && "Illegal SetCC type!"); - assert(Cond.getValueSizeInBits() <= SVT.getSizeInBits() && - "Unexpected SetCC type!"); + assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!"); // Make sure the extra bits conform to getSetCCResultContents. There are // two sets of extra bits: those in Cond, which come from type promotion, @@ -888,6 +877,11 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { Op, DAG.getValueType(N->getOperand(0).getValueType())); } +SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { + return DAG.UpdateNodeOperands(SDValue(N, 0), + SExtPromotedInteger(N->getOperand(0))); +} + SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); @@ -910,6 +904,11 @@ SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); } +SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { + return DAG.UpdateNodeOperands(SDValue(N, 0), + ZExtPromotedInteger(N->getOperand(0))); +} + SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); @@ -960,6 +959,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; + case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; @@ -1027,7 +1027,8 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, } else if (Amt == NVTBits) { Lo = DAG.getConstant(0, NVT); Hi = InL; - } else if (Amt == 1) { + } else if (Amt == 1 && + TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) { // Emit this X << 1 as X+X. SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); SDValue LoOps[2] = { InL, InL }; @@ -1173,7 +1174,6 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, GetExpandedInteger(N->getOperand(1), RHSL, RHSH); MVT NVT = LHSL.getValueType(); - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); SDValue LoOps[2] = { LHSL, RHSL }; SDValue HiOps[3] = { LHSH, RHSH }; @@ -1187,6 +1187,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, TLI.getTypeToExpandTo(NVT)); if (hasCarry) { + SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); if (N->getOpcode() == ISD::ADD) { Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); @@ -1198,8 +1199,8 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, } } else { if (N->getOpcode() == ISD::ADD) { - Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2); - Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2); + Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); + Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0], ISD::SETULT); SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, @@ -1211,9 +1212,10 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, DAG.getConstant(1, NVT), Carry1); Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); } else { - Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2); - Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2); - SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); + Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); + Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); + SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]), + LoOps[0], LoOps[1], ISD::SETULT); SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, DAG.getConstant(1, NVT), DAG.getConstant(0, NVT)); @@ -1708,7 +1710,7 @@ void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = N->getOperand(0); if (Op.getValueType().bitsLE(NVT)) { - // The low part is sign extension of the input (which degenerates to a copy). + // The low part is sign extension of the input (degenerates to a copy). Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); // The high part is obtained by SRA'ing all but one of the bits of low part. unsigned LoSize = NVT.getSizeInBits(); @@ -1822,7 +1824,7 @@ void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = N->getOperand(0); if (Op.getValueType().bitsLE(NVT)) { - // The low part is zero extension of the input (which degenerates to a copy). + // The low part is zero extension of the input (degenerates to a copy). Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); Hi = DAG.getConstant(0, NVT); // The high part is just a zero. } else {