X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FScheduleDAG.cpp;h=f506b3ebfba4c0f4de846874c02e8801799739ab;hb=534bcfb270d25d2a29759d19981443fee7260e94;hp=a6e32b2bfad142269b8c9ef85682aa7a3df1a9e2;hpb=9efce638d307b2c71bd7f0258d47501661434c27;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index a6e32b2bfad..f506b3ebfba 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by James M. Laskey and is distributed under the -// University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -18,7 +18,7 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" @@ -27,25 +27,14 @@ #include "llvm/Support/MathExtras.h" using namespace llvm; - -/// getPhysicalRegisterRegClass - Returns the Register Class of a physical -/// register. -static const TargetRegisterClass *getPhysicalRegisterRegClass( - const MRegisterInfo *MRI, - MVT::ValueType VT, - unsigned reg) { - assert(MRegisterInfo::isPhysicalRegister(reg) && - "reg must be a physical register"); - // Pick the register class of the right type that contains this physreg. - for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(), - E = MRI->regclass_end(); I != E; ++I) - if ((*I)->hasType(VT) && (*I)->contains(reg)) - return *I; - assert(false && "Couldn't find the register class"); - return 0; +ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, + const TargetMachine &tm) + : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) { + TII = TM.getInstrInfo(); + MRI = TM.getRegisterInfo(); + ConstPool = BB->getParent()->getConstantPool(); } - /// CheckForPhysRegDependency - Check if the dependency between def and use of /// a specified operand is a physical register dependency. If so, returns the /// register and the cost of copying the register. @@ -67,7 +56,7 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op, II.ImplicitDefs[ResNo - II.numDefs] == Reg) { PhysReg = Reg; const TargetRegisterClass *RC = - getPhysicalRegisterRegClass(MRI, Def->getValueType(ResNo), Reg); + MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg); Cost = RC->getCopyCost(); } } @@ -81,11 +70,12 @@ SUnit *ScheduleDAG::Clone(SUnit *Old) { SU->Latency = Old->Latency; SU->isTwoAddress = Old->isTwoAddress; SU->isCommutable = Old->isCommutable; - SU->hasImplicitDefs = Old->hasImplicitDefs; + SU->hasPhysRegDefs = Old->hasPhysRegDefs; SUnitMap[Old->Node].push_back(SU); return SU; } + /// BuildSchedUnits - Build SUnits from the selection dag that we are input. /// This SUnit graph is similar to the SelectionDAG, but represents flagged /// together nodes with a single SUnit. @@ -95,8 +85,6 @@ void ScheduleDAG::BuildSchedUnits() { // invalidated. SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end())); - const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); - for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(), E = DAG.allnodes_end(); NI != E; ++NI) { if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. @@ -149,32 +137,8 @@ void ScheduleDAG::BuildSchedUnits() { // Update the SUnit NodeSUnit->Node = N; SUnitMap[N].push_back(NodeSUnit); - - // Compute the latency for the node. We use the sum of the latencies for - // all nodes flagged together into this SUnit. - if (InstrItins.isEmpty()) { - // No latency information. - NodeSUnit->Latency = 1; - } else { - NodeSUnit->Latency = 0; - if (N->isTargetOpcode()) { - unsigned SchedClass = TII->getSchedClass(N->getTargetOpcode()); - InstrStage *S = InstrItins.begin(SchedClass); - InstrStage *E = InstrItins.end(SchedClass); - for (; S != E; ++S) - NodeSUnit->Latency += S->Cycles; - } - for (unsigned i = 0, e = NodeSUnit->FlaggedNodes.size(); i != e; ++i) { - SDNode *FNode = NodeSUnit->FlaggedNodes[i]; - if (FNode->isTargetOpcode()) { - unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode()); - InstrStage *S = InstrItins.begin(SchedClass); - InstrStage *E = InstrItins.end(SchedClass); - for (; S != E; ++S) - NodeSUnit->Latency += S->Cycles; - } - } - } + + ComputeLatency(NodeSUnit); } // Pass 2: add the preds, succs, etc. @@ -185,8 +149,6 @@ void ScheduleDAG::BuildSchedUnits() { if (MainNode->isTargetOpcode()) { unsigned Opc = MainNode->getTargetOpcode(); const TargetInstrDescriptor &TID = TII->get(Opc); - if (TID.ImplicitDefs) - SU->hasImplicitDefs = true; for (unsigned i = 0; i != TID.numOperands; ++i) { if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { SU->isTwoAddress = true; @@ -203,8 +165,10 @@ void ScheduleDAG::BuildSchedUnits() { for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) { SDNode *N = SU->FlaggedNodes[n]; - if (N->isTargetOpcode() && TII->getImplicitDefs(N->getTargetOpcode())) - SU->hasImplicitDefs = true; + if (N->isTargetOpcode() && + TII->getImplicitDefs(N->getTargetOpcode()) && + CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode())) + SU->hasPhysRegDefs = true; for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { SDNode *OpN = N->getOperand(i).Val; @@ -232,6 +196,36 @@ void ScheduleDAG::BuildSchedUnits() { return; } +void ScheduleDAG::ComputeLatency(SUnit *SU) { + const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); + + // Compute the latency for the node. We use the sum of the latencies for + // all nodes flagged together into this SUnit. + if (InstrItins.isEmpty()) { + // No latency information. + SU->Latency = 1; + } else { + SU->Latency = 0; + if (SU->Node->isTargetOpcode()) { + unsigned SchedClass = TII->getSchedClass(SU->Node->getTargetOpcode()); + InstrStage *S = InstrItins.begin(SchedClass); + InstrStage *E = InstrItins.end(SchedClass); + for (; S != E; ++S) + SU->Latency += S->Cycles; + } + for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) { + SDNode *FNode = SU->FlaggedNodes[i]; + if (FNode->isTargetOpcode()) { + unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode()); + InstrStage *S = InstrItins.begin(SchedClass); + InstrStage *E = InstrItins.end(SchedClass); + for (; S != E; ++S) + SU->Latency += S->Cycles; + } + } + } +} + void ScheduleDAG::CalculateDepths() { std::vector > WorkList; for (unsigned i = 0, e = SUnits.size(); i != e; ++i) @@ -339,7 +333,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, } else { for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { SDOperand Op = Use->getOperand(i); - if (Op.Val != Node) + if (Op.Val != Node || Op.ResNo != ResNo) continue; MVT::ValueType VT = Node->getValueType(Op.ResNo); if (VT != MVT::Other && VT != MVT::Flag) @@ -354,9 +348,9 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, const TargetRegisterClass *TRC = 0; // Figure out the register class to create for the destreg. if (VRBase) - TRC = RegMap->getRegClass(VRBase); + TRC = RegInfo.getRegClass(VRBase); else - TRC = getPhysicalRegisterRegClass(MRI, Node->getValueType(ResNo), SrcReg); + TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg); // If all uses are reading from the src physical register and copying the // register is either impossible or very expensive, then don't create a copy. @@ -364,7 +358,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, VRBase = SrcReg; } else { // Create the reg, emit the copy. - VRBase = RegMap->createVirtualRegister(TRC); + VRBase = RegInfo.createVirtualRegister(TRC); MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC); } @@ -392,7 +386,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, unsigned Reg = cast(Use->getOperand(1))->getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) { VRBase = Reg; - MI->addRegOperand(Reg, true); + MI->addOperand(MachineOperand::CreateReg(Reg, true)); break; } } @@ -403,8 +397,8 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, if (VRBase == 0) { const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i); assert(RC && "Isn't a register operand!"); - VRBase = RegMap->createVirtualRegister(RC); - MI->addRegOperand(VRBase, true); + VRBase = RegInfo.createVirtualRegister(RC); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); } bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase)); @@ -442,7 +436,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); bool isOptDef = (IIOpNum < TID->numOperands) ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false; - MI->addRegOperand(VReg, isOptDef); + MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -450,7 +444,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); - const TargetRegisterClass *VRC = RegMap->getRegClass(VReg); + const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg); if (VRC != RC) { cerr << "Register class of operand and regclass of use don't agree!\n"; #ifndef NDEBUG @@ -467,26 +461,19 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, abort(); } } - } else if (ConstantSDNode *C = - dyn_cast(Op)) { - MI->addImmOperand(C->getValue()); - } else if (RegisterSDNode *R = - dyn_cast(Op)) { - MI->addRegOperand(R->getReg(), false); - } else if (GlobalAddressSDNode *TGA = - dyn_cast(Op)) { - MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset()); - } else if (BasicBlockSDNode *BB = - dyn_cast(Op)) { - MI->addMachineBasicBlockOperand(BB->getBasicBlock()); - } else if (FrameIndexSDNode *FI = - dyn_cast(Op)) { - MI->addFrameIndexOperand(FI->getIndex()); - } else if (JumpTableSDNode *JT = - dyn_cast(Op)) { - MI->addJumpTableIndexOperand(JT->getIndex()); - } else if (ConstantPoolSDNode *CP = - dyn_cast(Op)) { + } else if (ConstantSDNode *C = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateImm(C->getValue())); + } else if (RegisterSDNode *R = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); + } else if (GlobalAddressSDNode *TGA = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset())); + } else if (BasicBlockSDNode *BB = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock())); + } else if (FrameIndexSDNode *FI = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); + } else if (JumpTableSDNode *JT = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateJTI(JT->getIndex())); + } else if (ConstantPoolSDNode *CP = dyn_cast(Op)) { int Offset = CP->getOffset(); unsigned Align = CP->getAlignment(); const Type *Type = CP->getType(); @@ -495,7 +482,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type); if (Align == 0) { // Alignment of vector types. FIXME! - Align = TM.getTargetData()->getTypeSize(Type); + Align = TM.getTargetData()->getABITypeSize(Type); Align = Log2_64(Align); } } @@ -505,16 +492,15 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align); else Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align); - MI->addConstantPoolIndexOperand(Idx, Offset); - } else if (ExternalSymbolSDNode *ES = - dyn_cast(Op)) { - MI->addExternalSymbolOperand(ES->getSymbol()); + MI->addOperand(MachineOperand::CreateCPI(Idx, Offset)); + } else if (ExternalSymbolSDNode *ES = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateES(ES->getSymbol())); } else { assert(Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Flag && "Chain and flag operands should occur at end of operand list!"); unsigned VReg = getVR(Op, VRBaseMap); - MI->addRegOperand(VReg, false); + MI->addOperand(MachineOperand::CreateReg(VReg, false)); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -522,7 +508,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); - assert(RegMap->getRegClass(VReg) == RC && + assert(RegInfo.getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"); } } @@ -580,33 +566,30 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, // TODO: If the node is a use of a CopyFromReg from a physical register // fold the extract into the copy now - // TODO: Add tracking info to SSARegMap of which vregs are subregs - // to allow coalescing in the allocator - // Create the extract_subreg machine instruction. MachineInstr *MI = new MachineInstr(BB, TII->get(TargetInstrInfo::EXTRACT_SUBREG)); // Figure out the register class to create for the destreg. unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); - const TargetRegisterClass *TRC = RegMap->getRegClass(VReg); + const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg); const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx); if (VRBase) { // Grab the destination register const TargetRegisterClass *DRC = 0; - DRC = RegMap->getRegClass(VRBase); + DRC = RegInfo.getRegClass(VRBase); assert(SRC == DRC && "Source subregister and destination must have the same class"); } else { // Create the reg - VRBase = RegMap->createVirtualRegister(SRC); + VRBase = RegInfo.createVirtualRegister(SRC); } // Add def, source, and subreg index - MI->addRegOperand(VRBase, true); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); - MI->addImmOperand(SubIdx); + MI->addOperand(MachineOperand::CreateImm(SubIdx)); } else if (Opc == TargetInstrInfo::INSERT_SUBREG) { assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) && @@ -623,7 +606,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, SubIdx = cast(Node->getOperand(2))->getValue(); } - // TODO: Add tracking info to SSARegMap of which vregs are subregs + // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs // to allow coalescing in the allocator // If the node is only used by a CopyToReg and the dest reg is a vreg, use @@ -650,20 +633,19 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, // Figure out the register class to create for the destreg. const TargetRegisterClass *TRC = 0; if (VRBase) { - TRC = RegMap->getRegClass(VRBase); + TRC = RegInfo.getRegClass(VRBase); } else { - TRC = getSuperregRegisterClass(RegMap->getRegClass(SubReg), - SubIdx, + TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx, Node->getValueType(0)); assert(TRC && "Couldn't determine register class for insert_subreg"); - VRBase = RegMap->createVirtualRegister(TRC); // Create the reg + VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg } - MI->addRegOperand(VRBase, true); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); if (!isUndefInput) AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap); - MI->addImmOperand(SubIdx); + MI->addOperand(MachineOperand::CreateImm(SubIdx)); } else assert(0 && "Node is not a subreg insert or extract"); @@ -764,10 +746,10 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, const TargetRegisterClass *TRC = 0; // Get the target register class if (MRegisterInfo::isVirtualRegister(InReg)) - TRC = RegMap->getRegClass(InReg); + TRC = RegInfo.getRegClass(InReg); else - TRC = getPhysicalRegisterRegClass(MRI, - Node->getOperand(2).getValueType(), + TRC = + MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), InReg); MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC); } @@ -790,14 +772,14 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, // Add the asm string as an external symbol operand. const char *AsmStr = cast(Node->getOperand(1))->getSymbol(); - MI->addExternalSymbolOperand(AsmStr); + MI->addOperand(MachineOperand::CreateES(AsmStr)); // Add all of the operand registers to the instruction. for (unsigned i = 2; i != NumOps;) { unsigned Flags = cast(Node->getOperand(i))->getValue(); unsigned NumVals = Flags >> 3; - MI->addImmOperand(Flags); + MI->addOperand(MachineOperand::CreateImm(Flags)); ++i; // Skip the ID value. switch (Flags & 7) { @@ -805,24 +787,27 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, case 1: // Use of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, false); + MI->addOperand(MachineOperand::CreateReg(Reg, false)); } break; case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, true); + MI->addOperand(MachineOperand::CreateReg(Reg, true)); } break; case 3: { // Immediate. for (; NumVals; --NumVals, ++i) { if (ConstantSDNode *CS = dyn_cast(Node->getOperand(i))) { - MI->addImmOperand(CS->getValue()); + MI->addOperand(MachineOperand::CreateImm(CS->getValue())); + } else if (GlobalAddressSDNode *GA = + dyn_cast(Node->getOperand(i))) { + MI->addOperand(MachineOperand::CreateGA(GA->getGlobal(), + GA->getOffset())); } else { - GlobalAddressSDNode *GA = - cast(Node->getOperand(i)); - MI->addGlobalAddressOperand(GA->getGlobal(), GA->getOffset()); + BasicBlockSDNode *BB =cast(Node->getOperand(i)); + MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock())); } } break; @@ -845,17 +830,50 @@ void ScheduleDAG::EmitNoop() { TII->insertNoop(*BB, BB->end()); } +void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap &VRBaseMap) { + for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); + I != E; ++I) { + if (I->isCtrl) continue; // ignore chain preds + if (!I->Dep->Node) { + // Copy to physical register. + DenseMap::iterator VRI = VRBaseMap.find(I->Dep); + assert(VRI != VRBaseMap.end() && "Node emitted out of order - late"); + // Find the destination physical register. + unsigned Reg = 0; + for (SUnit::const_succ_iterator II = SU->Succs.begin(), + EE = SU->Succs.end(); II != EE; ++II) { + if (I->Reg) { + Reg = I->Reg; + break; + } + } + assert(I->Reg && "Unknown physical register!"); + MRI->copyRegToReg(*BB, BB->end(), Reg, VRI->second, + SU->CopyDstRC, SU->CopySrcRC); + } else { + // Copy from physical register. + assert(I->Reg && "Unknown physical register!"); + unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC); + bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)); + assert(isNew && "Node emitted out of order - early"); + MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, + SU->CopyDstRC, SU->CopySrcRC); + } + break; + } +} + /// EmitSchedule - Emit the machine code in scheduled order. void ScheduleDAG::EmitSchedule() { // If this is the first basic block in the function, and if it has live ins // that need to be copied into vregs, emit the copies into the top of the // block before emitting the code for the block. MachineFunction &MF = DAG.getMachineFunction(); - if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) { - for (MachineFunction::livein_iterator LI = MF.livein_begin(), - E = MF.livein_end(); LI != E; ++LI) + if (&MF.front() == BB) { + for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(), + E = RegInfo.livein_end(); LI != E; ++LI) if (LI->second) { - const TargetRegisterClass *RC = RegMap->getRegClass(LI->second); + const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second); MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, LI->first, RC, RC); } @@ -864,11 +882,15 @@ void ScheduleDAG::EmitSchedule() { // Finally, emit the code for all of the scheduled instructions. DenseMap VRBaseMap; + DenseMap CopyVRBaseMap; for (unsigned i = 0, e = Sequence.size(); i != e; i++) { if (SUnit *SU = Sequence[i]) { for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j) EmitNode(SU->FlaggedNodes[j], SU->InstanceNo, VRBaseMap); - EmitNode(SU->Node, SU->InstanceNo, VRBaseMap); + if (SU->Node) + EmitNode(SU->Node, SU->InstanceNo, VRBaseMap); + else + EmitCrossRCCopy(SU, CopyVRBaseMap); } else { // Null SUnit* is a noop. EmitNoop(); @@ -890,11 +912,6 @@ void ScheduleDAG::dumpSchedule() const { /// Run - perform scheduling. /// MachineBasicBlock *ScheduleDAG::Run() { - TII = TM.getInstrInfo(); - MRI = TM.getRegisterInfo(); - RegMap = BB->getParent()->getSSARegMap(); - ConstPool = BB->getParent()->getConstantPool(); - Schedule(); return BB; } @@ -903,7 +920,10 @@ MachineBasicBlock *ScheduleDAG::Run() { /// a group of nodes flagged together. void SUnit::dump(const SelectionDAG *G) const { cerr << "SU(" << NodeNum << "): "; - Node->dump(G); + if (Node) + Node->dump(G); + else + cerr << "CROSS RC COPY "; cerr << "\n"; if (FlaggedNodes.size() != 0) { for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) { @@ -919,8 +939,6 @@ void SUnit::dumpAll(const SelectionDAG *G) const { cerr << " # preds left : " << NumPredsLeft << "\n"; cerr << " # succs left : " << NumSuccsLeft << "\n"; - cerr << " # chain preds left : " << NumChainPredsLeft << "\n"; - cerr << " # chain succs left : " << NumChainSuccsLeft << "\n"; cerr << " Latency : " << Latency << "\n"; cerr << " Depth : " << Depth << "\n"; cerr << " Height : " << Height << "\n";