X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FScheduleDAG.cpp;h=f506b3ebfba4c0f4de846874c02e8801799739ab;hb=534bcfb270d25d2a29759d19981443fee7260e94;hp=b616b7e4825818d503cddaf74a3b5cf34b88a246;hpb=f10c973797cf79da802f9b0118543cbd50954c9c;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index b616b7e4825..f506b3ebfba 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by James M. Laskey and is distributed under the -// University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -18,7 +18,7 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" @@ -27,6 +27,13 @@ #include "llvm/Support/MathExtras.h" using namespace llvm; +ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, + const TargetMachine &tm) + : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) { + TII = TM.getInstrInfo(); + MRI = TM.getRegisterInfo(); + ConstPool = BB->getParent()->getConstantPool(); +} /// CheckForPhysRegDependency - Check if the dependency between def and use of /// a specified operand is a physical register dependency. If so, returns the @@ -326,7 +333,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, } else { for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { SDOperand Op = Use->getOperand(i); - if (Op.Val != Node) + if (Op.Val != Node || Op.ResNo != ResNo) continue; MVT::ValueType VT = Node->getValueType(Op.ResNo); if (VT != MVT::Other && VT != MVT::Flag) @@ -341,7 +348,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, const TargetRegisterClass *TRC = 0; // Figure out the register class to create for the destreg. if (VRBase) - TRC = RegMap->getRegClass(VRBase); + TRC = RegInfo.getRegClass(VRBase); else TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg); @@ -351,7 +358,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, VRBase = SrcReg; } else { // Create the reg, emit the copy. - VRBase = RegMap->createVirtualRegister(TRC); + VRBase = RegInfo.createVirtualRegister(TRC); MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC); } @@ -379,7 +386,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, unsigned Reg = cast(Use->getOperand(1))->getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) { VRBase = Reg; - MI->addRegOperand(Reg, true); + MI->addOperand(MachineOperand::CreateReg(Reg, true)); break; } } @@ -390,8 +397,8 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, if (VRBase == 0) { const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i); assert(RC && "Isn't a register operand!"); - VRBase = RegMap->createVirtualRegister(RC); - MI->addRegOperand(VRBase, true); + VRBase = RegInfo.createVirtualRegister(RC); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); } bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase)); @@ -429,7 +436,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); bool isOptDef = (IIOpNum < TID->numOperands) ? (TID->OpInfo[IIOpNum].Flags & M_OPTIONAL_DEF_OPERAND) : false; - MI->addRegOperand(VReg, isOptDef); + MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -437,7 +444,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); - const TargetRegisterClass *VRC = RegMap->getRegClass(VReg); + const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg); if (VRC != RC) { cerr << "Register class of operand and regclass of use don't agree!\n"; #ifndef NDEBUG @@ -454,26 +461,19 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, abort(); } } - } else if (ConstantSDNode *C = - dyn_cast(Op)) { - MI->addImmOperand(C->getValue()); - } else if (RegisterSDNode *R = - dyn_cast(Op)) { - MI->addRegOperand(R->getReg(), false); - } else if (GlobalAddressSDNode *TGA = - dyn_cast(Op)) { - MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset()); - } else if (BasicBlockSDNode *BB = - dyn_cast(Op)) { - MI->addMachineBasicBlockOperand(BB->getBasicBlock()); - } else if (FrameIndexSDNode *FI = - dyn_cast(Op)) { - MI->addFrameIndexOperand(FI->getIndex()); - } else if (JumpTableSDNode *JT = - dyn_cast(Op)) { - MI->addJumpTableIndexOperand(JT->getIndex()); - } else if (ConstantPoolSDNode *CP = - dyn_cast(Op)) { + } else if (ConstantSDNode *C = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateImm(C->getValue())); + } else if (RegisterSDNode *R = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); + } else if (GlobalAddressSDNode *TGA = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset())); + } else if (BasicBlockSDNode *BB = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock())); + } else if (FrameIndexSDNode *FI = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); + } else if (JumpTableSDNode *JT = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateJTI(JT->getIndex())); + } else if (ConstantPoolSDNode *CP = dyn_cast(Op)) { int Offset = CP->getOffset(); unsigned Align = CP->getAlignment(); const Type *Type = CP->getType(); @@ -482,7 +482,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type); if (Align == 0) { // Alignment of vector types. FIXME! - Align = TM.getTargetData()->getTypeSize(Type); + Align = TM.getTargetData()->getABITypeSize(Type); Align = Log2_64(Align); } } @@ -492,16 +492,15 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align); else Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align); - MI->addConstantPoolIndexOperand(Idx, Offset); - } else if (ExternalSymbolSDNode *ES = - dyn_cast(Op)) { - MI->addExternalSymbolOperand(ES->getSymbol()); + MI->addOperand(MachineOperand::CreateCPI(Idx, Offset)); + } else if (ExternalSymbolSDNode *ES = dyn_cast(Op)) { + MI->addOperand(MachineOperand::CreateES(ES->getSymbol())); } else { assert(Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Flag && "Chain and flag operands should occur at end of operand list!"); unsigned VReg = getVR(Op, VRBaseMap); - MI->addRegOperand(VReg, false); + MI->addOperand(MachineOperand::CreateReg(VReg, false)); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -509,7 +508,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); - assert(RegMap->getRegClass(VReg) == RC && + assert(RegInfo.getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"); } } @@ -567,33 +566,30 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, // TODO: If the node is a use of a CopyFromReg from a physical register // fold the extract into the copy now - // TODO: Add tracking info to SSARegMap of which vregs are subregs - // to allow coalescing in the allocator - // Create the extract_subreg machine instruction. MachineInstr *MI = new MachineInstr(BB, TII->get(TargetInstrInfo::EXTRACT_SUBREG)); // Figure out the register class to create for the destreg. unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); - const TargetRegisterClass *TRC = RegMap->getRegClass(VReg); + const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg); const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx); if (VRBase) { // Grab the destination register const TargetRegisterClass *DRC = 0; - DRC = RegMap->getRegClass(VRBase); + DRC = RegInfo.getRegClass(VRBase); assert(SRC == DRC && "Source subregister and destination must have the same class"); } else { // Create the reg - VRBase = RegMap->createVirtualRegister(SRC); + VRBase = RegInfo.createVirtualRegister(SRC); } // Add def, source, and subreg index - MI->addRegOperand(VRBase, true); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); - MI->addImmOperand(SubIdx); + MI->addOperand(MachineOperand::CreateImm(SubIdx)); } else if (Opc == TargetInstrInfo::INSERT_SUBREG) { assert((Node->getNumOperands() == 2 || Node->getNumOperands() == 3) && @@ -610,7 +606,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, SubIdx = cast(Node->getOperand(2))->getValue(); } - // TODO: Add tracking info to SSARegMap of which vregs are subregs + // TODO: Add tracking info to MachineRegisterInfo of which vregs are subregs // to allow coalescing in the allocator // If the node is only used by a CopyToReg and the dest reg is a vreg, use @@ -637,20 +633,19 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, // Figure out the register class to create for the destreg. const TargetRegisterClass *TRC = 0; if (VRBase) { - TRC = RegMap->getRegClass(VRBase); + TRC = RegInfo.getRegClass(VRBase); } else { - TRC = getSuperregRegisterClass(RegMap->getRegClass(SubReg), - SubIdx, + TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx, Node->getValueType(0)); assert(TRC && "Couldn't determine register class for insert_subreg"); - VRBase = RegMap->createVirtualRegister(TRC); // Create the reg + VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg } - MI->addRegOperand(VRBase, true); + MI->addOperand(MachineOperand::CreateReg(VRBase, true)); AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); if (!isUndefInput) AddOperand(MI, Node->getOperand(1), 0, 0, VRBaseMap); - MI->addImmOperand(SubIdx); + MI->addOperand(MachineOperand::CreateImm(SubIdx)); } else assert(0 && "Node is not a subreg insert or extract"); @@ -751,7 +746,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, const TargetRegisterClass *TRC = 0; // Get the target register class if (MRegisterInfo::isVirtualRegister(InReg)) - TRC = RegMap->getRegClass(InReg); + TRC = RegInfo.getRegClass(InReg); else TRC = MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), @@ -777,14 +772,14 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, // Add the asm string as an external symbol operand. const char *AsmStr = cast(Node->getOperand(1))->getSymbol(); - MI->addExternalSymbolOperand(AsmStr); + MI->addOperand(MachineOperand::CreateES(AsmStr)); // Add all of the operand registers to the instruction. for (unsigned i = 2; i != NumOps;) { unsigned Flags = cast(Node->getOperand(i))->getValue(); unsigned NumVals = Flags >> 3; - MI->addImmOperand(Flags); + MI->addOperand(MachineOperand::CreateImm(Flags)); ++i; // Skip the ID value. switch (Flags & 7) { @@ -792,24 +787,27 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, case 1: // Use of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, false); + MI->addOperand(MachineOperand::CreateReg(Reg, false)); } break; case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, true); + MI->addOperand(MachineOperand::CreateReg(Reg, true)); } break; case 3: { // Immediate. for (; NumVals; --NumVals, ++i) { if (ConstantSDNode *CS = dyn_cast(Node->getOperand(i))) { - MI->addImmOperand(CS->getValue()); + MI->addOperand(MachineOperand::CreateImm(CS->getValue())); + } else if (GlobalAddressSDNode *GA = + dyn_cast(Node->getOperand(i))) { + MI->addOperand(MachineOperand::CreateGA(GA->getGlobal(), + GA->getOffset())); } else { - GlobalAddressSDNode *GA = - cast(Node->getOperand(i)); - MI->addGlobalAddressOperand(GA->getGlobal(), GA->getOffset()); + BasicBlockSDNode *BB =cast(Node->getOperand(i)); + MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock())); } } break; @@ -855,7 +853,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap &VRBaseM } else { // Copy from physical register. assert(I->Reg && "Unknown physical register!"); - unsigned VRBase = RegMap->createVirtualRegister(SU->CopyDstRC); + unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC); bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)); assert(isNew && "Node emitted out of order - early"); MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg, @@ -872,10 +870,10 @@ void ScheduleDAG::EmitSchedule() { // block before emitting the code for the block. MachineFunction &MF = DAG.getMachineFunction(); if (&MF.front() == BB) { - for (MachineFunction::livein_iterator LI = MF.livein_begin(), - E = MF.livein_end(); LI != E; ++LI) + for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(), + E = RegInfo.livein_end(); LI != E; ++LI) if (LI->second) { - const TargetRegisterClass *RC = RegMap->getRegClass(LI->second); + const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second); MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second, LI->first, RC, RC); } @@ -914,11 +912,6 @@ void ScheduleDAG::dumpSchedule() const { /// Run - perform scheduling. /// MachineBasicBlock *ScheduleDAG::Run() { - TII = TM.getInstrInfo(); - MRI = TM.getRegisterInfo(); - RegMap = BB->getParent()->getSSARegMap(); - ConstPool = BB->getParent()->getConstantPool(); - Schedule(); return BB; }