X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FScheduleDAGEmit.cpp;h=4ea29063ab58eb1163aed05427129d42dd3fb6db;hb=49c18cce976c158e86f54c681dff21bb81640fb8;hp=8471a9a84f2043d0ad4a65d54b45510cfc70d436;hpb=8a11053f3ca7efb29312c4293c4fdb5d2ca3e20f;p=oota-llvm.git

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index 8471a9a84f2..4ea29063ab5 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -65,6 +65,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
   // the CopyToReg'd destination register instead of creating a new vreg.
   bool MatchReg = true;
+  const TargetRegisterClass *UseRC = NULL;
   for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
        UI != E; ++UI) {
     SDNode *User = *UI;
@@ -84,8 +85,19 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
         if (Op.getNode() != Node || Op.getResNo() != ResNo)
           continue;
         MVT VT = Node->getValueType(Op.getResNo());
-        if (VT != MVT::Other && VT != MVT::Flag)
-          Match = false;
+        if (VT == MVT::Other || VT == MVT::Flag)
+          continue;
+        Match = false;
+        if (User->isMachineOpcode()) {
+          const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
+          const TargetRegisterClass *RC =
+            getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
+          if (!UseRC)
+            UseRC = RC;
+          else if (RC)
+            assert(UseRC == RC &&
+                   "Multiple uses expecting different register classes!");
+        }
       }
     }
     MatchReg &= Match;
@@ -93,14 +105,18 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
       break;
   }
 
+  MVT VT = Node->getValueType(ResNo);
   const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
-  SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, Node->getValueType(ResNo));
+  SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
   
   // Figure out the register class to create for the destreg.
   if (VRBase) {
     DstRC = MRI.getRegClass(VRBase);
+  } else if (UseRC) {
+    assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
+    DstRC = UseRC;
   } else {
-    DstRC = TLI->getRegClassFor(Node->getValueType(ResNo));
+    DstRC = TLI->getRegClassFor(VT);
   }
     
   // If all uses are reading from the src physical register and copying the
@@ -110,7 +126,10 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
   } else {
     // Create the reg, emit the copy.
     VRBase = MRI.createVirtualRegister(DstRC);
-    TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
+    bool Emitted =
+      TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
+    Emitted = Emitted; // Silence compiler warning.
+    assert(Emitted && "Unable to issue a copy instruction!");
   }
 
   SDValue Op(Node, ResNo);
@@ -254,9 +273,9 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
     }
 #endif
   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
-    MI->addOperand(MachineOperand::CreateImm(C->getValue()));
+    MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
-    ConstantFP *CFP = ConstantFP::get(F->getValueAPF());
+    const ConstantFP *CFP = F->getConstantFPValue();
     MI->addOperand(MachineOperand::CreateFPImm(CFP));
   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
     MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
@@ -363,7 +382,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
   }
   
   if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
-    unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
+    unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 
     // Create the extract_subreg machine instruction.
     MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
@@ -397,7 +416,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
     SDValue N1 = Node->getOperand(1);
     SDValue N2 = Node->getOperand(2);
     unsigned SubReg = getVR(N1, VRBaseMap);
-    unsigned SubIdx = cast<ConstantSDNode>(N2)->getValue();
+    unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
     
       
     // Figure out the register class to create for the destreg.
@@ -419,7 +438,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
     // is an implicit value immediate, otherwise it's a register
     if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
-      MI->addOperand(MachineOperand::CreateImm(SD->getValue()));
+      MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
     } else
       AddOperand(MI, N0, 0, 0, VRBaseMap);
     // Add the subregster being inserted
@@ -577,7 +596,8 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
       
     // Add all of the operand registers to the instruction.
     for (unsigned i = 2; i != NumOps;) {
-      unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
+      unsigned Flags =
+        cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
       unsigned NumVals = Flags >> 3;
         
       MI->addOperand(MachineOperand::CreateImm(Flags));
@@ -591,6 +611,13 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
           MI->addOperand(MachineOperand::CreateReg(Reg, true));
         }
         break;
+      case 6:   // Def of earlyclobber register.
+        for (; NumVals; --NumVals, ++i) {
+          unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+          MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 
+                                                   false, 0, true));
+        }
+        break;
       case 1:  // Use of register.
       case 3:  // Immediate.
       case 4:  // Addressing mode.