X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FScheduleDAGRRList.cpp;h=a50dd7b7c5d37c33476b292f4d95dfcdd71d2f3b;hb=2f1d3108e481758da66662f72673741da86312da;hp=0575b41d1f554adbad4a8c93da899b70bf22f833;hpb=f10c973797cf79da802f9b0118543cbd50954c9c;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 0575b41d1f5..a50dd7b7c5d 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Evan Cheng and is distributed under the -// University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -18,22 +18,23 @@ #define DEBUG_TYPE "pre-RA-sched" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/CodeGen/SSARegMap.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/PriorityQueue.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include -#include #include "llvm/Support/CommandLine.h" using namespace llvm; -STATISTIC(NumBacktracks, "Number of times scheduler backtraced"); +STATISTIC(NumBacktracks, "Number of times scheduler backtracked"); STATISTIC(NumUnfolds, "Number of nodes unfolded"); STATISTIC(NumDups, "Number of duplicated nodes"); STATISTIC(NumCCCopies, "Number of cross class copies"); @@ -59,7 +60,6 @@ private: bool isBottomUp; /// AvailableQueue - The priority queue to use for the available SUnits. - ///a SchedulingPriorityQueue *AvailableQueue; /// LiveRegs / LiveRegDefs - A set of physical registers and their definition @@ -83,6 +83,24 @@ public: void Schedule(); + /// IsReachable - Checks if SU is reachable from TargetSU. + bool IsReachable(SUnit *SU, SUnit *TargetSU); + + /// willCreateCycle - Returns true if adding an edge from SU to TargetSU will + /// create a cycle. + bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); + + /// AddPred - This adds the specified node X as a predecessor of + /// the current node Y if not already. + /// This returns true if this is a new predecessor. + /// Updates the topological ordering if required. + bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial, + unsigned PhyReg = 0, int Cost = 1); + + /// RemovePred - This removes the specified node N from the predecessors of + /// the current node M. Updates the topological ordering if required. + bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isSpecial); + private: void ReleasePred(SUnit*, bool, unsigned); void ReleaseSucc(SUnit*, bool isChain, unsigned); @@ -100,6 +118,84 @@ private: void ListScheduleTopDown(); void ListScheduleBottomUp(); void CommuteNodesToReducePressure(); + + + /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it. + /// Updates the topological ordering if required. + SUnit *CreateNewSUnit(SDNode *N) { + SUnit *NewNode = NewSUnit(N); + // Update the topological ordering. + if (NewNode->NodeNum >= Node2Index.size()) + InitDAGTopologicalSorting(); + return NewNode; + } + + /// CreateClone - Creates a new SUnit from an existing one. + /// Updates the topological ordering if required. + SUnit *CreateClone(SUnit *N) { + SUnit *NewNode = Clone(N); + // Update the topological ordering. + if (NewNode->NodeNum >= Node2Index.size()) + InitDAGTopologicalSorting(); + return NewNode; + } + + /// Functions for preserving the topological ordering + /// even after dynamic insertions of new edges. + /// This allows a very fast implementation of IsReachable. + + + /** + The idea of the algorithm is taken from + "Online algorithms for managing the topological order of + a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly + This is the MNR algorithm, which was first introduced by + A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in + "Maintaining a topological order under edge insertions". + + Short description of the algorithm: + + Topological ordering, ord, of a DAG maps each node to a topological + index so that for all edges X->Y it is the case that ord(X) < ord(Y). + + This means that if there is a path from the node X to the node Z, + then ord(X) < ord(Z). + + This property can be used to check for reachability of nodes: + if Z is reachable from X, then an insertion of the edge Z->X would + create a cycle. + + The algorithm first computes a topological ordering for the DAG by initializing + the Index2Node and Node2Index arrays and then tries to keep the ordering + up-to-date after edge insertions by reordering the DAG. + + On insertion of the edge X->Y, the algorithm first marks by calling DFS the + nodes reachable from Y, and then shifts them using Shift to lie immediately + after X in Index2Node. + */ + + /// InitDAGTopologicalSorting - create the initial topological + /// ordering from the DAG to be scheduled. + void InitDAGTopologicalSorting(); + + /// DFS - make a DFS traversal and mark all nodes affected by the + /// edge insertion. These nodes will later get new topological indexes + /// by means of the Shift method. + void DFS(SUnit *SU, int UpperBound, bool& HasLoop); + + /// Shift - reassign topological indexes for the nodes in the DAG + /// to preserve the topological ordering. + void Shift(BitVector& Visited, int LowerBound, int UpperBound); + + /// Allocate - assign the topological index to the node n. + void Allocate(int n, int index); + + /// Index2Node - Maps topological index to the node number. + std::vector Index2Node; + /// Node2Index - Maps the node number to its topological index. + std::vector Node2Index; + /// Visited - a set of nodes visited during a DFS traversal. + BitVector Visited; }; } // end anonymous namespace @@ -108,8 +204,8 @@ private: void ScheduleDAGRRList::Schedule() { DOUT << "********** List Scheduling **********\n"; - LiveRegDefs.resize(MRI->getNumRegs(), NULL); - LiveRegCycles.resize(MRI->getNumRegs(), 0); + LiveRegDefs.resize(TRI->getNumRegs(), NULL); + LiveRegCycles.resize(TRI->getNumRegs(), 0); // Build scheduling units. BuildSchedUnits(); @@ -118,8 +214,9 @@ void ScheduleDAGRRList::Schedule() { SUnits[su].dumpAll(&DAG)); CalculateDepths(); CalculateHeights(); + InitDAGTopologicalSorting(); - AvailableQueue->initNodes(SUnitMap, SUnits); + AvailableQueue->initNodes(SUnits); // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate. if (isBottomUp) @@ -144,19 +241,21 @@ void ScheduleDAGRRList::Schedule() { /// possible. It will be commuted when it is translated to a MI. void ScheduleDAGRRList::CommuteNodesToReducePressure() { SmallPtrSet OperandSeen; - for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node. + for (unsigned i = Sequence.size(); i != 0; ) { + --i; SUnit *SU = Sequence[i]; if (!SU || !SU->Node) continue; if (SU->isCommutable) { unsigned Opc = SU->Node->getTargetOpcode(); - unsigned NumRes = TII->getNumDefs(Opc); - unsigned NumOps = CountOperands(SU->Node); + const TargetInstrDesc &TID = TII->get(Opc); + unsigned NumRes = TID.getNumDefs(); + unsigned NumOps = TID.getNumOperands() - NumRes; for (unsigned j = 0; j != NumOps; ++j) { - if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1) + if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1) continue; SDNode *OpN = SU->Node->getOperand(j).Val; - SUnit *OpSU = SUnitMap[OpN][SU->InstanceNo]; + SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()]; if (OpSU && OperandSeen.count(OpSU) == 1) { // Ok, so SU is not the last use of OpSU, but SU is two-address so // it will clobber OpSU. Try to commute SU if no other source operands @@ -165,7 +264,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { for (unsigned k = 0; k < NumOps; ++k) { if (k != j) { OpN = SU->Node->getOperand(k).Val; - OpSU = SUnitMap[OpN][SU->InstanceNo]; + OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()]; if (OpSU && OperandSeen.count(OpSU) == 1) { DoCommute = false; break; @@ -184,7 +283,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { if (!I->isCtrl) - OperandSeen.insert(I->Dep); + OperandSeen.insert(I->Dep->OrigNode); } } } @@ -215,11 +314,8 @@ void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain, #endif if (PredSU->NumSuccsLeft == 0) { - // EntryToken has to go last! Special case it here. - if (!PredSU->Node || PredSU->Node->getOpcode() != ISD::EntryToken) { - PredSU->isAvailable = true; - AvailableQueue->push(PredSU); - } + PredSU->isAvailable = true; + AvailableQueue->push(PredSU); } } @@ -269,14 +365,14 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { /// CapturePred - This does the opposite of ReleasePred. Since SU is being /// unscheduled, incrcease the succ left count of its predecessors. Remove /// them from AvailableQueue if necessary. -void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { - PredSU->CycleBound = 0; +void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { + unsigned CycleBound = 0; for (SUnit::succ_iterator I = PredSU->Succs.begin(), E = PredSU->Succs.end(); I != E; ++I) { if (I->Dep == SU) continue; - PredSU->CycleBound = std::max(PredSU->CycleBound, - I->Dep->Cycle + PredSU->Latency); + CycleBound = std::max(CycleBound, + I->Dep->Cycle + PredSU->Latency); } if (PredSU->isAvailable) { @@ -285,6 +381,7 @@ void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { AvailableQueue->remove(PredSU); } + PredSU->CycleBound = CycleBound; ++PredSU->NumSuccsLeft; } @@ -327,36 +424,187 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { AvailableQueue->push(SU); } -// FIXME: This is probably too slow! -static void isReachable(SUnit *SU, SUnit *TargetSU, - SmallPtrSet &Visited, bool &Reached) { - if (Reached) return; - if (SU == TargetSU) { - Reached = true; - return; +/// IsReachable - Checks if SU is reachable from TargetSU. +bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) { + // If insertion of the edge SU->TargetSU would create a cycle + // then there is a path from TargetSU to SU. + int UpperBound, LowerBound; + LowerBound = Node2Index[TargetSU->NodeNum]; + UpperBound = Node2Index[SU->NodeNum]; + bool HasLoop = false; + // Is Ord(TargetSU) < Ord(SU) ? + if (LowerBound < UpperBound) { + Visited.reset(); + // There may be a path from TargetSU to SU. Check for it. + DFS(TargetSU, UpperBound, HasLoop); + } + return HasLoop; +} + +/// Allocate - assign the topological index to the node n. +inline void ScheduleDAGRRList::Allocate(int n, int index) { + Node2Index[n] = index; + Index2Node[index] = n; +} + +/// InitDAGTopologicalSorting - create the initial topological +/// ordering from the DAG to be scheduled. +void ScheduleDAGRRList::InitDAGTopologicalSorting() { + unsigned DAGSize = SUnits.size(); + std::vector InDegree(DAGSize); + std::vector WorkList; + WorkList.reserve(DAGSize); + std::vector TopOrder; + TopOrder.reserve(DAGSize); + + // Initialize the data structures. + for (unsigned i = 0, e = DAGSize; i != e; ++i) { + SUnit *SU = &SUnits[i]; + int NodeNum = SU->NodeNum; + unsigned Degree = SU->Succs.size(); + InDegree[NodeNum] = Degree; + + // Is it a node without dependencies? + if (Degree == 0) { + assert(SU->Succs.empty() && "SUnit should have no successors"); + // Collect leaf nodes. + WorkList.push_back(SU); + } + } + + while (!WorkList.empty()) { + SUnit *SU = WorkList.back(); + WorkList.pop_back(); + TopOrder.push_back(SU); + for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); + I != E; ++I) { + SUnit *SU = I->Dep; + if (!--InDegree[SU->NodeNum]) + // If all dependencies of the node are processed already, + // then the node can be computed now. + WorkList.push_back(SU); + } + } + + // Second pass, assign the actual topological order as node ids. + int Id = 0; + + Index2Node.clear(); + Node2Index.clear(); + Index2Node.resize(DAGSize); + Node2Index.resize(DAGSize); + Visited.resize(DAGSize); + + for (std::vector::reverse_iterator TI = TopOrder.rbegin(), + TE = TopOrder.rend();TI != TE; ++TI) { + Allocate((*TI)->NodeNum, Id); + Id++; + } + +#ifndef NDEBUG + // Check correctness of the ordering + for (unsigned i = 0, e = DAGSize; i != e; ++i) { + SUnit *SU = &SUnits[i]; + for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); + I != E; ++I) { + assert(Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && + "Wrong topological sorting"); + } + } +#endif +} + +/// AddPred - adds an edge from SUnit X to SUnit Y. +/// Updates the topological ordering if required. +bool ScheduleDAGRRList::AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial, + unsigned PhyReg, int Cost) { + int UpperBound, LowerBound; + LowerBound = Node2Index[Y->NodeNum]; + UpperBound = Node2Index[X->NodeNum]; + bool HasLoop = false; + // Is Ord(X) < Ord(Y) ? + if (LowerBound < UpperBound) { + // Update the topological order. + Visited.reset(); + DFS(Y, UpperBound, HasLoop); + assert(!HasLoop && "Inserted edge creates a loop!"); + // Recompute topological indexes. + Shift(Visited, LowerBound, UpperBound); } - if (!Visited.insert(SU)) return; + // Now really insert the edge. + return Y->addPred(X, isCtrl, isSpecial, PhyReg, Cost); +} - for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; - ++I) - isReachable(I->Dep, TargetSU, Visited, Reached); +/// RemovePred - This removes the specified node N from the predecessors of +/// the current node M. Updates the topological ordering if required. +bool ScheduleDAGRRList::RemovePred(SUnit *M, SUnit *N, + bool isCtrl, bool isSpecial) { + // InitDAGTopologicalSorting(); + return M->removePred(N, isCtrl, isSpecial); } -static bool isReachable(SUnit *SU, SUnit *TargetSU) { - SmallPtrSet Visited; - bool Reached = false; - isReachable(SU, TargetSU, Visited, Reached); - return Reached; +/// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark +/// all nodes affected by the edge insertion. These nodes will later get new +/// topological indexes by means of the Shift method. +void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) { + std::vector WorkList; + WorkList.reserve(SUnits.size()); + + WorkList.push_back(SU); + while (!WorkList.empty()) { + SU = WorkList.back(); + WorkList.pop_back(); + Visited.set(SU->NodeNum); + for (int I = SU->Succs.size()-1; I >= 0; --I) { + int s = SU->Succs[I].Dep->NodeNum; + if (Node2Index[s] == UpperBound) { + HasLoop = true; + return; + } + // Visit successors if not already and in affected region. + if (!Visited.test(s) && Node2Index[s] < UpperBound) { + WorkList.push_back(SU->Succs[I].Dep); + } + } + } } -/// willCreateCycle - Returns true if adding an edge from SU to TargetSU will +/// Shift - Renumber the nodes so that the topological ordering is +/// preserved. +void ScheduleDAGRRList::Shift(BitVector& Visited, int LowerBound, + int UpperBound) { + std::vector L; + int shift = 0; + int i; + + for (i = LowerBound; i <= UpperBound; ++i) { + // w is node at topological index i. + int w = Index2Node[i]; + if (Visited.test(w)) { + // Unmark. + Visited.reset(w); + L.push_back(w); + shift = shift + 1; + } else { + Allocate(w, i - shift); + } + } + + for (unsigned j = 0; j < L.size(); ++j) { + Allocate(L[j], i - shift); + i = i + 1; + } +} + + +/// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will /// create a cycle. -static bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { - if (isReachable(TargetSU, SU)) +bool ScheduleDAGRRList::WillCreateCycle(SUnit *SU, SUnit *TargetSU) { + if (IsReachable(TargetSU, SU)) return true; for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) - if (I->Cost < 0 && isReachable(TargetSU, I->Dep)) + if (I->Cost < 0 && IsReachable(TargetSU, I->Dep)) return true; return false; } @@ -397,22 +645,24 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { return NULL; SUnit *NewSU; - for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) - if (N->getValueType(i) == MVT::Flag) - return NULL; bool TryUnfold = false; - for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { - const SDOperand &Op = N->getOperand(i); - MVT::ValueType VT = Op.Val->getValueType(Op.ResNo); + for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { + MVT VT = N->getValueType(i); if (VT == MVT::Flag) return NULL; else if (VT == MVT::Other) TryUnfold = true; } + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { + const SDOperand &Op = N->getOperand(i); + MVT VT = Op.Val->getValueType(Op.ResNo); + if (VT == MVT::Flag) + return NULL; + } if (TryUnfold) { - SmallVector NewNodes; - if (!MRI->unfoldMemoryOperand(DAG, N, NewNodes)) + SmallVector NewNodes; + if (!TII->unfoldMemoryOperand(DAG, N, NewNodes)) return NULL; DOUT << "Unfolding SU # " << SU->NodeNum << "\n"; @@ -420,45 +670,48 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { N = NewNodes[1]; SDNode *LoadNode = NewNodes[0]; - std::vector Deleted; unsigned NumVals = N->getNumValues(); unsigned OldNumVals = SU->Node->getNumValues(); for (unsigned i = 0; i != NumVals; ++i) - DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), - SDOperand(N, i), Deleted); + DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i)); DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1), - SDOperand(LoadNode, 1), Deleted); - - SUnit *LoadSU = NewSUnit(LoadNode); - SUnit *NewSU = NewSUnit(N); - SUnitMap[LoadNode].push_back(LoadSU); - SUnitMap[N].push_back(NewSU); - const TargetInstrDescriptor *TID = &TII->get(LoadNode->getTargetOpcode()); - for (unsigned i = 0; i != TID->numOperands; ++i) { - if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) { - LoadSU->isTwoAddress = true; - break; - } - } - if (TID->Flags & M_COMMUTABLE) - LoadSU->isCommutable = true; + SDOperand(LoadNode, 1)); - TID = &TII->get(N->getTargetOpcode()); - for (unsigned i = 0; i != TID->numOperands; ++i) { - if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) { + SUnit *NewSU = CreateNewSUnit(N); + assert(N->getNodeId() == -1 && "Node already inserted!"); + N->setNodeId(NewSU->NodeNum); + + const TargetInstrDesc &TID = TII->get(N->getTargetOpcode()); + for (unsigned i = 0; i != TID.getNumOperands(); ++i) { + if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { NewSU->isTwoAddress = true; break; } } - if (TID->Flags & M_COMMUTABLE) + if (TID.isCommutable()) NewSU->isCommutable = true; - // FIXME: Calculate height / depth and propagate the changes? - LoadSU->Depth = NewSU->Depth = SU->Depth; - LoadSU->Height = NewSU->Height = SU->Height; - ComputeLatency(LoadSU); + NewSU->Depth = SU->Depth; + NewSU->Height = SU->Height; ComputeLatency(NewSU); + // LoadNode may already exist. This can happen when there is another + // load from the same location and producing the same type of value + // but it has different alignment or volatileness. + bool isNewLoad = true; + SUnit *LoadSU; + if (LoadNode->getNodeId() != -1) { + LoadSU = &SUnits[LoadNode->getNodeId()]; + isNewLoad = false; + } else { + LoadSU = CreateNewSUnit(LoadNode); + LoadNode->setNodeId(LoadSU->NodeNum); + + LoadSU->Depth = SU->Depth; + LoadSU->Height = SU->Height; + ComputeLatency(LoadSU); + } + SUnit *ChainPred = NULL; SmallVector ChainSuccs; SmallVector LoadPreds; @@ -468,7 +721,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { I != E; ++I) { if (I->isCtrl) ChainPred = I->Dep; - else if (I->Dep->Node && I->Dep->Node->isOperand(LoadNode)) + else if (I->Dep->Node && I->Dep->Node->isOperandOf(LoadNode)) LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); else NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); @@ -483,35 +736,45 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { I->isCtrl, I->isSpecial)); } - SU->removePred(ChainPred, true, false); - LoadSU->addPred(ChainPred, true, false); + if (ChainPred) { + RemovePred(SU, ChainPred, true, false); + if (isNewLoad) + AddPred(LoadSU, ChainPred, true, false); + } for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) { SDep *Pred = &LoadPreds[i]; - SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial); - LoadSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial, - Pred->Reg, Pred->Cost); + RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial); + if (isNewLoad) { + AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial, + Pred->Reg, Pred->Cost); + } } for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) { SDep *Pred = &NodePreds[i]; - SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial); - NewSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial, - Pred->Reg, Pred->Cost); + RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial); + AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial, + Pred->Reg, Pred->Cost); } for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) { SDep *Succ = &NodeSuccs[i]; - Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial); - Succ->Dep->addPred(NewSU, Succ->isCtrl, Succ->isSpecial, - Succ->Reg, Succ->Cost); + RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial); + AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isSpecial, + Succ->Reg, Succ->Cost); } for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) { SDep *Succ = &ChainSuccs[i]; - Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial); - Succ->Dep->addPred(LoadSU, Succ->isCtrl, Succ->isSpecial, - Succ->Reg, Succ->Cost); + RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial); + if (isNewLoad) { + AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isSpecial, + Succ->Reg, Succ->Cost); + } } - NewSU->addPred(LoadSU, false, false); + if (isNewLoad) { + AddPred(NewSU, LoadSU, false, false); + } - AvailableQueue->addNode(LoadSU); + if (isNewLoad) + AvailableQueue->addNode(LoadSU); AvailableQueue->addNode(NewSU); ++NumUnfolds; @@ -519,18 +782,18 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { if (NewSU->NumSuccsLeft == 0) { NewSU->isAvailable = true; return NewSU; - } else - SU = NewSU; + } + SU = NewSU; } DOUT << "Duplicating SU # " << SU->NodeNum << "\n"; - NewSU = Clone(SU); + NewSU = CreateClone(SU); // New SUnit has the exact same predecessors. for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) if (!I->isSpecial) { - NewSU->addPred(I->Dep, I->isCtrl, false, I->Reg, I->Cost); + AddPred(NewSU, I->Dep, I->isCtrl, false, I->Reg, I->Cost); NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1); } @@ -543,14 +806,14 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { continue; if (I->Dep->isScheduled) { NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1); - I->Dep->addPred(NewSU, I->isCtrl, false, I->Reg, I->Cost); + AddPred(I->Dep, NewSU, I->isCtrl, false, I->Reg, I->Cost); DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl)); } } for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) { SUnit *Succ = DelDeps[i].first; bool isCtrl = DelDeps[i].second; - Succ->removePred(SU, isCtrl, false); + RemovePred(Succ, SU, isCtrl, false); } AvailableQueue->updateNode(SU); @@ -566,14 +829,13 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVector &Copies) { - abort(); - SUnit *CopyFromSU = NewSUnit(NULL); + SUnit *CopyFromSU = CreateNewSUnit(NULL); CopyFromSU->CopySrcRC = SrcRC; CopyFromSU->CopyDstRC = DestRC; CopyFromSU->Depth = SU->Depth; CopyFromSU->Height = SU->Height; - SUnit *CopyToSU = NewSUnit(NULL); + SUnit *CopyToSU = CreateNewSUnit(NULL); CopyToSU->CopySrcRC = DestRC; CopyToSU->CopyDstRC = SrcRC; @@ -586,18 +848,18 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, continue; if (I->Dep->isScheduled) { CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1); - I->Dep->addPred(CopyToSU, I->isCtrl, false, I->Reg, I->Cost); + AddPred(I->Dep, CopyToSU, I->isCtrl, false, I->Reg, I->Cost); DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl)); } } for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) { SUnit *Succ = DelDeps[i].first; bool isCtrl = DelDeps[i].second; - Succ->removePred(SU, isCtrl, false); + RemovePred(Succ, SU, isCtrl, false); } - CopyFromSU->addPred(SU, false, false, Reg, -1); - CopyToSU->addPred(CopyFromSU, false, false, Reg, 1); + AddPred(CopyFromSU, SU, false, false, Reg, -1); + AddPred(CopyToSU, CopyFromSU, false, false, Reg, 1); AvailableQueue->updateNode(SU); AvailableQueue->addNode(CopyFromSU); @@ -611,12 +873,12 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, /// getPhysicalRegisterVT - Returns the ValueType of the physical register /// definition of the specified node. /// FIXME: Move to SelectionDAG? -static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg, - const TargetInstrInfo *TII) { - const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode()); +static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, + const TargetInstrInfo *TII) { + const TargetInstrDesc &TID = TII->get(N->getTargetOpcode()); assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); - unsigned NumRes = TID.numDefs; - for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) { + unsigned NumRes = TID.getNumDefs(); + for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) { if (Reg == *ImpDef) break; ++NumRes; @@ -643,7 +905,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (RegAdded.insert(Reg)) LRegs.push_back(Reg); } - for (const unsigned *Alias = MRI->getAliasSet(Reg); + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { if (RegAdded.insert(*Alias)) @@ -656,7 +918,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1]; if (!Node || !Node->isTargetOpcode()) continue; - const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode()); + const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode()); if (!TID.ImplicitDefs) continue; for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) { @@ -664,7 +926,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (RegAdded.insert(*Reg)) LRegs.push_back(*Reg); } - for (const unsigned *Alias = MRI->getAliasSet(*Reg); + for (const unsigned *Alias = TRI->getAliasSet(*Reg); *Alias; ++Alias) if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { if (RegAdded.insert(*Alias)) @@ -681,13 +943,17 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, void ScheduleDAGRRList::ListScheduleBottomUp() { unsigned CurCycle = 0; // Add root to Available queue. - SUnit *RootSU = SUnitMap[DAG.getRoot().Val].front(); - RootSU->isAvailable = true; - AvailableQueue->push(RootSU); + if (!SUnits.empty()) { + SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()]; + assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); + RootSU->isAvailable = true; + AvailableQueue->push(RootSU); + } // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. SmallVector NotReady; + Sequence.reserve(SUnits.size()); while (!AvailableQueue->empty()) { bool Delayed = false; DenseMap > LRegsMap; @@ -731,7 +997,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { OldSU->isAvailable = false; AvailableQueue->remove(OldSU); } - TrySU->addPred(OldSU, true, true); + AddPred(TrySU, OldSU, true, true); // If one or more successors has been unscheduled, then the current // node is no longer avaialable. Schedule a successor that's now // available instead. @@ -747,7 +1013,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { } if (!CurSU) { - // Can't backtrace. Try duplicating the nodes that produces these + // Can't backtrack. Try duplicating the nodes that produces these // "expensive to copy" values to break the dependency. In case even // that doesn't work, insert cross class copies. SUnit *TrySU = NotReady[0]; @@ -758,10 +1024,10 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { SUnit *NewDef = CopyAndMoveSuccessors(LRDef); if (!NewDef) { // Issue expensive cross register class copies. - MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); + MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); const TargetRegisterClass *RC = - MRI->getPhysicalRegisterRegClass(VT, Reg); - const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC); + TRI->getPhysicalRegisterRegClass(Reg, VT); + const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); if (!DestRC) { assert(false && "Don't know how to copy this physical register!"); abort(); @@ -770,14 +1036,14 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); DOUT << "Adding an edge from SU # " << TrySU->NodeNum << " to SU #" << Copies.front()->NodeNum << "\n"; - TrySU->addPred(Copies.front(), true, true); + AddPred(TrySU, Copies.front(), true, true); NewDef = Copies.back(); } DOUT << "Adding an edge from SU # " << NewDef->NodeNum << " to SU #" << TrySU->NodeNum << "\n"; LiveRegDefs[Reg] = NewDef; - NewDef->addPred(TrySU, true, true); + AddPred(NewDef, TrySU, true, true); TrySU->isAvailable = false; CurSU = NewDef; } @@ -806,12 +1072,6 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { ++CurCycle; } - // Add entry node last - if (DAG.getEntryNode().Val != DAG.getRoot().Val) { - SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front(); - Sequence.push_back(Entry); - } - // Reverse the order if it is bottom up. std::reverse(Sequence.begin(), Sequence.end()); @@ -819,16 +1079,34 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { #ifndef NDEBUG // Verify that all SUnits were scheduled. bool AnyNotSched = false; + unsigned DeadNodes = 0; + unsigned Noops = 0; for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { - if (SUnits[i].NumSuccsLeft != 0) { + if (!SUnits[i].isScheduled) { + if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { + ++DeadNodes; + continue; + } if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; SUnits[i].dump(&DAG); cerr << "has not been scheduled!\n"; AnyNotSched = true; } + if (SUnits[i].NumSuccsLeft != 0) { + if (!AnyNotSched) + cerr << "*** List scheduling failed! ***\n"; + SUnits[i].dump(&DAG); + cerr << "has successors left!\n"; + AnyNotSched = true; + } } + for (unsigned i = 0, e = Sequence.size(); i != e; ++i) + if (!Sequence[i]) + ++Noops; assert(!AnyNotSched); + assert(Sequence.size() + DeadNodes - Noops == SUnits.size() && + "The number of nodes scheduled doesn't match the expected number!"); #endif } @@ -885,25 +1163,20 @@ void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { /// schedulers. void ScheduleDAGRRList::ListScheduleTopDown() { unsigned CurCycle = 0; - SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front(); // All leaves to Available queue. for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { // It is available if it has no predecessors. - if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) { + if (SUnits[i].Preds.empty()) { AvailableQueue->push(&SUnits[i]); SUnits[i].isAvailable = true; } } - // Emit the entry node first. - ScheduleNodeTopDown(Entry, CurCycle); - Sequence.push_back(Entry); - ++CurCycle; - // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. std::vector NotReady; + Sequence.reserve(SUnits.size()); while (!AvailableQueue->empty()) { SUnit *CurSU = AvailableQueue->pop(); while (CurSU && CurSU->CycleBound > CurCycle) { @@ -921,23 +1194,41 @@ void ScheduleDAGRRList::ListScheduleTopDown() { ScheduleNodeTopDown(CurSU, CurCycle); Sequence.push_back(CurSU); } - CurCycle++; + ++CurCycle; } #ifndef NDEBUG // Verify that all SUnits were scheduled. bool AnyNotSched = false; + unsigned DeadNodes = 0; + unsigned Noops = 0; for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { if (!SUnits[i].isScheduled) { + if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { + ++DeadNodes; + continue; + } if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; SUnits[i].dump(&DAG); cerr << "has not been scheduled!\n"; AnyNotSched = true; } + if (SUnits[i].NumPredsLeft != 0) { + if (!AnyNotSched) + cerr << "*** List scheduling failed! ***\n"; + SUnits[i].dump(&DAG); + cerr << "has predecessors left!\n"; + AnyNotSched = true; + } } + for (unsigned i = 0, e = Sequence.size(); i != e; ++i) + if (!Sequence[i]) + ++Noops; assert(!AnyNotSched); + assert(Sequence.size() + DeadNodes - Noops == SUnits.size() && + "The number of nodes scheduled doesn't match the expected number!"); #endif } @@ -982,14 +1273,14 @@ namespace { template class VISIBILITY_HIDDEN RegReductionPriorityQueue : public SchedulingPriorityQueue { - std::priority_queue, SF> Queue; + PriorityQueue, SF> Queue; + unsigned currentQueueId; public: RegReductionPriorityQueue() : - Queue(SF(this)) {} + Queue(SF(this)), currentQueueId(0) {} - virtual void initNodes(DenseMap > &sumap, - std::vector &sunits) {} + virtual void initNodes(std::vector &sunits) {} virtual void addNode(const SUnit *SU) {} @@ -1006,48 +1297,34 @@ namespace { bool empty() const { return Queue.empty(); } void push(SUnit *U) { + assert(!U->NodeQueueId && "Node in the queue already"); + U->NodeQueueId = ++currentQueueId; Queue.push(U); } + void push_all(const std::vector &Nodes) { for (unsigned i = 0, e = Nodes.size(); i != e; ++i) - Queue.push(Nodes[i]); + push(Nodes[i]); } SUnit *pop() { if (empty()) return NULL; SUnit *V = Queue.top(); Queue.pop(); + V->NodeQueueId = 0; return V; } - /// remove - This is a really inefficient way to remove a node from a - /// priority queue. We should roll our own heap to make this better or - /// something. void remove(SUnit *SU) { - std::vector Temp; - - assert(!Queue.empty() && "Not in queue!"); - while (Queue.top() != SU) { - Temp.push_back(Queue.top()); - Queue.pop(); - assert(!Queue.empty() && "Not in queue!"); - } - - // Remove the node from the PQ. - Queue.pop(); - - // Add all the other nodes back. - for (unsigned i = 0, e = Temp.size(); i != e; ++i) - Queue.push(Temp[i]); + assert(!Queue.empty() && "Queue is empty!"); + assert(SU->NodeQueueId != 0 && "Not in queue!"); + Queue.erase_one(SU); + SU->NodeQueueId = 0; } }; - template class VISIBILITY_HIDDEN BURegReductionPriorityQueue - : public RegReductionPriorityQueue { - // SUnitMap SDNode to SUnit mapping (n -> n). - DenseMap > *SUnitMap; - + : public RegReductionPriorityQueue { // SUnits - The SUnits for the current graph. const std::vector *SUnits; @@ -1055,13 +1332,14 @@ namespace { std::vector SethiUllmanNumbers; const TargetInstrInfo *TII; + const TargetRegisterInfo *TRI; + ScheduleDAGRRList *scheduleDAG; public: - explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii) - : TII(tii) {} + explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii, + const TargetRegisterInfo *tri) + : TII(tii), TRI(tri), scheduleDAG(NULL) {} - void initNodes(DenseMap > &sumap, - std::vector &sunits) { - SUnitMap = &sumap; + void initNodes(std::vector &sunits) { SUnits = &sunits; // Add pseudo dependency edges for two-address nodes. AddPseudoTwoAddrDeps(); @@ -1096,6 +1374,11 @@ namespace { // CopyToReg should be close to its uses to facilitate coalescing and // avoid spilling. return 0; + else if (Opc == TargetInstrInfo::EXTRACT_SUBREG || + Opc == TargetInstrInfo::INSERT_SUBREG) + // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to + // facilitate coalescing. + return 0; else if (SU->NumSuccs == 0) // If SU does not have a use, i.e. it doesn't produce a value that would // be consumed (e.g. store), then it terminates a chain of computation. @@ -1110,20 +1393,20 @@ namespace { return SethiUllmanNumbers[SU->NodeNum]; } + void setScheduleDAG(ScheduleDAGRRList *scheduleDag) { + scheduleDAG = scheduleDag; + } + private: - bool canClobber(SUnit *SU, SUnit *Op); + bool canClobber(const SUnit *SU, const SUnit *Op); void AddPseudoTwoAddrDeps(); void CalculateSethiUllmanNumbers(); unsigned CalcNodeSethiUllmanNumber(const SUnit *SU); }; - template class VISIBILITY_HIDDEN TDRegReductionPriorityQueue - : public RegReductionPriorityQueue { - // SUnitMap SDNode to SUnit mapping (n -> n). - DenseMap > *SUnitMap; - + : public RegReductionPriorityQueue { // SUnits - The SUnits for the current graph. const std::vector *SUnits; @@ -1133,9 +1416,7 @@ namespace { public: TDRegReductionPriorityQueue() {} - void initNodes(DenseMap > &sumap, - std::vector &sunits) { - SUnitMap = &sumap; + void initNodes(std::vector &sunits) { SUnits = &sunits; // Calculate node priorities. CalculateSethiUllmanNumbers(); @@ -1184,71 +1465,91 @@ static unsigned closestSucc(const SUnit *SU) { return MaxCycle; } +/// calcMaxScratches - Returns an cost estimate of the worse case requirement +/// for scratch registers. Live-in operands and live-out results don't count +/// since they are "fixed". +static unsigned calcMaxScratches(const SUnit *SU) { + unsigned Scratches = 0; + for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); + I != E; ++I) { + if (I->isCtrl) continue; // ignore chain preds + if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg) + Scratches++; + } + for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); + I != E; ++I) { + if (I->isCtrl) continue; // ignore chain succs + if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg) + Scratches += 10; + } + return Scratches; +} + // Bottom up bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { - // There used to be a special tie breaker here that looked for - // two-address instructions and preferred the instruction with a - // def&use operand. The special case triggered diagnostics when - // _GLIBCXX_DEBUG was enabled because it broke the strict weak - // ordering that priority_queue requires. It didn't help much anyway - // because AddPseudoTwoAddrDeps already covers many of the cases - // where it would have applied. In addition, it's counter-intuitive - // that a tie breaker would be the first thing attempted. There's a - // "real" tie breaker below that is the operation of last resort. - // The fact that the "special tie breaker" would trigger when there - // wasn't otherwise a tie is what broke the strict weak ordering - // constraint. unsigned LPriority = SPQ->getNodePriority(left); unsigned RPriority = SPQ->getNodePriority(right); - if (LPriority > RPriority) - return true; - else if (LPriority == RPriority) { - // Try schedule def + use closer when Sethi-Ullman numbers are the same. - // e.g. - // t1 = op t2, c1 - // t3 = op t4, c2 - // - // and the following instructions are both ready. - // t2 = op c3 - // t4 = op c4 - // - // Then schedule t2 = op first. - // i.e. - // t4 = op c4 - // t2 = op c3 - // t1 = op t2, c1 - // t3 = op t4, c2 - // - // This creates more short live intervals. - unsigned LDist = closestSucc(left); - unsigned RDist = closestSucc(right); - if (LDist < RDist) - return true; - else if (LDist == RDist) { - if (left->Height > right->Height) - return true; - else if (left->Height == right->Height) - if (left->Depth < right->Depth) - return true; - else if (left->Depth == right->Depth) - if (left->CycleBound > right->CycleBound) - return true; - } - } - return false; + if (LPriority != RPriority) + return LPriority > RPriority; + + // Try schedule def + use closer when Sethi-Ullman numbers are the same. + // e.g. + // t1 = op t2, c1 + // t3 = op t4, c2 + // + // and the following instructions are both ready. + // t2 = op c3 + // t4 = op c4 + // + // Then schedule t2 = op first. + // i.e. + // t4 = op c4 + // t2 = op c3 + // t1 = op t2, c1 + // t3 = op t4, c2 + // + // This creates more short live intervals. + unsigned LDist = closestSucc(left); + unsigned RDist = closestSucc(right); + if (LDist != RDist) + return LDist < RDist; + + // Intuitively, it's good to push down instructions whose results are + // liveout so their long live ranges won't conflict with other values + // which are needed inside the BB. Further prioritize liveout instructions + // by the number of operands which are calculated within the BB. + unsigned LScratch = calcMaxScratches(left); + unsigned RScratch = calcMaxScratches(right); + if (LScratch != RScratch) + return LScratch > RScratch; + + if (left->Height != right->Height) + return left->Height > right->Height; + + if (left->Depth != right->Depth) + return left->Depth < right->Depth; + + if (left->CycleBound != right->CycleBound) + return left->CycleBound > right->CycleBound; + + assert(left->NodeQueueId && right->NodeQueueId && + "NodeQueueId cannot be zero"); + return (left->NodeQueueId > right->NodeQueueId); } -template -bool BURegReductionPriorityQueue::canClobber(SUnit *SU, SUnit *Op) { +bool +BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) { if (SU->isTwoAddress) { unsigned Opc = SU->Node->getTargetOpcode(); - unsigned NumRes = TII->getNumDefs(Opc); - unsigned NumOps = ScheduleDAG::CountOperands(SU->Node); + const TargetInstrDesc &TID = TII->get(Opc); + unsigned NumRes = TID.getNumDefs(); + unsigned NumOps = TID.getNumOperands() - NumRes; for (unsigned i = 0; i != NumOps; ++i) { - if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) { + if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) { SDNode *DU = SU->Node->getOperand(i).Val; - if (Op == (*SUnitMap)[DU][SU->InstanceNo]) + if (DU->getNodeId() != -1 && + Op->OrigNode == &(*SUnits)[DU->getNodeId()]) return true; } } @@ -1270,6 +1571,33 @@ static bool hasCopyToRegUse(SUnit *SU) { return false; } +/// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's +/// physical register defs. +static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, + const TargetInstrInfo *TII, + const TargetRegisterInfo *TRI) { + SDNode *N = SuccSU->Node; + unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs(); + const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs(); + assert(ImpDefs && "Caller should check hasPhysRegDefs"); + const unsigned *SUImpDefs = + TII->get(SU->Node->getTargetOpcode()).getImplicitDefs(); + if (!SUImpDefs) + return false; + for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { + MVT VT = N->getValueType(i); + if (VT == MVT::Flag || VT == MVT::Other) + continue; + unsigned Reg = ImpDefs[i - NumDefs]; + for (;*SUImpDefs; ++SUImpDefs) { + unsigned SUReg = *SUImpDefs; + if (TRI->regsOverlap(Reg, SUReg)) + return true; + } + } + return false; +} + /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses /// it as a def&use operand. Add a pseudo control edge from it to the other /// node (if it won't create a cycle) so the two-address one will be scheduled @@ -1277,8 +1605,7 @@ static bool hasCopyToRegUse(SUnit *SU) { /// one that has a CopyToReg use (more likely to be a loop induction update). /// If both are two-address, but one is commutable while the other is not /// commutable, favor the one that's not commutable. -template -void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { +void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { SUnit *SU = (SUnit *)&((*SUnits)[i]); if (!SU->isTwoAddress) @@ -1289,31 +1616,47 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { continue; unsigned Opc = Node->getTargetOpcode(); - unsigned NumRes = TII->getNumDefs(Opc); - unsigned NumOps = ScheduleDAG::CountOperands(Node); + const TargetInstrDesc &TID = TII->get(Opc); + unsigned NumRes = TID.getNumDefs(); + unsigned NumOps = TID.getNumOperands() - NumRes; for (unsigned j = 0; j != NumOps; ++j) { - if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) { + if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) { SDNode *DU = SU->Node->getOperand(j).Val; - SUnit *DUSU = (*SUnitMap)[DU][SU->InstanceNo]; + if (DU->getNodeId() == -1) + continue; + const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; if (!DUSU) continue; - for (SUnit::succ_iterator I = DUSU->Succs.begin(),E = DUSU->Succs.end(); - I != E; ++I) { + for (SUnit::const_succ_iterator I = DUSU->Succs.begin(), + E = DUSU->Succs.end(); I != E; ++I) { if (I->isCtrl) continue; SUnit *SuccSU = I->Dep; - // Don't constraint nodes with implicit defs. It can create cycles - // plus it may increase register pressures. - if (SuccSU == SU || SuccSU->hasPhysRegDefs) + if (SuccSU == SU) + continue; + // Be conservative. Ignore if nodes aren't at roughly the same + // depth and height. + if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1) continue; - // Be conservative. Ignore if nodes aren't at the same depth. - if (SuccSU->Depth != SU->Depth) + if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode()) + continue; + // Don't constrain nodes with physical register defs if the + // predecessor can clobber them. + if (SuccSU->hasPhysRegDefs) { + if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) + continue; + } + // Don't constraint extract_subreg / insert_subreg these may be + // coalesced away. We don't them close to their uses. + unsigned SuccOpc = SuccSU->Node->getTargetOpcode(); + if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || + SuccOpc == TargetInstrInfo::INSERT_SUBREG) continue; if ((!canClobber(SuccSU, DUSU) || (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) || (!SU->isCommutable && SuccSU->isCommutable)) && - !isReachable(SuccSU, SU)) { + !scheduleDAG->IsReachable(SuccSU, SU)) { DOUT << "Adding an edge from SU # " << SU->NodeNum << " to SU #" << SuccSU->NodeNum << "\n"; - SU->addPred(SuccSU, true, true); + scheduleDAG->AddPred(SU, SuccSU, true, true); } } } @@ -1323,8 +1666,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number. /// Smaller number is the higher priority. -template -unsigned BURegReductionPriorityQueue:: +unsigned BURegReductionPriorityQueue:: CalcNodeSethiUllmanNumber(const SUnit *SU) { unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; if (SethiUllmanNumber != 0) @@ -1353,15 +1695,18 @@ CalcNodeSethiUllmanNumber(const SUnit *SU) { /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all /// scheduling units. -template -void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() { +void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() { SethiUllmanNumbers.assign(SUnits->size(), 0); for (unsigned i = 0, e = SUnits->size(); i != e; ++i) CalcNodeSethiUllmanNumber(&(*SUnits)[i]); } -static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) { +/// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled +/// predecessors of the successors of the SUnit SU. Stop when the provided +/// limit is exceeded. +static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU, + unsigned Limit) { unsigned Sum = 0; for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { @@ -1370,10 +1715,10 @@ static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) { EE = SuccSU->Preds.end(); II != EE; ++II) { SUnit *PredSU = II->Dep; if (!PredSU->isScheduled) - ++Sum; + if (++Sum > Limit) + return Sum; } } - return Sum; } @@ -1386,28 +1731,14 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { bool RIsTarget = right->Node && right->Node->isTargetOpcode(); bool LIsFloater = LIsTarget && left->NumPreds == 0; bool RIsFloater = RIsTarget && right->NumPreds == 0; - unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0; - unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0; + unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0; + unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0; if (left->NumSuccs == 0 && right->NumSuccs != 0) return false; else if (left->NumSuccs != 0 && right->NumSuccs == 0) return true; - // Special tie breaker: if two nodes share a operand, the one that use it - // as a def&use operand is preferred. - if (LIsTarget && RIsTarget) { - if (left->isTwoAddress && !right->isTwoAddress) { - SDNode *DUNode = left->Node->getOperand(0).Val; - if (DUNode->isOperand(right->Node)) - RBonus += 2; - } - if (!left->isTwoAddress && right->isTwoAddress) { - SDNode *DUNode = right->Node->getOperand(0).Val; - if (DUNode->isOperand(left->Node)) - LBonus += 2; - } - } if (LIsFloater) LBonus -= 2; if (RIsFloater) @@ -1417,24 +1748,26 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { if (right->NumSuccs == 1) RBonus += 2; - if (LPriority+LBonus < RPriority+RBonus) - return true; - else if (LPriority == RPriority) - if (left->Depth < right->Depth) - return true; - else if (left->Depth == right->Depth) - if (left->NumSuccsLeft > right->NumSuccsLeft) - return true; - else if (left->NumSuccsLeft == right->NumSuccsLeft) - if (left->CycleBound > right->CycleBound) - return true; - return false; + if (LPriority+LBonus != RPriority+RBonus) + return LPriority+LBonus < RPriority+RBonus; + + if (left->Depth != right->Depth) + return left->Depth < right->Depth; + + if (left->NumSuccsLeft != right->NumSuccsLeft) + return left->NumSuccsLeft > right->NumSuccsLeft; + + if (left->CycleBound != right->CycleBound) + return left->CycleBound > right->CycleBound; + + assert(left->NodeQueueId && right->NodeQueueId && + "NodeQueueId cannot be zero"); + return (left->NodeQueueId > right->NodeQueueId); } /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number. /// Smaller number is the higher priority. -template -unsigned TDRegReductionPriorityQueue:: +unsigned TDRegReductionPriorityQueue:: CalcNodeSethiUllmanNumber(const SUnit *SU) { unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; if (SethiUllmanNumber != 0) @@ -1474,8 +1807,7 @@ CalcNodeSethiUllmanNumber(const SUnit *SU) { /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all /// scheduling units. -template -void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() { +void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() { SethiUllmanNumbers.assign(SUnits->size(), 0); for (unsigned i = 0, e = SUnits->size(); i != e; ++i) @@ -1490,14 +1822,21 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, MachineBasicBlock *BB) { const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo(); - return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, - new BURegReductionPriorityQueue(TII)); + const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo(); + + BURegReductionPriorityQueue *priorityQueue = + new BURegReductionPriorityQueue(TII, TRI); + + ScheduleDAGRRList * scheduleDAG = + new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, priorityQueue); + priorityQueue->setScheduleDAG(scheduleDAG); + return scheduleDAG; } llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, MachineBasicBlock *BB) { return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, - new TDRegReductionPriorityQueue()); + new TDRegReductionPriorityQueue()); }