X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FScheduleDAGRRList.cpp;h=c605292695bc911220dc55e2a70b084ba7415dbc;hb=b3bc6352defdf1a5c6b1b0770d0c4d603f6524a8;hp=098b7996d4c8003be75d10fb2fc794f3f75f0801;hpb=0f4012f4759a6c6ca28f11ed1eb98feb8ab1481b;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 098b7996d4c..c605292695b 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1,4 +1,4 @@ -//===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===// +//===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===// // // The LLVM Compiler Infrastructure // @@ -41,11 +41,11 @@ STATISTIC(NumCCCopies, "Number of cross class copies"); static RegisterScheduler burrListDAGScheduler("list-burr", - " Bottom-up register reduction list scheduling", + "Bottom-up register reduction list scheduling", createBURRListDAGScheduler); static RegisterScheduler tdrListrDAGScheduler("list-tdrr", - " Top-down register reduction list scheduling", + "Top-down register reduction list scheduling", createTDRRListDAGScheduler); namespace { @@ -66,10 +66,10 @@ private: /// AvailableQueue - The priority queue to use for the available SUnits. SchedulingPriorityQueue *AvailableQueue; - /// LiveRegs / LiveRegDefs - A set of physical registers and their definition + /// LiveRegDefs - A set of physical registers and their definition /// that are "live". These nodes must be scheduled before any other nodes that /// modifies the registers can be scheduled. - SmallSet LiveRegs; + unsigned NumLiveRegs; std::vector LiveRegDefs; std::vector LiveRegCycles; @@ -88,7 +88,7 @@ public: void Schedule(); /// IsReachable - Checks if SU is reachable from TargetSU. - bool IsReachable(SUnit *SU, SUnit *TargetSU); + bool IsReachable(const SUnit *SU, const SUnit *TargetSU); /// willCreateCycle - Returns true if adding an edge from SU to TargetSU will /// create a cycle. @@ -155,7 +155,7 @@ private: /// DFS - make a DFS traversal and mark all nodes affected by the /// edge insertion. These nodes will later get new topological indexes /// by means of the Shift method. - void DFS(SUnit *SU, int UpperBound, bool& HasLoop); + void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); /// Shift - reassign topological indexes for the nodes in the DAG /// to preserve the topological ordering. @@ -178,6 +178,7 @@ private: void ScheduleDAGRRList::Schedule() { DOUT << "********** List Scheduling **********\n"; + NumLiveRegs = 0; LiveRegDefs.resize(TRI->getNumRegs(), NULL); LiveRegCycles.resize(TRI->getNumRegs(), 0); @@ -216,7 +217,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { SUnit *SU = Sequence[i]; if (!SU || !SU->Node) continue; if (SU->isCommutable) { - unsigned Opc = SU->Node->getTargetOpcode(); + unsigned Opc = SU->Node->getMachineOpcode(); const TargetInstrDesc &TID = TII->get(Opc); unsigned NumRes = TID.getNumDefs(); unsigned NumOps = TID.getNumOperands() - NumRes; @@ -224,7 +225,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1) continue; - SDNode *OpN = SU->Node->getOperand(j).Val; + SDNode *OpN = SU->Node->getOperand(j).getNode(); SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()]; if (OpSU && OperandSeen.count(OpSU) == 1) { // Ok, so SU is not the last use of OpSU, but SU is two-address so @@ -233,7 +234,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { bool DoCommute = true; for (unsigned k = 0; k < NumOps; ++k) { if (k != j) { - OpN = SU->Node->getOperand(k).Val; + OpN = SU->Node->getOperand(k).getNode(); OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()]; if (OpSU && OperandSeen.count(OpSU) == 1) { DoCommute = false; @@ -308,7 +309,8 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { // expensive to copy the register. Make sure nothing that can // clobber the register is scheduled between the predecessor and // this node. - if (LiveRegs.insert(I->Reg)) { + if (!LiveRegDefs[I->Reg]) { + ++NumLiveRegs; LiveRegDefs[I->Reg] = I->Dep; LiveRegCycles[I->Reg] = CurCycle; } @@ -320,9 +322,10 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { I != E; ++I) { if (I->Cost < 0) { if (LiveRegCycles[I->Reg] == I->Dep->Cycle) { - LiveRegs.erase(I->Reg); + assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!"); assert(LiveRegDefs[I->Reg] == SU && "Physical register dependency violated?"); + --NumLiveRegs; LiveRegDefs[I->Reg] = NULL; LiveRegCycles[I->Reg] = 0; } @@ -367,9 +370,10 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { I != E; ++I) { CapturePred(I->Dep, SU, I->isCtrl); if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) { - LiveRegs.erase(I->Reg); + assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!"); assert(LiveRegDefs[I->Reg] == I->Dep && "Physical register dependency violated?"); + --NumLiveRegs; LiveRegDefs[I->Reg] = NULL; LiveRegCycles[I->Reg] = 0; } @@ -378,10 +382,9 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { if (I->Cost < 0) { - if (LiveRegs.insert(I->Reg)) { - assert(!LiveRegDefs[I->Reg] && - "Physical register dependency violated?"); + if (!LiveRegDefs[I->Reg]) { LiveRegDefs[I->Reg] = SU; + ++NumLiveRegs; } if (I->Dep->Cycle < LiveRegCycles[I->Reg]) LiveRegCycles[I->Reg] = I->Dep->Cycle; @@ -395,7 +398,7 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { } /// IsReachable - Checks if SU is reachable from TargetSU. -bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) { +bool ScheduleDAGRRList::IsReachable(const SUnit *SU, const SUnit *TargetSU) { // If insertion of the edge SU->TargetSU would create a cycle // then there is a path from TargetSU to SU. int UpperBound, LowerBound; @@ -448,18 +451,19 @@ inline void ScheduleDAGRRList::Allocate(int n, int index) { /// immediately after X in Index2Node. void ScheduleDAGRRList::InitDAGTopologicalSorting() { unsigned DAGSize = SUnits.size(); - std::vector InDegree(DAGSize); std::vector WorkList; WorkList.reserve(DAGSize); - std::vector TopOrder; - TopOrder.reserve(DAGSize); + + Index2Node.resize(DAGSize); + Node2Index.resize(DAGSize); // Initialize the data structures. for (unsigned i = 0, e = DAGSize; i != e; ++i) { SUnit *SU = &SUnits[i]; int NodeNum = SU->NodeNum; unsigned Degree = SU->Succs.size(); - InDegree[NodeNum] = Degree; + // Temporarily use the Node2Index array as scratch space for degree counts. + Node2Index[NodeNum] = Degree; // Is it a node without dependencies? if (Degree == 0) { @@ -469,35 +473,23 @@ void ScheduleDAGRRList::InitDAGTopologicalSorting() { } } + int Id = DAGSize; while (!WorkList.empty()) { SUnit *SU = WorkList.back(); WorkList.pop_back(); - TopOrder.push_back(SU); + Allocate(SU->NodeNum, --Id); for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { SUnit *SU = I->Dep; - if (!--InDegree[SU->NodeNum]) + if (!--Node2Index[SU->NodeNum]) // If all dependencies of the node are processed already, // then the node can be computed now. WorkList.push_back(SU); } } - // Second pass, assign the actual topological order as node ids. - int Id = 0; - - Index2Node.clear(); - Node2Index.clear(); - Index2Node.resize(DAGSize); - Node2Index.resize(DAGSize); Visited.resize(DAGSize); - for (std::vector::reverse_iterator TI = TopOrder.rbegin(), - TE = TopOrder.rend();TI != TE; ++TI) { - Allocate((*TI)->NodeNum, Id); - Id++; - } - #ifndef NDEBUG // Check correctness of the ordering for (unsigned i = 0, e = DAGSize; i != e; ++i) { @@ -543,8 +535,8 @@ bool ScheduleDAGRRList::RemovePred(SUnit *M, SUnit *N, /// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark /// all nodes affected by the edge insertion. These nodes will later get new /// topological indexes by means of the Shift method. -void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) { - std::vector WorkList; +void ScheduleDAGRRList::DFS(const SUnit *SU, int UpperBound, bool& HasLoop) { + std::vector WorkList; WorkList.reserve(SUnits.size()); WorkList.push_back(SU); @@ -651,8 +643,8 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { TryUnfold = true; } for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { - const SDOperand &Op = N->getOperand(i); - MVT VT = Op.Val->getValueType(Op.ResNo); + const SDValue &Op = N->getOperand(i); + MVT VT = Op.getNode()->getValueType(Op.getResNo()); if (VT == MVT::Flag) return NULL; } @@ -670,15 +662,15 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { unsigned NumVals = N->getNumValues(); unsigned OldNumVals = SU->Node->getNumValues(); for (unsigned i = 0; i != NumVals; ++i) - DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i)); - DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1), - SDOperand(LoadNode, 1)); + DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); + DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), + SDValue(LoadNode, 1)); SUnit *NewSU = CreateNewSUnit(N); assert(N->getNodeId() == -1 && "Node already inserted!"); N->setNodeId(NewSU->NodeNum); - const TargetInstrDesc &TID = TII->get(N->getTargetOpcode()); + const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); for (unsigned i = 0; i != TID.getNumOperands(); ++i) { if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { NewSU->isTwoAddress = true; @@ -872,7 +864,7 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, /// FIXME: Move to SelectionDAG? static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) { - const TargetInstrDesc &TID = TII->get(N->getTargetOpcode()); + const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); unsigned NumRes = TID.getNumDefs(); for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) { @@ -889,7 +881,7 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, /// whatever is necessary (i.e. backtracking or cloning) to make it possible. bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, SmallVector &LRegs){ - if (LiveRegs.empty()) + if (NumLiveRegs == 0) return false; SmallSet RegAdded; @@ -898,13 +890,13 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, I != E; ++I) { if (I->Cost < 0) { unsigned Reg = I->Reg; - if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) { + if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) { if (RegAdded.insert(Reg)) LRegs.push_back(Reg); } for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) - if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { + if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) { if (RegAdded.insert(*Alias)) LRegs.push_back(*Alias); } @@ -913,19 +905,19 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) { SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1]; - if (!Node || !Node->isTargetOpcode()) + if (!Node || !Node->isMachineOpcode()) continue; - const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode()); + const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode()); if (!TID.ImplicitDefs) continue; for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) { - if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) { + if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) { if (RegAdded.insert(*Reg)) LRegs.push_back(*Reg); } for (const unsigned *Alias = TRI->getAliasSet(*Reg); *Alias; ++Alias) - if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { + if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) { if (RegAdded.insert(*Alias)) LRegs.push_back(*Alias); } @@ -941,7 +933,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { unsigned CurCycle = 0; // Add root to Available queue. if (!SUnits.empty()) { - SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()]; + SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()]; assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); RootSU->isAvailable = true; AvailableQueue->push(RootSU); @@ -1403,7 +1395,7 @@ namespace { class VISIBILITY_HIDDEN BURegReductionPriorityQueue : public RegReductionPriorityQueue { // SUnits - The SUnits for the current graph. - const std::vector *SUnits; + std::vector *SUnits; // SethiUllmanNumbers - The SethiUllman number for each node. std::vector SethiUllmanNumbers; @@ -1673,13 +1665,13 @@ bu_ls_rr_fast_sort::operator()(const SUnit *left, const SUnit *right) const { bool BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) { if (SU->isTwoAddress) { - unsigned Opc = SU->Node->getTargetOpcode(); + unsigned Opc = SU->Node->getMachineOpcode(); const TargetInstrDesc &TID = TII->get(Opc); unsigned NumRes = TID.getNumDefs(); unsigned NumOps = TID.getNumOperands() - NumRes; for (unsigned i = 0; i != NumOps; ++i) { if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) { - SDNode *DU = SU->Node->getOperand(i).Val; + SDNode *DU = SU->Node->getOperand(i).getNode(); if (DU->getNodeId() != -1 && Op->OrigNode == &(*SUnits)[DU->getNodeId()]) return true; @@ -1692,11 +1684,11 @@ BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) { /// hasCopyToRegUse - Return true if SU has a value successor that is a /// CopyToReg node. -static bool hasCopyToRegUse(SUnit *SU) { +static bool hasCopyToRegUse(const SUnit *SU) { for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { if (I->isCtrl) continue; - SUnit *SuccSU = I->Dep; + const SUnit *SuccSU = I->Dep; if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg) return true; } @@ -1705,21 +1697,23 @@ static bool hasCopyToRegUse(SUnit *SU) { /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's /// physical register defs. -static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, +static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) { SDNode *N = SuccSU->Node; - unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs(); - const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs(); + unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); + const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); assert(ImpDefs && "Caller should check hasPhysRegDefs"); const unsigned *SUImpDefs = - TII->get(SU->Node->getTargetOpcode()).getImplicitDefs(); + TII->get(SU->Node->getMachineOpcode()).getImplicitDefs(); if (!SUImpDefs) return false; for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { MVT VT = N->getValueType(i); if (VT == MVT::Flag || VT == MVT::Other) continue; + if (!N->hasAnyUseOfValue(i)) + continue; unsigned Reg = ImpDefs[i - NumDefs]; for (;*SUImpDefs; ++SUImpDefs) { unsigned SUReg = *SUImpDefs; @@ -1739,21 +1733,21 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, /// commutable, favor the one that's not commutable. void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { - SUnit *SU = (SUnit *)&((*SUnits)[i]); + SUnit *SU = &(*SUnits)[i]; if (!SU->isTwoAddress) continue; SDNode *Node = SU->Node; - if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0) + if (!Node || !Node->isMachineOpcode() || SU->FlaggedNodes.size() > 0) continue; - unsigned Opc = Node->getTargetOpcode(); + unsigned Opc = Node->getMachineOpcode(); const TargetInstrDesc &TID = TII->get(Opc); unsigned NumRes = TID.getNumDefs(); unsigned NumOps = TID.getNumOperands() - NumRes; for (unsigned j = 0; j != NumOps; ++j) { if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) { - SDNode *DU = SU->Node->getOperand(j).Val; + SDNode *DU = SU->Node->getOperand(j).getNode(); if (DU->getNodeId() == -1) continue; const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; @@ -1768,7 +1762,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { // depth and height. if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1) continue; - if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode()) + if (!SuccSU->Node || !SuccSU->Node->isMachineOpcode()) continue; // Don't constrain nodes with physical register defs if the // predecessor can clobber them. @@ -1778,7 +1772,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { } // Don't constraint extract_subreg / insert_subreg these may be // coalesced away. We don't them close to their uses. - unsigned SuccOpc = SuccSU->Node->getTargetOpcode(); + unsigned SuccOpc = SuccSU->Node->getMachineOpcode(); if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || SuccOpc == TargetInstrInfo::INSERT_SUBREG) continue; @@ -1819,7 +1813,7 @@ static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU, unsigned Sum = 0; for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { - SUnit *SuccSU = I->Dep; + const SUnit *SuccSU = I->Dep; for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(), EE = SuccSU->Preds.end(); II != EE; ++II) { SUnit *PredSU = II->Dep; @@ -1836,8 +1830,8 @@ static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU, bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { unsigned LPriority = SPQ->getNodePriority(left); unsigned RPriority = SPQ->getNodePriority(right); - bool LIsTarget = left->Node && left->Node->isTargetOpcode(); - bool RIsTarget = right->Node && right->Node->isTargetOpcode(); + bool LIsTarget = left->Node && left->Node->isMachineOpcode(); + bool RIsTarget = right->Node && right->Node->isMachineOpcode(); bool LIsFloater = LIsTarget && left->NumPreds == 0; bool RIsFloater = RIsTarget && right->NumPreds == 0; unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0;