X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FScheduleDAGRRList.cpp;h=c605292695bc911220dc55e2a70b084ba7415dbc;hb=ee4c619b3b28a42078fc8033e5dccd42fc6edd42;hp=338035a4879a268af8385dfc68195d27b5faec9a;hpb=e5a8dc5cc4647cdfd97c71165d4c8f805b4c78a3;p=oota-llvm.git

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 338035a4879..c605292695b 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -41,11 +41,11 @@ STATISTIC(NumCCCopies,   "Number of cross class copies");
 
 static RegisterScheduler
   burrListDAGScheduler("list-burr",
-                       "  Bottom-up register reduction list scheduling",
+                       "Bottom-up register reduction list scheduling",
                        createBURRListDAGScheduler);
 static RegisterScheduler
   tdrListrDAGScheduler("list-tdrr",
-                       "  Top-down register reduction list scheduling",
+                       "Top-down register reduction list scheduling",
                        createTDRRListDAGScheduler);
 
 namespace {
@@ -66,10 +66,10 @@ private:
   /// AvailableQueue - The priority queue to use for the available SUnits.
   SchedulingPriorityQueue *AvailableQueue;
 
-  /// LiveRegs / LiveRegDefs - A set of physical registers and their definition
+  /// LiveRegDefs - A set of physical registers and their definition
   /// that are "live". These nodes must be scheduled before any other nodes that
   /// modifies the registers can be scheduled.
-  SmallSet<unsigned, 4> LiveRegs;
+  unsigned NumLiveRegs;
   std::vector<SUnit*> LiveRegDefs;
   std::vector<unsigned> LiveRegCycles;
 
@@ -178,6 +178,7 @@ private:
 void ScheduleDAGRRList::Schedule() {
   DOUT << "********** List Scheduling **********\n";
 
+  NumLiveRegs = 0;
   LiveRegDefs.resize(TRI->getNumRegs(), NULL);  
   LiveRegCycles.resize(TRI->getNumRegs(), 0);
 
@@ -224,7 +225,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
         if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
           continue;
 
-        SDNode *OpN = SU->Node->getOperand(j).Val;
+        SDNode *OpN = SU->Node->getOperand(j).getNode();
         SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
         if (OpSU && OperandSeen.count(OpSU) == 1) {
           // Ok, so SU is not the last use of OpSU, but SU is two-address so
@@ -233,7 +234,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
           bool DoCommute = true;
           for (unsigned k = 0; k < NumOps; ++k) {
             if (k != j) {
-              OpN = SU->Node->getOperand(k).Val;
+              OpN = SU->Node->getOperand(k).getNode();
               OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
               if (OpSU && OperandSeen.count(OpSU) == 1) {
                 DoCommute = false;
@@ -308,7 +309,8 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
       // expensive to copy the register. Make sure nothing that can 
       // clobber the register is scheduled between the predecessor and
       // this node.
-      if (LiveRegs.insert(I->Reg)) {
+      if (!LiveRegDefs[I->Reg]) {
+        ++NumLiveRegs;
         LiveRegDefs[I->Reg] = I->Dep;
         LiveRegCycles[I->Reg] = CurCycle;
       }
@@ -320,9 +322,10 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
        I != E; ++I) {
     if (I->Cost < 0)  {
       if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
-        LiveRegs.erase(I->Reg);
+        assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
         assert(LiveRegDefs[I->Reg] == SU &&
                "Physical register dependency violated?");
+        --NumLiveRegs;
         LiveRegDefs[I->Reg] = NULL;
         LiveRegCycles[I->Reg] = 0;
       }
@@ -367,9 +370,10 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
        I != E; ++I) {
     CapturePred(I->Dep, SU, I->isCtrl);
     if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg])  {
-      LiveRegs.erase(I->Reg);
+      assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
       assert(LiveRegDefs[I->Reg] == I->Dep &&
              "Physical register dependency violated?");
+      --NumLiveRegs;
       LiveRegDefs[I->Reg] = NULL;
       LiveRegCycles[I->Reg] = 0;
     }
@@ -378,10 +382,9 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
   for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
        I != E; ++I) {
     if (I->Cost < 0)  {
-      if (LiveRegs.insert(I->Reg)) {
-        assert(!LiveRegDefs[I->Reg] &&
-               "Physical register dependency violated?");
+      if (!LiveRegDefs[I->Reg]) {
         LiveRegDefs[I->Reg] = SU;
+        ++NumLiveRegs;
       }
       if (I->Dep->Cycle < LiveRegCycles[I->Reg])
         LiveRegCycles[I->Reg] = I->Dep->Cycle;
@@ -641,7 +644,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
   }
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     const SDValue &Op = N->getOperand(i);
-    MVT VT = Op.Val->getValueType(Op.getResNo());
+    MVT VT = Op.getNode()->getValueType(Op.getResNo());
     if (VT == MVT::Flag)
       return NULL;
   }
@@ -878,7 +881,7 @@ static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
 /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
 bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
                                                  SmallVector<unsigned, 4> &LRegs){
-  if (LiveRegs.empty())
+  if (NumLiveRegs == 0)
     return false;
 
   SmallSet<unsigned, 4> RegAdded;
@@ -887,13 +890,13 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
        I != E; ++I) {
     if (I->Cost < 0)  {
       unsigned Reg = I->Reg;
-      if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
+      if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) {
         if (RegAdded.insert(Reg))
           LRegs.push_back(Reg);
       }
       for (const unsigned *Alias = TRI->getAliasSet(Reg);
            *Alias; ++Alias)
-        if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
+        if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) {
           if (RegAdded.insert(*Alias))
             LRegs.push_back(*Alias);
         }
@@ -908,13 +911,13 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
     if (!TID.ImplicitDefs)
       continue;
     for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
-      if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
+      if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) {
         if (RegAdded.insert(*Reg))
           LRegs.push_back(*Reg);
       }
       for (const unsigned *Alias = TRI->getAliasSet(*Reg);
            *Alias; ++Alias)
-        if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
+        if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
           if (RegAdded.insert(*Alias))
             LRegs.push_back(*Alias);
         }
@@ -930,7 +933,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
   unsigned CurCycle = 0;
   // Add root to Available queue.
   if (!SUnits.empty()) {
-    SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()];
+    SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()];
     assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
     RootSU->isAvailable = true;
     AvailableQueue->push(RootSU);
@@ -1668,7 +1671,7 @@ BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) {
     unsigned NumOps = TID.getNumOperands() - NumRes;
     for (unsigned i = 0; i != NumOps; ++i) {
       if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
-        SDNode *DU = SU->Node->getOperand(i).Val;
+        SDNode *DU = SU->Node->getOperand(i).getNode();
         if (DU->getNodeId() != -1 &&
             Op->OrigNode == &(*SUnits)[DU->getNodeId()])
           return true;
@@ -1709,6 +1712,8 @@ static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
     MVT VT = N->getValueType(i);
     if (VT == MVT::Flag || VT == MVT::Other)
       continue;
+    if (!N->hasAnyUseOfValue(i))
+      continue;
     unsigned Reg = ImpDefs[i - NumDefs];
     for (;*SUImpDefs; ++SUImpDefs) {
       unsigned SUReg = *SUImpDefs;
@@ -1742,7 +1747,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
     unsigned NumOps = TID.getNumOperands() - NumRes;
     for (unsigned j = 0; j != NumOps; ++j) {
       if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
-        SDNode *DU = SU->Node->getOperand(j).Val;
+        SDNode *DU = SU->Node->getOperand(j).getNode();
         if (DU->getNodeId() == -1)
           continue;
         const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];