X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FScheduleDAGRRList.cpp;h=c605292695bc911220dc55e2a70b084ba7415dbc;hb=f9410141f703f4e8a6aba717617ef958249f6d13;hp=ec32be6e2663b7dadaa2bd53702e3b084fefc076;hpb=e513ba49589bcf8fdf7dad658e20db21d6ef4758;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index ec32be6e266..c605292695b 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1,4 +1,4 @@ -//===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===// +//===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===// // // The LLVM Compiler Infrastructure // @@ -24,11 +24,13 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/PriorityQueue.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include -#include #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -39,11 +41,11 @@ STATISTIC(NumCCCopies, "Number of cross class copies"); static RegisterScheduler burrListDAGScheduler("list-burr", - " Bottom-up register reduction list scheduling", + "Bottom-up register reduction list scheduling", createBURRListDAGScheduler); static RegisterScheduler tdrListrDAGScheduler("list-tdrr", - " Top-down register reduction list scheduling", + "Top-down register reduction list scheduling", createTDRRListDAGScheduler); namespace { @@ -56,22 +58,26 @@ private: /// isBottomUp - This is true if the scheduling problem is bottom-up, false if /// it is top-down. bool isBottomUp; + + /// Fast - True if we are performing fast scheduling. + /// + bool Fast; /// AvailableQueue - The priority queue to use for the available SUnits. SchedulingPriorityQueue *AvailableQueue; - /// LiveRegs / LiveRegDefs - A set of physical registers and their definition + /// LiveRegDefs - A set of physical registers and their definition /// that are "live". These nodes must be scheduled before any other nodes that /// modifies the registers can be scheduled. - SmallSet LiveRegs; + unsigned NumLiveRegs; std::vector LiveRegDefs; std::vector LiveRegCycles; public: ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb, - const TargetMachine &tm, bool isbottomup, - SchedulingPriorityQueue *availqueue) - : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup), + const TargetMachine &tm, bool isbottomup, bool f, + SchedulingPriorityQueue *availqueue) + : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup), Fast(f), AvailableQueue(availqueue) { } @@ -81,8 +87,8 @@ public: void Schedule(); - /// IsReachable - Checks if SU is reachable from TargetSU - bool IsReachable(SUnit *SU, SUnit *TargetSU); + /// IsReachable - Checks if SU is reachable from TargetSU. + bool IsReachable(const SUnit *SU, const SUnit *TargetSU); /// willCreateCycle - Returns true if adding an edge from SU to TargetSU will /// create a cycle. @@ -90,13 +96,13 @@ public: /// AddPred - This adds the specified node X as a predecessor of /// the current node Y if not already. - /// This returns true if this is a new pred. - /// Updates the topological oredering if required. + /// This returns true if this is a new predecessor. + /// Updates the topological ordering if required. bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial, - unsigned PhyReg = 0, int Cost = 1); + unsigned PhyReg = 0, int Cost = 1); - /// RemovePred - This removes the specified node N from predecessors of - /// the current node M. Updates the topological oredering if required + /// RemovePred - This removes the specified node N from the predecessors of + /// the current node M. Updates the topological ordering if required. bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isSpecial); private: @@ -119,20 +125,20 @@ private: /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it. - /// Updates the topological oredering if required. + /// Updates the topological ordering if required. SUnit *CreateNewSUnit(SDNode *N) { SUnit *NewNode = NewSUnit(N); - // Update the topologic ordering + // Update the topological ordering. if (NewNode->NodeNum >= Node2Index.size()) InitDAGTopologicalSorting(); return NewNode; } - /// CreateClone - Creates a new SUnit from old one. - /// Updates the topological oredering if required. + /// CreateClone - Creates a new SUnit from an existing one. + /// Updates the topological ordering if required. SUnit *CreateClone(SUnit *N) { SUnit *NewNode = Clone(N); - // Update the topologic ordering + // Update the topological ordering. if (NewNode->NodeNum >= Node2Index.size()) InitDAGTopologicalSorting(); return NewNode; @@ -140,59 +146,29 @@ private: /// Functions for preserving the topological ordering /// even after dynamic insertions of new edges. - /// This allows for very fast implementation of IsReachable. - - - /** - The idea of the algorithm is taken from - "Online algorithms for managing the topological order of - a directed acyclic graph" by David J.Pearce and Paul H.J. Kelly - This is the MNR algorithm, which is first introduced by - A.Marchetti-Spaccamela, U.Nanni and H.Rohnert in - "Maintaining a topological order under edge insertions". - - Short description of the algorithm: - - Topological ordering, ord, of a DAG maps each node to a topological - index so that fall all edges X->Y it is the case that ord(X) < ord(Y). - - This means that if there is a path from the node X to the node Z, - then ord(X) < ord(Z). - - This property can be used to check for reachability of nodes: - if Z is reachable from X, then an insertion of the edge Z->X would - create a cycle. - - Algorithm first computes a topological ordering for a DAG by initializing - the Index2Node and Node2Index arrays and then tries to keep the ordering - up-to-date after edge insertions by reordering the DAG. - - On insertion of the edge X->Y, the algorithm first marks by calling DFS the - nodes reachable from Y, and then shifts them using Shift to lie immediately - after X in Index2Node. - */ + /// This allows a very fast implementation of IsReachable. - /// InitDAGTopologicalSorting - create the initial topological - /// ordering from the DAG to be scheduled + /// InitDAGTopologicalSorting - create the initial topological + /// ordering from the DAG to be scheduled. void InitDAGTopologicalSorting(); /// DFS - make a DFS traversal and mark all nodes affected by the - /// edge insertion. These nodes should later get new topological indexes - /// by means of Shift method - void DFS(SUnit *SU, int UpperBound, bool& HasLoop); + /// edge insertion. These nodes will later get new topological indexes + /// by means of the Shift method. + void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); /// Shift - reassign topological indexes for the nodes in the DAG - /// to preserve the topological ordering + /// to preserve the topological ordering. void Shift(BitVector& Visited, int LowerBound, int UpperBound); - /// Allocate - assign the topological index to a node n + /// Allocate - assign the topological index to the node n. void Allocate(int n, int index); - /// Index2Node - Maps topological index to the node number + /// Index2Node - Maps topological index to the node number. std::vector Index2Node; - /// Node2Index - Maps the node number to its topological index + /// Node2Index - Maps the node number to its topological index. std::vector Node2Index; - /// Visited - a set of nodes visited during a DFS traversal + /// Visited - a set of nodes visited during a DFS traversal. BitVector Visited; }; } // end anonymous namespace @@ -202,6 +178,7 @@ private: void ScheduleDAGRRList::Schedule() { DOUT << "********** List Scheduling **********\n"; + NumLiveRegs = 0; LiveRegDefs.resize(TRI->getNumRegs(), NULL); LiveRegCycles.resize(TRI->getNumRegs(), 0); @@ -210,11 +187,13 @@ void ScheduleDAGRRList::Schedule() { DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su].dumpAll(&DAG)); - CalculateDepths(); - CalculateHeights(); + if (!Fast) { + CalculateDepths(); + CalculateHeights(); + } InitDAGTopologicalSorting(); - AvailableQueue->initNodes(SUnitMap, SUnits); + AvailableQueue->initNodes(SUnits); // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate. if (isBottomUp) @@ -223,15 +202,9 @@ void ScheduleDAGRRList::Schedule() { ListScheduleTopDown(); AvailableQueue->releaseState(); - - CommuteNodesToReducePressure(); - - DOUT << "*** Final schedule ***\n"; - DEBUG(dumpSchedule()); - DOUT << "\n"; - - // Emit in scheduled order - EmitSchedule(); + + if (!Fast) + CommuteNodesToReducePressure(); } /// CommuteNodesToReducePressure - If a node is two-address and commutable, and @@ -239,11 +212,12 @@ void ScheduleDAGRRList::Schedule() { /// possible. It will be commuted when it is translated to a MI. void ScheduleDAGRRList::CommuteNodesToReducePressure() { SmallPtrSet OperandSeen; - for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node. + for (unsigned i = Sequence.size(); i != 0; ) { + --i; SUnit *SU = Sequence[i]; if (!SU || !SU->Node) continue; if (SU->isCommutable) { - unsigned Opc = SU->Node->getTargetOpcode(); + unsigned Opc = SU->Node->getMachineOpcode(); const TargetInstrDesc &TID = TII->get(Opc); unsigned NumRes = TID.getNumDefs(); unsigned NumOps = TID.getNumOperands() - NumRes; @@ -251,8 +225,8 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1) continue; - SDNode *OpN = SU->Node->getOperand(j).Val; - SUnit *OpSU = isPassiveNode(OpN) ? NULL : SUnitMap[OpN][SU->InstanceNo]; + SDNode *OpN = SU->Node->getOperand(j).getNode(); + SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()]; if (OpSU && OperandSeen.count(OpSU) == 1) { // Ok, so SU is not the last use of OpSU, but SU is two-address so // it will clobber OpSU. Try to commute SU if no other source operands @@ -260,8 +234,8 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { bool DoCommute = true; for (unsigned k = 0; k < NumOps; ++k) { if (k != j) { - OpN = SU->Node->getOperand(k).Val; - OpSU = isPassiveNode(OpN) ? NULL : SUnitMap[OpN][SU->InstanceNo]; + OpN = SU->Node->getOperand(k).getNode(); + OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()]; if (OpSU && OperandSeen.count(OpSU) == 1) { DoCommute = false; break; @@ -280,7 +254,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { if (!I->isCtrl) - OperandSeen.insert(I->Dep); + OperandSeen.insert(I->Dep->OrigNode); } } } @@ -311,11 +285,8 @@ void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain, #endif if (PredSU->NumSuccsLeft == 0) { - // EntryToken has to go last! Special case it here. - if (!PredSU->Node || PredSU->Node->getOpcode() != ISD::EntryToken) { - PredSU->isAvailable = true; - AvailableQueue->push(PredSU); - } + PredSU->isAvailable = true; + AvailableQueue->push(PredSU); } } @@ -338,7 +309,8 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { // expensive to copy the register. Make sure nothing that can // clobber the register is scheduled between the predecessor and // this node. - if (LiveRegs.insert(I->Reg)) { + if (!LiveRegDefs[I->Reg]) { + ++NumLiveRegs; LiveRegDefs[I->Reg] = I->Dep; LiveRegCycles[I->Reg] = CurCycle; } @@ -350,9 +322,10 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { I != E; ++I) { if (I->Cost < 0) { if (LiveRegCycles[I->Reg] == I->Dep->Cycle) { - LiveRegs.erase(I->Reg); + assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!"); assert(LiveRegDefs[I->Reg] == SU && "Physical register dependency violated?"); + --NumLiveRegs; LiveRegDefs[I->Reg] = NULL; LiveRegCycles[I->Reg] = 0; } @@ -365,14 +338,14 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) { /// CapturePred - This does the opposite of ReleasePred. Since SU is being /// unscheduled, incrcease the succ left count of its predecessors. Remove /// them from AvailableQueue if necessary. -void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { - PredSU->CycleBound = 0; +void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { + unsigned CycleBound = 0; for (SUnit::succ_iterator I = PredSU->Succs.begin(), E = PredSU->Succs.end(); I != E; ++I) { if (I->Dep == SU) continue; - PredSU->CycleBound = std::max(PredSU->CycleBound, - I->Dep->Cycle + PredSU->Latency); + CycleBound = std::max(CycleBound, + I->Dep->Cycle + PredSU->Latency); } if (PredSU->isAvailable) { @@ -381,6 +354,7 @@ void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) { AvailableQueue->remove(PredSU); } + PredSU->CycleBound = CycleBound; ++PredSU->NumSuccsLeft; } @@ -396,9 +370,10 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { I != E; ++I) { CapturePred(I->Dep, SU, I->isCtrl); if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) { - LiveRegs.erase(I->Reg); + assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!"); assert(LiveRegDefs[I->Reg] == I->Dep && "Physical register dependency violated?"); + --NumLiveRegs; LiveRegDefs[I->Reg] = NULL; LiveRegCycles[I->Reg] = 0; } @@ -407,10 +382,9 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { if (I->Cost < 0) { - if (LiveRegs.insert(I->Reg)) { - assert(!LiveRegDefs[I->Reg] && - "Physical register dependency violated?"); + if (!LiveRegDefs[I->Reg]) { LiveRegDefs[I->Reg] = SU; + ++NumLiveRegs; } if (I->Dep->Cycle < LiveRegCycles[I->Reg]) LiveRegCycles[I->Reg] = I->Dep->Cycle; @@ -424,9 +398,9 @@ void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { } /// IsReachable - Checks if SU is reachable from TargetSU. -bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) { - // If insertion of the edge SU->TargetSU would creates a cycle - // then there is a path from TargetSU to SU +bool ScheduleDAGRRList::IsReachable(const SUnit *SU, const SUnit *TargetSU) { + // If insertion of the edge SU->TargetSU would create a cycle + // then there is a path from TargetSU to SU. int UpperBound, LowerBound; LowerBound = Node2Index[TargetSU->NodeNum]; UpperBound = Node2Index[SU->NodeNum]; @@ -440,66 +414,82 @@ bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) { return HasLoop; } -/// Allocate - assign the topological index to a node n +/// Allocate - assign the topological index to the node n. inline void ScheduleDAGRRList::Allocate(int n, int index) { Node2Index[n] = index; Index2Node[index] = n; } -/// InitDAGTopologicalSorting - create the initial topological -/// ordering from the DAG to be scheduled. +/// InitDAGTopologicalSorting - create the initial topological +/// ordering from the DAG to be scheduled. + +/// The idea of the algorithm is taken from +/// "Online algorithms for managing the topological order of +/// a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly +/// This is the MNR algorithm, which was first introduced by +/// A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in +/// "Maintaining a topological order under edge insertions". +/// +/// Short description of the algorithm: +/// +/// Topological ordering, ord, of a DAG maps each node to a topological +/// index so that for all edges X->Y it is the case that ord(X) < ord(Y). +/// +/// This means that if there is a path from the node X to the node Z, +/// then ord(X) < ord(Z). +/// +/// This property can be used to check for reachability of nodes: +/// if Z is reachable from X, then an insertion of the edge Z->X would +/// create a cycle. +/// +/// The algorithm first computes a topological ordering for the DAG by +/// initializing the Index2Node and Node2Index arrays and then tries to keep +/// the ordering up-to-date after edge insertions by reordering the DAG. +/// +/// On insertion of the edge X->Y, the algorithm first marks by calling DFS +/// the nodes reachable from Y, and then shifts them using Shift to lie +/// immediately after X in Index2Node. void ScheduleDAGRRList::InitDAGTopologicalSorting() { unsigned DAGSize = SUnits.size(); - std::vector InDegree(DAGSize); std::vector WorkList; WorkList.reserve(DAGSize); - std::vector TopOrder; - TopOrder.reserve(DAGSize); - // Initialize the data structures + Index2Node.resize(DAGSize); + Node2Index.resize(DAGSize); + + // Initialize the data structures. for (unsigned i = 0, e = DAGSize; i != e; ++i) { SUnit *SU = &SUnits[i]; int NodeNum = SU->NodeNum; unsigned Degree = SU->Succs.size(); - InDegree[NodeNum] = Degree; + // Temporarily use the Node2Index array as scratch space for degree counts. + Node2Index[NodeNum] = Degree; // Is it a node without dependencies? if (Degree == 0) { assert(SU->Succs.empty() && "SUnit should have no successors"); - // Collect leaf nodes + // Collect leaf nodes. WorkList.push_back(SU); } } + int Id = DAGSize; while (!WorkList.empty()) { SUnit *SU = WorkList.back(); WorkList.pop_back(); - TopOrder.push_back(SU); + Allocate(SU->NodeNum, --Id); for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { SUnit *SU = I->Dep; - if (!--InDegree[SU->NodeNum]) + if (!--Node2Index[SU->NodeNum]) // If all dependencies of the node are processed already, - // then the node can be computed now + // then the node can be computed now. WorkList.push_back(SU); } } - // Second pass, assign the actual topological order as node ids. - int Id = 0; - - Index2Node.clear(); - Node2Index.clear(); - Index2Node.resize(DAGSize); - Node2Index.resize(DAGSize); Visited.resize(DAGSize); - for (std::vector::reverse_iterator TI = TopOrder.rbegin(), - TE = TopOrder.rend();TI != TE; ++TI) { - Allocate((*TI)->NodeNum, Id); - Id++; - } - #ifndef NDEBUG // Check correctness of the ordering for (unsigned i = 0, e = DAGSize; i != e; ++i) { @@ -513,8 +503,8 @@ void ScheduleDAGRRList::InitDAGTopologicalSorting() { #endif } -/// AddPred - adds edge from SUnit X to SUnit Y -/// Updates the topological oredering if required. +/// AddPred - adds an edge from SUnit X to SUnit Y. +/// Updates the topological ordering if required. bool ScheduleDAGRRList::AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial, unsigned PhyReg, int Cost) { int UpperBound, LowerBound; @@ -523,28 +513,30 @@ bool ScheduleDAGRRList::AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial, bool HasLoop = false; // Is Ord(X) < Ord(Y) ? if (LowerBound < UpperBound) { - // Update the topological order + // Update the topological order. Visited.reset(); DFS(Y, UpperBound, HasLoop); assert(!HasLoop && "Inserted edge creates a loop!"); - // Recompute topological indexes + // Recompute topological indexes. Shift(Visited, LowerBound, UpperBound); } - // Now really insert the edge - return Y->addPred(X,isCtrl,isSpecial,PhyReg,Cost); + // Now really insert the edge. + return Y->addPred(X, isCtrl, isSpecial, PhyReg, Cost); } -/// RemovePred - This removes the specified node N from preds of -/// the current node M. Updates the topological oredering if required +/// RemovePred - This removes the specified node N from the predecessors of +/// the current node M. Updates the topological ordering if required. bool ScheduleDAGRRList::RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isSpecial) { // InitDAGTopologicalSorting(); return M->removePred(N, isCtrl, isSpecial); } -/// DFS - make a DFS traversal to mark all nodes reachable from SU and and mark /// all nodes affected by the edge insertion. These nodes should later get new /// topological indexes by means of the Shift method -void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) { - std::vector WorkList; +/// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark +/// all nodes affected by the edge insertion. These nodes will later get new +/// topological indexes by means of the Shift method. +void ScheduleDAGRRList::DFS(const SUnit *SU, int UpperBound, bool& HasLoop) { + std::vector WorkList; WorkList.reserve(SUnits.size()); WorkList.push_back(SU); @@ -558,7 +550,7 @@ void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) { HasLoop = true; return; } - // Visit successors if not already and is in affected region + // Visit successors if not already and in affected region. if (!Visited.test(s) && Node2Index[s] < UpperBound) { WorkList.push_back(SU->Succs[I].Dep); } @@ -566,8 +558,8 @@ void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) { } } -/// Shift - renumber the nodes so that the topological ordering is -/// preserved +/// Shift - Renumber the nodes so that the topological ordering is +/// preserved. void ScheduleDAGRRList::Shift(BitVector& Visited, int LowerBound, int UpperBound) { std::vector L; @@ -575,10 +567,10 @@ void ScheduleDAGRRList::Shift(BitVector& Visited, int LowerBound, int i; for (i = LowerBound; i <= UpperBound; ++i) { - // w is node at topological index i + // w is node at topological index i. int w = Index2Node[i]; if (Visited.test(w)) { - // Unmark + // Unmark. Visited.reset(w); L.push_back(w); shift = shift + 1; @@ -644,21 +636,21 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { SUnit *NewSU; bool TryUnfold = false; for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { - MVT::ValueType VT = N->getValueType(i); + MVT VT = N->getValueType(i); if (VT == MVT::Flag) return NULL; else if (VT == MVT::Other) TryUnfold = true; } for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { - const SDOperand &Op = N->getOperand(i); - MVT::ValueType VT = Op.Val->getValueType(Op.ResNo); + const SDValue &Op = N->getOperand(i); + MVT VT = Op.getNode()->getValueType(Op.getResNo()); if (VT == MVT::Flag) return NULL; } if (TryUnfold) { - SmallVector NewNodes; + SmallVector NewNodes; if (!TII->unfoldMemoryOperand(DAG, N, NewNodes)) return NULL; @@ -670,13 +662,15 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { unsigned NumVals = N->getNumValues(); unsigned OldNumVals = SU->Node->getNumValues(); for (unsigned i = 0; i != NumVals; ++i) - DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i)); - DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1), - SDOperand(LoadNode, 1)); + DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, i), SDValue(N, i)); + DAG.ReplaceAllUsesOfValueWith(SDValue(SU->Node, OldNumVals-1), + SDValue(LoadNode, 1)); SUnit *NewSU = CreateNewSUnit(N); - SUnitMap[N].push_back(NewSU); - const TargetInstrDesc &TID = TII->get(N->getTargetOpcode()); + assert(N->getNodeId() == -1 && "Node already inserted!"); + N->setNodeId(NewSU->NodeNum); + + const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); for (unsigned i = 0; i != TID.getNumOperands(); ++i) { if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { NewSU->isTwoAddress = true; @@ -695,14 +689,12 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { // but it has different alignment or volatileness. bool isNewLoad = true; SUnit *LoadSU; - DenseMap >::iterator SMI = - SUnitMap.find(LoadNode); - if (SMI != SUnitMap.end()) { - LoadSU = SMI->second.front(); + if (LoadNode->getNodeId() != -1) { + LoadSU = &SUnits[LoadNode->getNodeId()]; isNewLoad = false; } else { LoadSU = CreateNewSUnit(LoadNode); - SUnitMap[LoadNode].push_back(LoadSU); + LoadNode->setNodeId(LoadSU->NodeNum); LoadSU->Depth = SU->Depth; LoadSU->Height = SU->Height; @@ -733,36 +725,37 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { I->isCtrl, I->isSpecial)); } - RemovePred(SU, ChainPred, true, false); - if (isNewLoad) { - AddPred(LoadSU,ChainPred, true, false); + if (ChainPred) { + RemovePred(SU, ChainPred, true, false); + if (isNewLoad) + AddPred(LoadSU, ChainPred, true, false); } for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) { SDep *Pred = &LoadPreds[i]; RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial); if (isNewLoad) { AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial, - Pred->Reg, Pred->Cost); + Pred->Reg, Pred->Cost); } } for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) { SDep *Pred = &NodePreds[i]; RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial); AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial, - Pred->Reg, Pred->Cost); + Pred->Reg, Pred->Cost); } for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) { SDep *Succ = &NodeSuccs[i]; RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial); AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isSpecial, - Succ->Reg, Succ->Cost); + Succ->Reg, Succ->Cost); } for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) { SDep *Succ = &ChainSuccs[i]; RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial); if (isNewLoad) { AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isSpecial, - Succ->Reg, Succ->Cost); + Succ->Reg, Succ->Cost); } } if (isNewLoad) { @@ -869,9 +862,9 @@ void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, /// getPhysicalRegisterVT - Returns the ValueType of the physical register /// definition of the specified node. /// FIXME: Move to SelectionDAG? -static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg, - const TargetInstrInfo *TII) { - const TargetInstrDesc &TID = TII->get(N->getTargetOpcode()); +static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, + const TargetInstrInfo *TII) { + const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); unsigned NumRes = TID.getNumDefs(); for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) { @@ -888,7 +881,7 @@ static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg, /// whatever is necessary (i.e. backtracking or cloning) to make it possible. bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, SmallVector &LRegs){ - if (LiveRegs.empty()) + if (NumLiveRegs == 0) return false; SmallSet RegAdded; @@ -897,13 +890,13 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, I != E; ++I) { if (I->Cost < 0) { unsigned Reg = I->Reg; - if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) { + if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != I->Dep) { if (RegAdded.insert(Reg)) LRegs.push_back(Reg); } for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) - if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { + if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != I->Dep) { if (RegAdded.insert(*Alias)) LRegs.push_back(*Alias); } @@ -912,19 +905,19 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) { SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1]; - if (!Node || !Node->isTargetOpcode()) + if (!Node || !Node->isMachineOpcode()) continue; - const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode()); + const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode()); if (!TID.ImplicitDefs) continue; for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) { - if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) { + if (LiveRegDefs[*Reg] && LiveRegDefs[*Reg] != SU) { if (RegAdded.insert(*Reg)) LRegs.push_back(*Reg); } for (const unsigned *Alias = TRI->getAliasSet(*Reg); *Alias; ++Alias) - if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { + if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) { if (RegAdded.insert(*Alias)) LRegs.push_back(*Alias); } @@ -939,16 +932,21 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, void ScheduleDAGRRList::ListScheduleBottomUp() { unsigned CurCycle = 0; // Add root to Available queue. - SUnit *RootSU = SUnitMap[DAG.getRoot().Val].front(); - RootSU->isAvailable = true; - AvailableQueue->push(RootSU); + if (!SUnits.empty()) { + SUnit *RootSU = &SUnits[DAG.getRoot().getNode()->getNodeId()]; + assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!"); + RootSU->isAvailable = true; + AvailableQueue->push(RootSU); + } // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. SmallVector NotReady; + DenseMap > LRegsMap; + Sequence.reserve(SUnits.size()); while (!AvailableQueue->empty()) { bool Delayed = false; - DenseMap > LRegsMap; + LRegsMap.clear(); SUnit *CurSU = AvailableQueue->pop(); while (CurSU) { if (CurSU->CycleBound <= CurCycle) { @@ -1016,7 +1014,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { SUnit *NewDef = CopyAndMoveSuccessors(LRDef); if (!NewDef) { // Issue expensive cross register class copies. - MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); + MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); const TargetRegisterClass *RC = TRI->getPhysicalRegisterRegClass(Reg, VT); const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); @@ -1064,12 +1062,6 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { ++CurCycle; } - // Add entry node last - if (DAG.getEntryNode().Val != DAG.getRoot().Val) { - SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front(); - Sequence.push_back(Entry); - } - // Reverse the order if it is bottom up. std::reverse(Sequence.begin(), Sequence.end()); @@ -1077,16 +1069,34 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { #ifndef NDEBUG // Verify that all SUnits were scheduled. bool AnyNotSched = false; + unsigned DeadNodes = 0; + unsigned Noops = 0; for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { - if (SUnits[i].NumSuccsLeft != 0) { + if (!SUnits[i].isScheduled) { + if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { + ++DeadNodes; + continue; + } if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; SUnits[i].dump(&DAG); cerr << "has not been scheduled!\n"; AnyNotSched = true; } + if (SUnits[i].NumSuccsLeft != 0) { + if (!AnyNotSched) + cerr << "*** List scheduling failed! ***\n"; + SUnits[i].dump(&DAG); + cerr << "has successors left!\n"; + AnyNotSched = true; + } } + for (unsigned i = 0, e = Sequence.size(); i != e; ++i) + if (!Sequence[i]) + ++Noops; assert(!AnyNotSched); + assert(Sequence.size() + DeadNodes - Noops == SUnits.size() && + "The number of nodes scheduled doesn't match the expected number!"); #endif } @@ -1143,25 +1153,20 @@ void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { /// schedulers. void ScheduleDAGRRList::ListScheduleTopDown() { unsigned CurCycle = 0; - SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front(); // All leaves to Available queue. for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { // It is available if it has no predecessors. - if (SUnits[i].Preds.empty() && &SUnits[i] != Entry) { + if (SUnits[i].Preds.empty()) { AvailableQueue->push(&SUnits[i]); SUnits[i].isAvailable = true; } } - // Emit the entry node first. - ScheduleNodeTopDown(Entry, CurCycle); - Sequence.push_back(Entry); - ++CurCycle; - // While Available queue is not empty, grab the node with the highest // priority. If it is not ready put it back. Schedule the node. std::vector NotReady; + Sequence.reserve(SUnits.size()); while (!AvailableQueue->empty()) { SUnit *CurSU = AvailableQueue->pop(); while (CurSU && CurSU->CycleBound > CurCycle) { @@ -1179,23 +1184,41 @@ void ScheduleDAGRRList::ListScheduleTopDown() { ScheduleNodeTopDown(CurSU, CurCycle); Sequence.push_back(CurSU); } - CurCycle++; + ++CurCycle; } #ifndef NDEBUG // Verify that all SUnits were scheduled. bool AnyNotSched = false; + unsigned DeadNodes = 0; + unsigned Noops = 0; for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { if (!SUnits[i].isScheduled) { + if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) { + ++DeadNodes; + continue; + } if (!AnyNotSched) cerr << "*** List scheduling failed! ***\n"; SUnits[i].dump(&DAG); cerr << "has not been scheduled!\n"; AnyNotSched = true; } + if (SUnits[i].NumPredsLeft != 0) { + if (!AnyNotSched) + cerr << "*** List scheduling failed! ***\n"; + SUnits[i].dump(&DAG); + cerr << "has predecessors left!\n"; + AnyNotSched = true; + } } + for (unsigned i = 0, e = Sequence.size(); i != e; ++i) + if (!Sequence[i]) + ++Noops; assert(!AnyNotSched); + assert(Sequence.size() + DeadNodes - Noops == SUnits.size() && + "The number of nodes scheduled doesn't match the expected number!"); #endif } @@ -1221,6 +1244,15 @@ namespace { bool operator()(const SUnit* left, const SUnit* right) const; }; + struct bu_ls_rr_fast_sort : public std::binary_function{ + RegReductionPriorityQueue *SPQ; + bu_ls_rr_fast_sort(RegReductionPriorityQueue *spq) + : SPQ(spq) {} + bu_ls_rr_fast_sort(const bu_ls_rr_fast_sort &RHS) : SPQ(RHS.SPQ) {} + + bool operator()(const SUnit* left, const SUnit* right) const; + }; + struct td_ls_rr_sort : public std::binary_function { RegReductionPriorityQueue *SPQ; td_ls_rr_sort(RegReductionPriorityQueue *spq) : SPQ(spq) {} @@ -1236,18 +1268,88 @@ static inline bool isCopyFromLiveIn(const SUnit *SU) { N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag; } +/// CalcNodeBUSethiUllmanNumber - Compute Sethi Ullman number for bottom up +/// scheduling. Smaller number is the higher priority. +static unsigned +CalcNodeBUSethiUllmanNumber(const SUnit *SU, std::vector &SUNumbers) { + unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; + if (SethiUllmanNumber != 0) + return SethiUllmanNumber; + + unsigned Extra = 0; + for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); + I != E; ++I) { + if (I->isCtrl) continue; // ignore chain preds + SUnit *PredSU = I->Dep; + unsigned PredSethiUllman = CalcNodeBUSethiUllmanNumber(PredSU, SUNumbers); + if (PredSethiUllman > SethiUllmanNumber) { + SethiUllmanNumber = PredSethiUllman; + Extra = 0; + } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl) + ++Extra; + } + + SethiUllmanNumber += Extra; + + if (SethiUllmanNumber == 0) + SethiUllmanNumber = 1; + + return SethiUllmanNumber; +} + +/// CalcNodeTDSethiUllmanNumber - Compute Sethi Ullman number for top down +/// scheduling. Smaller number is the higher priority. +static unsigned +CalcNodeTDSethiUllmanNumber(const SUnit *SU, std::vector &SUNumbers) { + unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; + if (SethiUllmanNumber != 0) + return SethiUllmanNumber; + + unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0; + if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) + SethiUllmanNumber = 0xffff; + else if (SU->NumSuccsLeft == 0) + // If SU does not have a use, i.e. it doesn't produce a value that would + // be consumed (e.g. store), then it terminates a chain of computation. + // Give it a small SethiUllman number so it will be scheduled right before + // its predecessors that it doesn't lengthen their live ranges. + SethiUllmanNumber = 0; + else if (SU->NumPredsLeft == 0 && + (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU))) + SethiUllmanNumber = 0xffff; + else { + int Extra = 0; + for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); + I != E; ++I) { + if (I->isCtrl) continue; // ignore chain preds + SUnit *PredSU = I->Dep; + unsigned PredSethiUllman = CalcNodeTDSethiUllmanNumber(PredSU, SUNumbers); + if (PredSethiUllman > SethiUllmanNumber) { + SethiUllmanNumber = PredSethiUllman; + Extra = 0; + } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl) + ++Extra; + } + + SethiUllmanNumber += Extra; + } + + return SethiUllmanNumber; +} + + namespace { template class VISIBILITY_HIDDEN RegReductionPriorityQueue : public SchedulingPriorityQueue { - std::priority_queue, SF> Queue; + PriorityQueue, SF> Queue; + unsigned currentQueueId; public: RegReductionPriorityQueue() : - Queue(SF(this)) {} + Queue(SF(this)), currentQueueId(0) {} - virtual void initNodes(DenseMap > &sumap, - std::vector &sunits) {} + virtual void initNodes(std::vector &sunits) {} virtual void addNode(const SUnit *SU) {} @@ -1264,50 +1366,36 @@ namespace { bool empty() const { return Queue.empty(); } void push(SUnit *U) { + assert(!U->NodeQueueId && "Node in the queue already"); + U->NodeQueueId = ++currentQueueId; Queue.push(U); } + void push_all(const std::vector &Nodes) { for (unsigned i = 0, e = Nodes.size(); i != e; ++i) - Queue.push(Nodes[i]); + push(Nodes[i]); } SUnit *pop() { if (empty()) return NULL; SUnit *V = Queue.top(); Queue.pop(); + V->NodeQueueId = 0; return V; } - /// remove - This is a really inefficient way to remove a node from a - /// priority queue. We should roll our own heap to make this better or - /// something. void remove(SUnit *SU) { - std::vector Temp; - - assert(!Queue.empty() && "Not in queue!"); - while (Queue.top() != SU) { - Temp.push_back(Queue.top()); - Queue.pop(); - assert(!Queue.empty() && "Not in queue!"); - } - - // Remove the node from the PQ. - Queue.pop(); - - // Add all the other nodes back. - for (unsigned i = 0, e = Temp.size(); i != e; ++i) - Queue.push(Temp[i]); + assert(!Queue.empty() && "Queue is empty!"); + assert(SU->NodeQueueId != 0 && "Not in queue!"); + Queue.erase_one(SU); + SU->NodeQueueId = 0; } }; - template class VISIBILITY_HIDDEN BURegReductionPriorityQueue - : public RegReductionPriorityQueue { - // SUnitMap SDNode to SUnit mapping (n -> n). - DenseMap > *SUnitMap; - + : public RegReductionPriorityQueue { // SUnits - The SUnits for the current graph. - const std::vector *SUnits; + std::vector *SUnits; // SethiUllmanNumbers - The SethiUllman number for each node. std::vector SethiUllmanNumbers; @@ -1315,14 +1403,13 @@ namespace { const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; ScheduleDAGRRList *scheduleDAG; + public: explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii, const TargetRegisterInfo *tri) : TII(tii), TRI(tri), scheduleDAG(NULL) {} - void initNodes(DenseMap > &sumap, - std::vector &sunits) { - SUnitMap = &sumap; + void initNodes(std::vector &sunits) { SUnits = &sunits; // Add pseudo dependency edges for two-address nodes. AddPseudoTwoAddrDeps(); @@ -1331,13 +1418,15 @@ namespace { } void addNode(const SUnit *SU) { - SethiUllmanNumbers.resize(SUnits->size(), 0); - CalcNodeSethiUllmanNumber(SU); + unsigned SUSize = SethiUllmanNumbers.size(); + if (SUnits->size() > SUSize) + SethiUllmanNumbers.resize(SUSize*2, 0); + CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); } void updateNode(const SUnit *SU) { SethiUllmanNumbers[SU->NodeNum] = 0; - CalcNodeSethiUllmanNumber(SU); + CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); } void releaseState() { @@ -1384,16 +1473,53 @@ namespace { bool canClobber(const SUnit *SU, const SUnit *Op); void AddPseudoTwoAddrDeps(); void CalculateSethiUllmanNumbers(); - unsigned CalcNodeSethiUllmanNumber(const SUnit *SU); }; - template - class VISIBILITY_HIDDEN TDRegReductionPriorityQueue - : public RegReductionPriorityQueue { - // SUnitMap SDNode to SUnit mapping (n -> n). - DenseMap > *SUnitMap; + class VISIBILITY_HIDDEN BURegReductionFastPriorityQueue + : public RegReductionPriorityQueue { + // SUnits - The SUnits for the current graph. + const std::vector *SUnits; + + // SethiUllmanNumbers - The SethiUllman number for each node. + std::vector SethiUllmanNumbers; + public: + explicit BURegReductionFastPriorityQueue() {} + + void initNodes(std::vector &sunits) { + SUnits = &sunits; + // Calculate node priorities. + CalculateSethiUllmanNumbers(); + } + void addNode(const SUnit *SU) { + unsigned SUSize = SethiUllmanNumbers.size(); + if (SUnits->size() > SUSize) + SethiUllmanNumbers.resize(SUSize*2, 0); + CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); + } + + void updateNode(const SUnit *SU) { + SethiUllmanNumbers[SU->NodeNum] = 0; + CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); + } + + void releaseState() { + SUnits = 0; + SethiUllmanNumbers.clear(); + } + + unsigned getNodePriority(const SUnit *SU) const { + return SethiUllmanNumbers[SU->NodeNum]; + } + + private: + void CalculateSethiUllmanNumbers(); + }; + + + class VISIBILITY_HIDDEN TDRegReductionPriorityQueue + : public RegReductionPriorityQueue { // SUnits - The SUnits for the current graph. const std::vector *SUnits; @@ -1403,22 +1529,22 @@ namespace { public: TDRegReductionPriorityQueue() {} - void initNodes(DenseMap > &sumap, - std::vector &sunits) { - SUnitMap = &sumap; + void initNodes(std::vector &sunits) { SUnits = &sunits; // Calculate node priorities. CalculateSethiUllmanNumbers(); } void addNode(const SUnit *SU) { - SethiUllmanNumbers.resize(SUnits->size(), 0); - CalcNodeSethiUllmanNumber(SU); + unsigned SUSize = SethiUllmanNumbers.size(); + if (SUnits->size() > SUSize) + SethiUllmanNumbers.resize(SUSize*2, 0); + CalcNodeTDSethiUllmanNumber(SU, SethiUllmanNumbers); } void updateNode(const SUnit *SU) { SethiUllmanNumbers[SU->NodeNum] = 0; - CalcNodeSethiUllmanNumber(SU); + CalcNodeTDSethiUllmanNumber(SU, SethiUllmanNumbers); } void releaseState() { @@ -1433,7 +1559,6 @@ namespace { private: void CalculateSethiUllmanNumbers(); - unsigned CalcNodeSethiUllmanNumber(const SUnit *SU); }; } @@ -1476,19 +1601,6 @@ static unsigned calcMaxScratches(const SUnit *SU) { // Bottom up bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { - // There used to be a special tie breaker here that looked for - // two-address instructions and preferred the instruction with a - // def&use operand. The special case triggered diagnostics when - // _GLIBCXX_DEBUG was enabled because it broke the strict weak - // ordering that priority_queue requires. It didn't help much anyway - // because AddPseudoTwoAddrDeps already covers many of the cases - // where it would have applied. In addition, it's counter-intuitive - // that a tie breaker would be the first thing attempted. There's a - // "real" tie breaker below that is the operation of last resort. - // The fact that the "special tie breaker" would trigger when there - // wasn't otherwise a tie is what broke the strict weak ordering - // constraint. - unsigned LPriority = SPQ->getNodePriority(left); unsigned RPriority = SPQ->getNodePriority(right); if (LPriority != RPriority) @@ -1534,22 +1646,34 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { if (left->CycleBound != right->CycleBound) return left->CycleBound > right->CycleBound; - // FIXME: No strict ordering. - return false; + assert(left->NodeQueueId && right->NodeQueueId && + "NodeQueueId cannot be zero"); + return (left->NodeQueueId > right->NodeQueueId); } -template bool -BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) { +bool +bu_ls_rr_fast_sort::operator()(const SUnit *left, const SUnit *right) const { + unsigned LPriority = SPQ->getNodePriority(left); + unsigned RPriority = SPQ->getNodePriority(right); + if (LPriority != RPriority) + return LPriority > RPriority; + assert(left->NodeQueueId && right->NodeQueueId && + "NodeQueueId cannot be zero"); + return (left->NodeQueueId > right->NodeQueueId); +} + +bool +BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) { if (SU->isTwoAddress) { - unsigned Opc = SU->Node->getTargetOpcode(); + unsigned Opc = SU->Node->getMachineOpcode(); const TargetInstrDesc &TID = TII->get(Opc); unsigned NumRes = TID.getNumDefs(); unsigned NumOps = TID.getNumOperands() - NumRes; for (unsigned i = 0; i != NumOps; ++i) { if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) { - SDNode *DU = SU->Node->getOperand(i).Val; - if ((*SUnitMap).find(DU) != (*SUnitMap).end() && - Op == (*SUnitMap)[DU][SU->InstanceNo]) + SDNode *DU = SU->Node->getOperand(i).getNode(); + if (DU->getNodeId() != -1 && + Op->OrigNode == &(*SUnits)[DU->getNodeId()]) return true; } } @@ -1560,11 +1684,11 @@ BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) { /// hasCopyToRegUse - Return true if SU has a value successor that is a /// CopyToReg node. -static bool hasCopyToRegUse(SUnit *SU) { +static bool hasCopyToRegUse(const SUnit *SU) { for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { if (I->isCtrl) continue; - SUnit *SuccSU = I->Dep; + const SUnit *SuccSU = I->Dep; if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg) return true; } @@ -1572,23 +1696,24 @@ static bool hasCopyToRegUse(SUnit *SU) { } /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's -/// physical register def. -static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, +/// physical register defs. +static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) { SDNode *N = SuccSU->Node; - unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs(); - const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs(); - if (!ImpDefs) - return false; + unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); + const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); + assert(ImpDefs && "Caller should check hasPhysRegDefs"); const unsigned *SUImpDefs = - TII->get(SU->Node->getTargetOpcode()).getImplicitDefs(); + TII->get(SU->Node->getMachineOpcode()).getImplicitDefs(); if (!SUImpDefs) return false; for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { - MVT::ValueType VT = N->getValueType(i); + MVT VT = N->getValueType(i); if (VT == MVT::Flag || VT == MVT::Other) continue; + if (!N->hasAnyUseOfValue(i)) + continue; unsigned Reg = ImpDefs[i - NumDefs]; for (;*SUImpDefs; ++SUImpDefs) { unsigned SUReg = *SUImpDefs; @@ -1606,30 +1731,29 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, /// one that has a CopyToReg use (more likely to be a loop induction update). /// If both are two-address, but one is commutable while the other is not /// commutable, favor the one that's not commutable. -template -void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { +void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { for (unsigned i = 0, e = SUnits->size(); i != e; ++i) { - SUnit *SU = (SUnit *)&((*SUnits)[i]); + SUnit *SU = &(*SUnits)[i]; if (!SU->isTwoAddress) continue; SDNode *Node = SU->Node; - if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0) + if (!Node || !Node->isMachineOpcode() || SU->FlaggedNodes.size() > 0) continue; - unsigned Opc = Node->getTargetOpcode(); + unsigned Opc = Node->getMachineOpcode(); const TargetInstrDesc &TID = TII->get(Opc); unsigned NumRes = TID.getNumDefs(); unsigned NumOps = TID.getNumOperands() - NumRes; for (unsigned j = 0; j != NumOps; ++j) { if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) { - SDNode *DU = SU->Node->getOperand(j).Val; - if ((*SUnitMap).find(DU) == (*SUnitMap).end()) + SDNode *DU = SU->Node->getOperand(j).getNode(); + if (DU->getNodeId() == -1) continue; - SUnit *DUSU = (*SUnitMap)[DU][SU->InstanceNo]; + const SUnit *DUSU = &(*SUnits)[DU->getNodeId()]; if (!DUSU) continue; - for (SUnit::succ_iterator I = DUSU->Succs.begin(),E = DUSU->Succs.end(); - I != E; ++I) { + for (SUnit::const_succ_iterator I = DUSU->Succs.begin(), + E = DUSU->Succs.end(); I != E; ++I) { if (I->isCtrl) continue; SUnit *SuccSU = I->Dep; if (SuccSU == SU) @@ -1638,7 +1762,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { // depth and height. if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1) continue; - if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode()) + if (!SuccSU->Node || !SuccSU->Node->isMachineOpcode()) continue; // Don't constrain nodes with physical register defs if the // predecessor can clobber them. @@ -1648,7 +1772,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { } // Don't constraint extract_subreg / insert_subreg these may be // coalesced away. We don't them close to their uses. - unsigned SuccOpc = SuccSU->Node->getTargetOpcode(); + unsigned SuccOpc = SuccSU->Node->getMachineOpcode(); if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || SuccOpc == TargetInstrInfo::INSERT_SUBREG) continue; @@ -1666,59 +1790,38 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { } } -/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number. -/// Smaller number is the higher priority. -template -unsigned BURegReductionPriorityQueue:: -CalcNodeSethiUllmanNumber(const SUnit *SU) { - unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; - if (SethiUllmanNumber != 0) - return SethiUllmanNumber; - - unsigned Extra = 0; - for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); - I != E; ++I) { - if (I->isCtrl) continue; // ignore chain preds - SUnit *PredSU = I->Dep; - unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU); - if (PredSethiUllman > SethiUllmanNumber) { - SethiUllmanNumber = PredSethiUllman; - Extra = 0; - } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl) - ++Extra; - } - - SethiUllmanNumber += Extra; - - if (SethiUllmanNumber == 0) - SethiUllmanNumber = 1; - - return SethiUllmanNumber; -} - /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all /// scheduling units. -template -void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() { +void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() { + SethiUllmanNumbers.assign(SUnits->size(), 0); + + for (unsigned i = 0, e = SUnits->size(); i != e; ++i) + CalcNodeBUSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); +} +void BURegReductionFastPriorityQueue::CalculateSethiUllmanNumbers() { SethiUllmanNumbers.assign(SUnits->size(), 0); for (unsigned i = 0, e = SUnits->size(); i != e; ++i) - CalcNodeSethiUllmanNumber(&(*SUnits)[i]); + CalcNodeBUSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); } -static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) { +/// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled +/// predecessors of the successors of the SUnit SU. Stop when the provided +/// limit is exceeded. +static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU, + unsigned Limit) { unsigned Sum = 0; for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { - SUnit *SuccSU = I->Dep; + const SUnit *SuccSU = I->Dep; for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(), EE = SuccSU->Preds.end(); II != EE; ++II) { SUnit *PredSU = II->Dep; if (!PredSU->isScheduled) - ++Sum; + if (++Sum > Limit) + return Sum; } } - return Sum; } @@ -1727,12 +1830,12 @@ static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) { bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { unsigned LPriority = SPQ->getNodePriority(left); unsigned RPriority = SPQ->getNodePriority(right); - bool LIsTarget = left->Node && left->Node->isTargetOpcode(); - bool RIsTarget = right->Node && right->Node->isTargetOpcode(); + bool LIsTarget = left->Node && left->Node->isMachineOpcode(); + bool RIsTarget = right->Node && right->Node->isMachineOpcode(); bool LIsFloater = LIsTarget && left->NumPreds == 0; bool RIsFloater = RIsTarget && right->NumPreds == 0; - unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0; - unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0; + unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0; + unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0; if (left->NumSuccs == 0 && right->NumSuccs != 0) return false; @@ -1760,59 +1863,18 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { if (left->CycleBound != right->CycleBound) return left->CycleBound > right->CycleBound; - // FIXME: No strict ordering. - return false; -} - -/// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number. -/// Smaller number is the higher priority. -template -unsigned TDRegReductionPriorityQueue:: -CalcNodeSethiUllmanNumber(const SUnit *SU) { - unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum]; - if (SethiUllmanNumber != 0) - return SethiUllmanNumber; - - unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0; - if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) - SethiUllmanNumber = 0xffff; - else if (SU->NumSuccsLeft == 0) - // If SU does not have a use, i.e. it doesn't produce a value that would - // be consumed (e.g. store), then it terminates a chain of computation. - // Give it a small SethiUllman number so it will be scheduled right before - // its predecessors that it doesn't lengthen their live ranges. - SethiUllmanNumber = 0; - else if (SU->NumPredsLeft == 0 && - (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU))) - SethiUllmanNumber = 0xffff; - else { - int Extra = 0; - for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); - I != E; ++I) { - if (I->isCtrl) continue; // ignore chain preds - SUnit *PredSU = I->Dep; - unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU); - if (PredSethiUllman > SethiUllmanNumber) { - SethiUllmanNumber = PredSethiUllman; - Extra = 0; - } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl) - ++Extra; - } - - SethiUllmanNumber += Extra; - } - - return SethiUllmanNumber; + assert(left->NodeQueueId && right->NodeQueueId && + "NodeQueueId cannot be zero"); + return (left->NodeQueueId > right->NodeQueueId); } /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all /// scheduling units. -template -void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() { +void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() { SethiUllmanNumbers.assign(SUnits->size(), 0); for (unsigned i = 0, e = SUnits->size(); i != e; ++i) - CalcNodeSethiUllmanNumber(&(*SUnits)[i]); + CalcNodeTDSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); } //===----------------------------------------------------------------------===// @@ -1821,23 +1883,27 @@ void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() { llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB) { + MachineBasicBlock *BB, + bool Fast) { + if (Fast) + return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, true, + new BURegReductionFastPriorityQueue()); + const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo(); const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo(); - BURegReductionPriorityQueue *priorityQueue = - new BURegReductionPriorityQueue(TII, TRI); + BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI); - ScheduleDAGRRList * scheduleDAG = - new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, priorityQueue); - priorityQueue->setScheduleDAG(scheduleDAG); - return scheduleDAG; + ScheduleDAGRRList *SD = + new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(),true,false, PQ); + PQ->setScheduleDAG(SD); + return SD; } llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB) { - return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, - new TDRegReductionPriorityQueue()); + MachineBasicBlock *BB, + bool Fast) { + return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, Fast, + new TDRegReductionPriorityQueue()); } -