X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FSelectionDAGISel.cpp;h=bf68040c97aebf62e3831692f2d4016728e40d84;hb=bf304c20651b80309af4c0fb3a14c0d73eaa984f;hp=9e7e9d8e424616c1293243fa53eadf54d93c8594;hpb=126d90770bdb17e6925b2fe26de99aa079b7b9b3;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 9e7e9d8e424..bf68040c97a 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -50,7 +50,9 @@ using namespace llvm; static cl::opt -EnableValueProp("enable-value-prop", cl::Hidden, cl::init(false)); +EnableValueProp("enable-value-prop", cl::Hidden); +static cl::opt +EnableLegalizeTypes("enable-legalize-types", cl::Hidden); #ifndef NDEBUG @@ -414,9 +416,9 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, // also creates the initial PHI MachineInstrs, though none of the input // operands are populated. for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { - MachineBasicBlock *MBB = new MachineBasicBlock(BB); + MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB); MBBMap[BB] = MBB; - MF.getBasicBlockList().push_back(MBB); + MF.push_back(MBB); // Create Machine PHI nodes for LLVM PHI nodes, lowering them as // appropriate. @@ -1432,8 +1434,9 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond, // Create TmpBB after CurBB. MachineFunction::iterator BBI = CurBB; - MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); - CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); + MachineFunction &MF = DAG.getMachineFunction(); + MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); + CurBB->getParent()->insert(++BBI, TmpBB); if (Opc == Instruction::Or) { // Codegen X | Y as: @@ -1554,7 +1557,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { // Okay, we decided not to do this, remove any inserted MBB's and clear // SwitchCases. for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) - CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); + CurMBB->getParent()->erase(SwitchCases[i].ThisBB); SwitchCases.clear(); } @@ -1861,8 +1864,8 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { MachineBasicBlock *FallThrough; if (I != E-1) { - FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); - CurMF->getBasicBlockList().insert(BBI, FallThrough); + FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); + CurMF->insert(BBI, FallThrough); } else { // If the last case doesn't match, go to the default block. FallThrough = Default; @@ -1945,8 +1948,8 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, // of the jump table, and jumping to it. Update successor information; // we will either branch to the default case for the switch, or the jump // table. - MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); - CurMF->getBasicBlockList().insert(BBI, JumpTableBB); + MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); + CurMF->insert(BBI, JumpTableBB); CR.CaseBB->addSuccessor(Default); CR.CaseBB->addSuccessor(JumpTableBB); @@ -2083,8 +2086,8 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, (cast(CR.GE)->getSExtValue() + 1LL)) { TrueBB = LHSR.first->BB; } else { - TrueBB = new MachineBasicBlock(LLVMBB); - CurMF->getBasicBlockList().insert(BBI, TrueBB); + TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); + CurMF->insert(BBI, TrueBB); WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); } @@ -2097,8 +2100,8 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, (cast(CR.LT)->getSExtValue() - 1LL)) { FalseBB = RHSR.first->BB; } else { - FalseBB = new MachineBasicBlock(LLVMBB); - CurMF->getBasicBlockList().insert(BBI, FalseBB); + FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); + CurMF->insert(BBI, FalseBB); WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); } @@ -2220,8 +2223,8 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits << ", BB: " << CasesBits[i].BB << "\n"; - MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); - CurMF->getBasicBlockList().insert(BBI, CaseBB); + MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); + CurMF->insert(BBI, CaseBB); BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, CaseBB, CasesBits[i].BB)); @@ -4877,8 +4880,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) { // Mark landing pad. FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); - for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) - SelectBasicBlock(I, MF, FuncInfo); + SelectAllBasicBlocks(Fn, MF, FuncInfo); // Add function live-ins to entry block live-in set. BasicBlock *EntryBB = &Fn.getEntryBlock(); @@ -5002,10 +5004,11 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, // Fix tail call attribute of CALL nodes. for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), - BI = prior(DAG.allnodes_end()); BI != BE; --BI) { + BI = DAG.allnodes_end(); BI != BE; ) { + --BI; if (BI->getOpcode() == ISD::CALL) { SDOperand OpRet(Ret, 0); - SDOperand OpCall(static_cast(BI), 0); + SDOperand OpCall(BI, 0); bool isMarkedTailCall = cast(OpCall.getOperand(3))->getValue() != 0; // If CALL node has tail call attribute set to true and the call is not @@ -5281,10 +5284,11 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) { void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { DOUT << "Lowered selection DAG:\n"; DEBUG(DAG.dump()); + std::string GroupName = "Instruction Selection and Scheduling"; // Run the DAG combiner in pre-legalize mode. if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Combining 1"); + NamedRegionTimer T("DAG Combining 1", GroupName); DAG.Combine(false, *AA); } else { DAG.Combine(false, *AA); @@ -5295,12 +5299,13 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { // Second step, hack on the DAG until it only uses operations and types that // the target supports. -#if 0 // Enable this some day. - DAG.LegalizeTypes(); - // Someday even later, enable a dag combine pass here. -#endif + if (EnableLegalizeTypes) {// Enable this some day. + DAG.LegalizeTypes(); + // TODO: enable a dag combine pass here. + } + if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Legalization"); + NamedRegionTimer T("DAG Legalization", GroupName); DAG.Legalize(); } else { DAG.Legalize(); @@ -5311,7 +5316,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { // Run the DAG combiner in post-legalize mode. if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Combining 2"); + NamedRegionTimer T("DAG Combining 2", GroupName); DAG.Combine(true, *AA); } else { DAG.Combine(true, *AA); @@ -5328,24 +5333,41 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { // Third, instruction select all of the operations to machine code, adding the // code to the MachineBasicBlock. if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Selection"); + NamedRegionTimer T("Instruction Selection", GroupName); InstructionSelect(DAG); } else { InstructionSelect(DAG); } + // Schedule machine code. + ScheduleDAG *Scheduler; + if (TimePassesIsEnabled) { + NamedRegionTimer T("Instruction Scheduling", GroupName); + Scheduler = Schedule(DAG); + } else { + Scheduler = Schedule(DAG); + } + // Emit machine code to BB. This can change 'BB' to the last block being // inserted into. if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Scheduling"); - ScheduleAndEmitDAG(DAG); + NamedRegionTimer T("Instruction Creation", GroupName); + BB = Scheduler->EmitSchedule(); } else { - ScheduleAndEmitDAG(DAG); + BB = Scheduler->EmitSchedule(); + } + + // Free the scheduler state. + if (TimePassesIsEnabled) { + NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); + delete Scheduler; + } else { + delete Scheduler; } // Perform target specific isel post processing. if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Selection Post Processing"); + NamedRegionTimer T("Instruction Selection Post Processing", GroupName); InstructionSelectPostProcessing(DAG); } else { InstructionSelectPostProcessing(DAG); @@ -5355,12 +5377,26 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { DEBUG(BB->dump()); } +void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, + FunctionLoweringInfo &FuncInfo) { + // Define AllNodes here so that memory allocation is reused for + // each basic block. + alist AllNodes; + + for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { + SelectBasicBlock(I, MF, FuncInfo, AllNodes); + AllNodes.clear(); + } +} + void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, - FunctionLoweringInfo &FuncInfo) { + FunctionLoweringInfo &FuncInfo, + alist &AllNodes) { std::vector > PHINodesToUpdate; { SelectionDAG DAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &DAG; // First step, lower LLVM code to some DAG. This DAG may use operations and @@ -5395,7 +5431,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, // Lower header first, if it wasn't already lowered if (!BitTestCases[i].Emitted) { SelectionDAG HSDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &HSDAG; SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); // Set the current basic block to the mbb we wish to insert the code into @@ -5409,7 +5446,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { SelectionDAG BSDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &BSDAG; SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); // Set the current basic block to the mbb we wish to insert the code into @@ -5467,7 +5505,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, // Lower header first, if it wasn't already lowered if (!JTCases[i].first.Emitted) { SelectionDAG HSDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &HSDAG; SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); // Set the current basic block to the mbb we wish to insert the code into @@ -5480,7 +5519,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, } SelectionDAG JSDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &JSDAG; SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); // Set the current basic block to the mbb we wish to insert the code into @@ -5529,7 +5569,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, // additional DAGs necessary. for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { SelectionDAG SDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &SDAG; SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); @@ -5574,10 +5615,10 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, } -//===----------------------------------------------------------------------===// -/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each +/// Schedule - Pick a safe ordering for instructions for each /// target node in the graph. -void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { +/// +ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { if (ViewSchedDAGs) DAG.viewGraph(); RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); @@ -5587,12 +5628,11 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { RegisterScheduler::setDefault(Ctor); } - ScheduleDAG *SL = Ctor(this, &DAG, BB, FastISel); - BB = SL->Run(); - - if (ViewSUnitDAGs) SL->viewGraph(); + ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); + Scheduler->Run(); - delete SL; + if (ViewSUnitDAGs) Scheduler->viewGraph(); + return Scheduler; }