X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FSelectionDAGISel.cpp;h=bf68040c97aebf62e3831692f2d4016728e40d84;hb=bf304c20651b80309af4c0fb3a14c0d73eaa984f;hp=c0b0e0356f33e75ba1c3798a09e40f5854c3967d;hpb=f667480d84a99a34adcac217e1a4c9fb7e2bfae6;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index c0b0e0356f3..bf68040c97a 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -27,7 +27,6 @@ #include "llvm/IntrinsicInst.h" #include "llvm/ParameterAttributes.h" #include "llvm/CodeGen/Collector.h" -#include "llvm/CodeGen/MachineDebugInfoDesc.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -51,7 +50,9 @@ using namespace llvm; static cl::opt -EnableValueProp("enable-value-prop", cl::Hidden, cl::init(false)); +EnableValueProp("enable-value-prop", cl::Hidden); +static cl::opt +EnableLegalizeTypes("enable-legalize-types", cl::Hidden); #ifndef NDEBUG @@ -266,15 +267,16 @@ namespace llvm { /// for the target. ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, - MachineBasicBlock *BB) { + MachineBasicBlock *BB, + bool Fast) { TargetLowering &TLI = IS->getTargetLowering(); if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { - return createTDListDAGScheduler(IS, DAG, BB); + return createTDListDAGScheduler(IS, DAG, BB, Fast); } else { assert(TLI.getSchedulingPreference() == TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); - return createBURRListDAGScheduler(IS, DAG, BB); + return createBURRListDAGScheduler(IS, DAG, BB, Fast); } } @@ -414,9 +416,9 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli, // also creates the initial PHI MachineInstrs, though none of the input // operands are populated. for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) { - MachineBasicBlock *MBB = new MachineBasicBlock(BB); + MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB); MBBMap[BB] = MBB; - MF.getBasicBlockList().push_back(MBB); + MF.push_back(MBB); // Create Machine PHI nodes for LLVM PHI nodes, lowering them as // appropriate. @@ -1157,17 +1159,13 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { if (isa(C) || isa(C)) { SmallVector Constants; - SmallVector ValueVTs; for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); OI != OE; ++OI) { SDNode *Val = getValue(*OI).Val; - for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) { + for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) Constants.push_back(SDOperand(Val, i)); - ValueVTs.push_back(Val->getValueType(i)); - } } - return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(&Constants[0], Constants.size()); } if (const ArrayType *ATy = dyn_cast(C->getType())) { @@ -1178,7 +1176,6 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { return SDOperand(); // empty array MVT EltVT = TLI.getValueType(ATy->getElementType()); SmallVector Constants(NumElts); - SmallVector ValueVTs(NumElts, EltVT); for (unsigned i = 0, e = NumElts; i != e; ++i) { if (isa(C)) Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); @@ -1187,8 +1184,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { else Constants[i] = DAG.getConstant(0, EltVT); } - return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(&Constants[0], Constants.size()); } if (const StructType *STy = dyn_cast(C->getType())) { @@ -1198,10 +1194,8 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { if (NumElts == 0) return SDOperand(); // empty struct SmallVector Constants(NumElts); - SmallVector ValueVTs(NumElts); for (unsigned i = 0, e = NumElts; i != e; ++i) { MVT EltVT = TLI.getValueType(STy->getElementType(i)); - ValueVTs[i] = EltVT; if (isa(C)) Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); else if (EltVT.isFloatingPoint()) @@ -1209,8 +1203,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { else Constants[i] = DAG.getConstant(0, EltVT); } - return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Constants[0], Constants.size()); + return DAG.getMergeValues(&Constants[0], Constants.size()); } const VectorType *VecTy = cast(V->getType()); @@ -1441,8 +1434,9 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond, // Create TmpBB after CurBB. MachineFunction::iterator BBI = CurBB; - MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock()); - CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB); + MachineFunction &MF = DAG.getMachineFunction(); + MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); + CurBB->getParent()->insert(++BBI, TmpBB); if (Opc == Instruction::Or) { // Codegen X | Y as: @@ -1563,7 +1557,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { // Okay, we decided not to do this, remove any inserted MBB's and clear // SwitchCases. for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) - CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB); + CurMBB->getParent()->erase(SwitchCases[i].ThisBB); SwitchCases.clear(); } @@ -1870,8 +1864,8 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { MachineBasicBlock *FallThrough; if (I != E-1) { - FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock()); - CurMF->getBasicBlockList().insert(BBI, FallThrough); + FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); + CurMF->insert(BBI, FallThrough); } else { // If the last case doesn't match, go to the default block. FallThrough = Default; @@ -1954,8 +1948,8 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, // of the jump table, and jumping to it. Update successor information; // we will either branch to the default case for the switch, or the jump // table. - MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB); - CurMF->getBasicBlockList().insert(BBI, JumpTableBB); + MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); + CurMF->insert(BBI, JumpTableBB); CR.CaseBB->addSuccessor(Default); CR.CaseBB->addSuccessor(JumpTableBB); @@ -2092,8 +2086,8 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, (cast(CR.GE)->getSExtValue() + 1LL)) { TrueBB = LHSR.first->BB; } else { - TrueBB = new MachineBasicBlock(LLVMBB); - CurMF->getBasicBlockList().insert(BBI, TrueBB); + TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); + CurMF->insert(BBI, TrueBB); WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); } @@ -2106,8 +2100,8 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, (cast(CR.LT)->getSExtValue() - 1LL)) { FalseBB = RHSR.first->BB; } else { - FalseBB = new MachineBasicBlock(LLVMBB); - CurMF->getBasicBlockList().insert(BBI, FalseBB); + FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); + CurMF->insert(BBI, FalseBB); WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); } @@ -2229,8 +2223,8 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits << ", BB: " << CasesBits[i].BB << "\n"; - MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB); - CurMF->getBasicBlockList().insert(BBI, CaseBB); + MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); + CurMF->insert(BBI, CaseBB); BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask, CaseBB, CasesBits[i].BB)); @@ -3179,9 +3173,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DbgRegionStartInst &RSI = cast(I); if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), - DAG.getConstant(LabelID, MVT::i32), - DAG.getConstant(0, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); } return 0; @@ -3191,9 +3183,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DbgRegionEndInst &REI = cast(I); if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), - DAG.getConstant(LabelID, MVT::i32), - DAG.getConstant(0, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); } return 0; @@ -3210,8 +3200,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { assert(DD && "Not a debug information descriptor"); SubprogramDesc *Subprogram = cast(DD); const CompileUnitDesc *CompileUnit = Subprogram->getFile(); - unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(), - CompileUnit->getFileName()); + unsigned SrcFile = MMI->RecordSource(CompileUnit); // Record the source line but does create a label. It will be emitted // at asm emission time. MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); @@ -3577,9 +3566,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, // Both PendingLoads and PendingExports must be flushed here; // this call might not return. (void)getRoot(); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getControlRoot(), - DAG.getConstant(BeginLabel, MVT::i32), - DAG.getConstant(1, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); } std::pair Result = @@ -3596,9 +3583,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, // Insert a label at the end of the invoke call to mark the try range. This // can be used to detect deletion of the invoke via the MachineModuleInfo. EndLabel = MMI->NextLabelID(); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), - DAG.getConstant(EndLabel, MVT::i32), - DAG.getConstant(1, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); // Inform MachineModuleInfo of range. MMI->addInvoke(LandingPad, BeginLabel, EndLabel); @@ -3779,10 +3764,7 @@ SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG, ValueVT); Part += NumRegs; } - - if (ValueVTs.size() == 1) - return Values[0]; - + return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), &Values[0], ValueVTs.size()); } @@ -4864,12 +4846,6 @@ SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { return SDOperand(); } -SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op, - SelectionDAG &DAG) { - assert(0 && "CustomPromoteOperation not implemented for this target!"); - abort(); - return SDOperand(); -} //===----------------------------------------------------------------------===// // SelectionDAGISel code @@ -4904,8 +4880,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) { // Mark landing pad. FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad(); - for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) - SelectBasicBlock(I, MF, FuncInfo); + SelectAllBasicBlocks(Fn, MF, FuncInfo); // Add function live-ins to entry block live-in set. BasicBlock *EntryBB = &Fn.getEntryBlock(); @@ -4952,13 +4927,7 @@ LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL) { ComputeValueVTs(TLI, AI->getType(), ValueVTs); unsigned NumValues = ValueVTs.size(); if (!AI->use_empty()) { - SmallVector LegalValueVTs(NumValues); - for (unsigned VI = 0; VI != NumValues; ++VI) - LegalValueVTs[VI] = Args[a + VI].getValueType(); - SDL.setValue(AI, - SDL.DAG.getMergeValues(SDL.DAG.getVTList(&LegalValueVTs[0], - NumValues), - &Args[a], NumValues)); + SDL.setValue(AI, SDL.DAG.getMergeValues(&Args[a], NumValues)); // If this argument is live outside of the entry block, insert a copy from // whereever we got it to the vreg that other BB's will reference it as. DenseMap::iterator VMI=FuncInfo.ValueMap.find(AI); @@ -5035,10 +5004,11 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG, // Fix tail call attribute of CALL nodes. for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(), - BI = prior(DAG.allnodes_end()); BI != BE; --BI) { + BI = DAG.allnodes_end(); BI != BE; ) { + --BI; if (BI->getOpcode() == ISD::CALL) { SDOperand OpRet(Ret, 0); - SDOperand OpCall(static_cast(BI), 0); + SDOperand OpCall(BI, 0); bool isMarkedTailCall = cast(OpCall.getOperand(3))->getValue() != 0; // If CALL node has tail call attribute set to true and the call is not @@ -5113,9 +5083,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, // Add a label to mark the beginning of the landing pad. Deletion of the // landing pad can thus be detected via the MachineModuleInfo. unsigned LabelID = MMI->addLandingPad(BB); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), - DAG.getConstant(LabelID, MVT::i32), - DAG.getConstant(1, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID)); // Mark exception register as live in. unsigned Reg = TLI.getExceptionAddressRegister(); @@ -5314,84 +5282,121 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) { } void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { - NamedRegionTimer *RegionTimer = 0; - DOUT << "Lowered selection DAG:\n"; DEBUG(DAG.dump()); + std::string GroupName = "Instruction Selection and Scheduling"; // Run the DAG combiner in pre-legalize mode. - if (TimePassesIsEnabled) - RegionTimer = new NamedRegionTimer("DAG Combining 1"); - DAG.Combine(false, *AA); - if (TimePassesIsEnabled) - delete RegionTimer; + if (TimePassesIsEnabled) { + NamedRegionTimer T("DAG Combining 1", GroupName); + DAG.Combine(false, *AA); + } else { + DAG.Combine(false, *AA); + } DOUT << "Optimized lowered selection DAG:\n"; DEBUG(DAG.dump()); // Second step, hack on the DAG until it only uses operations and types that // the target supports. -#if 0 // Enable this some day. - DAG.LegalizeTypes(); - // Someday even later, enable a dag combine pass here. -#endif - if (TimePassesIsEnabled) - RegionTimer = new NamedRegionTimer("DAG Legalization"); - DAG.Legalize(); - if (TimePassesIsEnabled) - delete RegionTimer; + if (EnableLegalizeTypes) {// Enable this some day. + DAG.LegalizeTypes(); + // TODO: enable a dag combine pass here. + } + + if (TimePassesIsEnabled) { + NamedRegionTimer T("DAG Legalization", GroupName); + DAG.Legalize(); + } else { + DAG.Legalize(); + } DOUT << "Legalized selection DAG:\n"; DEBUG(DAG.dump()); // Run the DAG combiner in post-legalize mode. - if (TimePassesIsEnabled) - RegionTimer = new NamedRegionTimer("DAG Combining 2"); - DAG.Combine(true, *AA); - if (TimePassesIsEnabled) - delete RegionTimer; + if (TimePassesIsEnabled) { + NamedRegionTimer T("DAG Combining 2", GroupName); + DAG.Combine(true, *AA); + } else { + DAG.Combine(true, *AA); + } DOUT << "Optimized legalized selection DAG:\n"; DEBUG(DAG.dump()); if (ViewISelDAGs) DAG.viewGraph(); - if (EnableValueProp) // FIXME: Only do this if !fast. + if (!FastISel && EnableValueProp) ComputeLiveOutVRegInfo(DAG); // Third, instruction select all of the operations to machine code, adding the // code to the MachineBasicBlock. - if (TimePassesIsEnabled) - RegionTimer = new NamedRegionTimer("Instruction Selection"); - InstructionSelect(DAG); - if (TimePassesIsEnabled) - delete RegionTimer; + if (TimePassesIsEnabled) { + NamedRegionTimer T("Instruction Selection", GroupName); + InstructionSelect(DAG); + } else { + InstructionSelect(DAG); + } + + // Schedule machine code. + ScheduleDAG *Scheduler; + if (TimePassesIsEnabled) { + NamedRegionTimer T("Instruction Scheduling", GroupName); + Scheduler = Schedule(DAG); + } else { + Scheduler = Schedule(DAG); + } // Emit machine code to BB. This can change 'BB' to the last block being // inserted into. - if (TimePassesIsEnabled) - RegionTimer = new NamedRegionTimer("Instruction Scheduling"); - ScheduleAndEmitDAG(DAG); - if (TimePassesIsEnabled) - delete RegionTimer; + if (TimePassesIsEnabled) { + NamedRegionTimer T("Instruction Creation", GroupName); + BB = Scheduler->EmitSchedule(); + } else { + BB = Scheduler->EmitSchedule(); + } + + // Free the scheduler state. + if (TimePassesIsEnabled) { + NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); + delete Scheduler; + } else { + delete Scheduler; + } // Perform target specific isel post processing. - if (TimePassesIsEnabled) - RegionTimer = new NamedRegionTimer("Instruction Selection Post Processing"); - InstructionSelectPostProcessing(DAG); - if (TimePassesIsEnabled) - delete RegionTimer; + if (TimePassesIsEnabled) { + NamedRegionTimer T("Instruction Selection Post Processing", GroupName); + InstructionSelectPostProcessing(DAG); + } else { + InstructionSelectPostProcessing(DAG); + } DOUT << "Selected machine code:\n"; DEBUG(BB->dump()); } +void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, + FunctionLoweringInfo &FuncInfo) { + // Define AllNodes here so that memory allocation is reused for + // each basic block. + alist AllNodes; + + for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { + SelectBasicBlock(I, MF, FuncInfo, AllNodes); + AllNodes.clear(); + } +} + void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, - FunctionLoweringInfo &FuncInfo) { + FunctionLoweringInfo &FuncInfo, + alist &AllNodes) { std::vector > PHINodesToUpdate; { SelectionDAG DAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &DAG; // First step, lower LLVM code to some DAG. This DAG may use operations and @@ -5426,7 +5431,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, // Lower header first, if it wasn't already lowered if (!BitTestCases[i].Emitted) { SelectionDAG HSDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &HSDAG; SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); // Set the current basic block to the mbb we wish to insert the code into @@ -5440,7 +5446,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) { SelectionDAG BSDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &BSDAG; SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI); // Set the current basic block to the mbb we wish to insert the code into @@ -5498,7 +5505,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, // Lower header first, if it wasn't already lowered if (!JTCases[i].first.Emitted) { SelectionDAG HSDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &HSDAG; SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI); // Set the current basic block to the mbb we wish to insert the code into @@ -5511,7 +5519,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, } SelectionDAG JSDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &JSDAG; SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI); // Set the current basic block to the mbb we wish to insert the code into @@ -5560,7 +5569,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, // additional DAGs necessary. for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) { SelectionDAG SDAG(TLI, MF, FuncInfo, - getAnalysisToUpdate()); + getAnalysisToUpdate(), + AllNodes); CurDAG = &SDAG; SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI); @@ -5605,10 +5615,10 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, } -//===----------------------------------------------------------------------===// -/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each +/// Schedule - Pick a safe ordering for instructions for each /// target node in the graph. -void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { +/// +ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { if (ViewSchedDAGs) DAG.viewGraph(); RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); @@ -5618,12 +5628,11 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) { RegisterScheduler::setDefault(Ctor); } - ScheduleDAG *SL = Ctor(this, &DAG, BB); - BB = SL->Run(); - - if (ViewSUnitDAGs) SL->viewGraph(); + ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); + Scheduler->Run(); - delete SL; + if (ViewSUnitDAGs) Scheduler->viewGraph(); + return Scheduler; }