X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FTargetLowering.cpp;h=1e7e847b8adba831b856087144f6a0fb927bf946;hb=b3bc6352defdf1a5c6b1b0770d0c4d603f6524a8;hp=4a2a0c039021ba3963ffee3ca0b99c803187f5f7;hpb=dddc6291fb5274282a20d5923b50535d456d34a4;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 4a2a0c03902..1e7e847b8ad 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -83,6 +83,26 @@ static void InitLibcallNames(const char **Names) { Names[RTLIB::SQRT_F64] = "sqrt"; Names[RTLIB::SQRT_F80] = "sqrtl"; Names[RTLIB::SQRT_PPCF128] = "sqrtl"; + Names[RTLIB::LOG_F32] = "logf"; + Names[RTLIB::LOG_F64] = "log"; + Names[RTLIB::LOG_F80] = "logl"; + Names[RTLIB::LOG_PPCF128] = "logl"; + Names[RTLIB::LOG2_F32] = "log2f"; + Names[RTLIB::LOG2_F64] = "log2"; + Names[RTLIB::LOG2_F80] = "log2l"; + Names[RTLIB::LOG2_PPCF128] = "log2l"; + Names[RTLIB::LOG10_F32] = "log10f"; + Names[RTLIB::LOG10_F64] = "log10"; + Names[RTLIB::LOG10_F80] = "log10l"; + Names[RTLIB::LOG10_PPCF128] = "log10l"; + Names[RTLIB::EXP_F32] = "expf"; + Names[RTLIB::EXP_F64] = "exp"; + Names[RTLIB::EXP_F80] = "expl"; + Names[RTLIB::EXP_PPCF128] = "expl"; + Names[RTLIB::EXP2_F32] = "exp2f"; + Names[RTLIB::EXP2_F64] = "exp2"; + Names[RTLIB::EXP2_F80] = "exp2l"; + Names[RTLIB::EXP2_PPCF128] = "exp2l"; Names[RTLIB::SIN_F32] = "sinf"; Names[RTLIB::SIN_F64] = "sin"; Names[RTLIB::SIN_F80] = "sinl"; @@ -95,8 +115,32 @@ static void InitLibcallNames(const char **Names) { Names[RTLIB::POW_F64] = "pow"; Names[RTLIB::POW_F80] = "powl"; Names[RTLIB::POW_PPCF128] = "powl"; + Names[RTLIB::CEIL_F32] = "ceilf"; + Names[RTLIB::CEIL_F64] = "ceil"; + Names[RTLIB::CEIL_F80] = "ceill"; + Names[RTLIB::CEIL_PPCF128] = "ceill"; + Names[RTLIB::TRUNC_F32] = "truncf"; + Names[RTLIB::TRUNC_F64] = "trunc"; + Names[RTLIB::TRUNC_F80] = "truncl"; + Names[RTLIB::TRUNC_PPCF128] = "truncl"; + Names[RTLIB::RINT_F32] = "rintf"; + Names[RTLIB::RINT_F64] = "rint"; + Names[RTLIB::RINT_F80] = "rintl"; + Names[RTLIB::RINT_PPCF128] = "rintl"; + Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; + Names[RTLIB::NEARBYINT_F64] = "nearbyint"; + Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; + Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; + Names[RTLIB::FLOOR_F32] = "floorf"; + Names[RTLIB::FLOOR_F64] = "floor"; + Names[RTLIB::FLOOR_F80] = "floorl"; + Names[RTLIB::FLOOR_PPCF128] = "floorl"; Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; + Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; + Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; + Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; + Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; @@ -123,6 +167,8 @@ static void InitLibcallNames(const char **Names) { Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; + Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; + Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; @@ -133,8 +179,16 @@ static void InitLibcallNames(const char **Names) { Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; + Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; + Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; + Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; + Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; + Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; + Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; + Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; + Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; Names[RTLIB::OEQ_F32] = "__eqsf2"; Names[RTLIB::OEQ_F64] = "__eqdf2"; Names[RTLIB::UNE_F32] = "__nesf2"; @@ -153,6 +207,173 @@ static void InitLibcallNames(const char **Names) { Names[RTLIB::O_F64] = "__unorddf2"; } +/// getFPEXT - Return the FPEXT_*_* value for the given types, or +/// UNKNOWN_LIBCALL if there is none. +RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { + if (OpVT == MVT::f32) { + if (RetVT == MVT::f64) + return FPEXT_F32_F64; + } + return UNKNOWN_LIBCALL; +} + +/// getFPROUND - Return the FPROUND_*_* value for the given types, or +/// UNKNOWN_LIBCALL if there is none. +RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { + if (RetVT == MVT::f32) { + if (OpVT == MVT::f64) + return FPROUND_F64_F32; + if (OpVT == MVT::f80) + return FPROUND_F80_F32; + if (OpVT == MVT::ppcf128) + return FPROUND_PPCF128_F32; + } else if (RetVT == MVT::f64) { + if (OpVT == MVT::f80) + return FPROUND_F80_F64; + if (OpVT == MVT::ppcf128) + return FPROUND_PPCF128_F64; + } + return UNKNOWN_LIBCALL; +} + +/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or +/// UNKNOWN_LIBCALL if there is none. +RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { + if (OpVT == MVT::f32) { + if (RetVT == MVT::i32) + return FPTOSINT_F32_I32; + if (RetVT == MVT::i64) + return FPTOSINT_F32_I64; + if (RetVT == MVT::i128) + return FPTOSINT_F32_I128; + } else if (OpVT == MVT::f64) { + if (RetVT == MVT::i32) + return FPTOSINT_F64_I32; + if (RetVT == MVT::i64) + return FPTOSINT_F64_I64; + if (RetVT == MVT::i128) + return FPTOSINT_F64_I128; + } else if (OpVT == MVT::f80) { + if (RetVT == MVT::i32) + return FPTOSINT_F80_I32; + if (RetVT == MVT::i64) + return FPTOSINT_F80_I64; + if (RetVT == MVT::i128) + return FPTOSINT_F80_I128; + } else if (OpVT == MVT::ppcf128) { + if (RetVT == MVT::i32) + return FPTOSINT_PPCF128_I32; + if (RetVT == MVT::i64) + return FPTOSINT_PPCF128_I64; + if (RetVT == MVT::i128) + return FPTOSINT_PPCF128_I128; + } + return UNKNOWN_LIBCALL; +} + +/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or +/// UNKNOWN_LIBCALL if there is none. +RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { + if (OpVT == MVT::f32) { + if (RetVT == MVT::i32) + return FPTOUINT_F32_I32; + if (RetVT == MVT::i64) + return FPTOUINT_F32_I64; + if (RetVT == MVT::i128) + return FPTOUINT_F32_I128; + } else if (OpVT == MVT::f64) { + if (RetVT == MVT::i32) + return FPTOUINT_F64_I32; + if (RetVT == MVT::i64) + return FPTOUINT_F64_I64; + if (RetVT == MVT::i128) + return FPTOUINT_F64_I128; + } else if (OpVT == MVT::f80) { + if (RetVT == MVT::i32) + return FPTOUINT_F80_I32; + if (RetVT == MVT::i64) + return FPTOUINT_F80_I64; + if (RetVT == MVT::i128) + return FPTOUINT_F80_I128; + } else if (OpVT == MVT::ppcf128) { + if (RetVT == MVT::i32) + return FPTOUINT_PPCF128_I32; + if (RetVT == MVT::i64) + return FPTOUINT_PPCF128_I64; + if (RetVT == MVT::i128) + return FPTOUINT_PPCF128_I128; + } + return UNKNOWN_LIBCALL; +} + +/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or +/// UNKNOWN_LIBCALL if there is none. +RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { + if (OpVT == MVT::i32) { + if (RetVT == MVT::f32) + return SINTTOFP_I32_F32; + else if (RetVT == MVT::f64) + return SINTTOFP_I32_F64; + else if (RetVT == MVT::f80) + return SINTTOFP_I32_F80; + else if (RetVT == MVT::ppcf128) + return SINTTOFP_I32_PPCF128; + } else if (OpVT == MVT::i64) { + if (RetVT == MVT::f32) + return SINTTOFP_I64_F32; + else if (RetVT == MVT::f64) + return SINTTOFP_I64_F64; + else if (RetVT == MVT::f80) + return SINTTOFP_I64_F80; + else if (RetVT == MVT::ppcf128) + return SINTTOFP_I64_PPCF128; + } else if (OpVT == MVT::i128) { + if (RetVT == MVT::f32) + return SINTTOFP_I128_F32; + else if (RetVT == MVT::f64) + return SINTTOFP_I128_F64; + else if (RetVT == MVT::f80) + return SINTTOFP_I128_F80; + else if (RetVT == MVT::ppcf128) + return SINTTOFP_I128_PPCF128; + } + return UNKNOWN_LIBCALL; +} + +/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or +/// UNKNOWN_LIBCALL if there is none. +RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { + if (OpVT == MVT::i32) { + if (RetVT == MVT::f32) + return UINTTOFP_I32_F32; + else if (RetVT == MVT::f64) + return UINTTOFP_I32_F64; + else if (RetVT == MVT::f80) + return UINTTOFP_I32_F80; + else if (RetVT == MVT::ppcf128) + return UINTTOFP_I32_PPCF128; + } else if (OpVT == MVT::i64) { + if (RetVT == MVT::f32) + return UINTTOFP_I64_F32; + else if (RetVT == MVT::f64) + return UINTTOFP_I64_F64; + else if (RetVT == MVT::f80) + return UINTTOFP_I64_F80; + else if (RetVT == MVT::ppcf128) + return UINTTOFP_I64_PPCF128; + } else if (OpVT == MVT::i128) { + if (RetVT == MVT::f32) + return UINTTOFP_I128_F32; + else if (RetVT == MVT::f64) + return UINTTOFP_I128_F64; + else if (RetVT == MVT::f80) + return UINTTOFP_I128_F80; + else if (RetVT == MVT::ppcf128) + return UINTTOFP_I128_PPCF128; + } + return UNKNOWN_LIBCALL; +} + /// InitCmpLibcallCCs - Set default comparison libcall CC. /// static void InitCmpLibcallCCs(ISD::CondCode *CCs) { @@ -181,10 +402,11 @@ TargetLowering::TargetLowering(TargetMachine &tm) "Fixed size array in TargetLowering is not large enough!"); // All operations default to being supported. memset(OpActions, 0, sizeof(OpActions)); - memset(LoadXActions, 0, sizeof(LoadXActions)); + memset(LoadExtActions, 0, sizeof(LoadExtActions)); memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); memset(ConvertActions, 0, sizeof(ConvertActions)); + memset(CondCodeActions, 0, sizeof(CondCodeActions)); // Set default actions for various operations. for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { @@ -209,6 +431,18 @@ TargetLowering::TargetLowering(TargetMachine &tm) setOperationAction(ISD::ConstantFP, MVT::f64, Expand); setOperationAction(ISD::ConstantFP, MVT::f80, Expand); + // These library functions default to expand. + setOperationAction(ISD::FLOG , MVT::f64, Expand); + setOperationAction(ISD::FLOG2, MVT::f64, Expand); + setOperationAction(ISD::FLOG10,MVT::f64, Expand); + setOperationAction(ISD::FEXP , MVT::f64, Expand); + setOperationAction(ISD::FEXP2, MVT::f64, Expand); + setOperationAction(ISD::FLOG , MVT::f32, Expand); + setOperationAction(ISD::FLOG2, MVT::f32, Expand); + setOperationAction(ISD::FLOG10,MVT::f32, Expand); + setOperationAction(ISD::FEXP , MVT::f32, Expand); + setOperationAction(ISD::FEXP2, MVT::f32, Expand); + // Default ISD::TRAP to expand (which turns it into abort). setOperationAction(ISD::TRAP, MVT::Other, Expand); @@ -240,7 +474,8 @@ TargetLowering::TargetLowering(TargetMachine &tm) InitCmpLibcallCCs(CmpLibcallCCs); // Tell Legalize whether the assembler supports DEBUG_LOC. - if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile()) + const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); + if (!TASM || !TASM->hasDotLocAndDotFile()) setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); } @@ -348,7 +583,7 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { } -MVT TargetLowering::getSetCCResultType(const SDOperand &) const { +MVT TargetLowering::getSetCCResultType(const SDValue &) const { return getValueType(TD->getIntPtrType()); } @@ -414,13 +649,30 @@ unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { return TD->getCallFrameTypeAlignment(Ty); } -SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, - SelectionDAG &DAG) const { +SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, + SelectionDAG &DAG) const { if (usesGlobalOffsetTable()) return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy()); return Table; } +bool +TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { + // Assume that everything is safe in static mode. + if (getTargetMachine().getRelocationModel() == Reloc::Static) + return true; + + // In dynamic-no-pic mode, assume that known defined values are safe. + if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && + GA && + !GA->getGlobal()->isDeclaration() && + !GA->getGlobal()->mayBeOverridden()) + return true; + + // Otherwise assume nothing is safe. + return false; +} + //===----------------------------------------------------------------------===// // Optimization Methods //===----------------------------------------------------------------------===// @@ -429,7 +681,7 @@ SDOperand TargetLowering::getPICJumpTableRelocBase(SDOperand Table, /// specified instruction is a constant integer. If so, check to see if there /// are any bits set in the constant that are not demanded. If so, shrink the /// constant and return true. -bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, +bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, const APInt &Demanded) { // FIXME: ISD::SELECT, ISD::SELECT_CC switch(Op.getOpcode()) { @@ -440,7 +692,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, if (ConstantSDNode *C = dyn_cast(Op.getOperand(1))) if (C->getAPIntValue().intersects(~Demanded)) { MVT VT = Op.getValueType(); - SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), + SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), DAG.getConstant(Demanded & C->getAPIntValue(), VT)); @@ -458,7 +710,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op, /// analyze the expression and return a mask of KnownOne and KnownZero bits for /// the expression (used to simplify the caller). The KnownZero/One bits may /// only be accurate for those bits in the DemandedMask. -bool TargetLowering::SimplifyDemandedBits(SDOperand Op, +bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, @@ -473,7 +725,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, KnownZero = KnownOne = APInt(BitWidth, 0); // Other users may use these bits. - if (!Op.Val->hasOneUse()) { + if (!Op.getNode()->hasOneUse()) { if (Depth != 0) { // If not at the root, Just compute the KnownZero/KnownOne bits to // simplify things downstream. @@ -612,7 +864,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known if ((KnownOne & KnownOne2) == KnownOne) { MVT VT = Op.getValueType(); - SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); + SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0), ANDC)); } @@ -627,7 +879,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, if (Expanded.isAllOnesValue()) { if (Expanded != C->getAPIntValue()) { MVT VT = Op.getValueType(); - SDOperand New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), + SDValue New = TLO.DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0), TLO.DAG.getConstant(Expanded, VT)); return TLO.CombineTo(Op, New); } @@ -679,8 +931,8 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, break; case ISD::SHL: if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { - unsigned ShAmt = SA->getValue(); - SDOperand InOp = Op.getOperand(0); + unsigned ShAmt = SA->getZExtValue(); + SDValue InOp = Op.getOperand(0); // If the shift count is an invalid immediate, don't do anything. if (ShAmt >= BitWidth) @@ -692,7 +944,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, if (InOp.getOpcode() == ISD::SRL && isa(InOp.getOperand(1))) { if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { - unsigned C1 = cast(InOp.getOperand(1))->getValue(); + unsigned C1= cast(InOp.getOperand(1))->getZExtValue(); unsigned Opc = ISD::SHL; int Diff = ShAmt-C1; if (Diff < 0) { @@ -700,7 +952,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, Opc = ISD::SRL; } - SDOperand NewSA = + SDValue NewSA = TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); MVT VT = Op.getValueType(); return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, @@ -711,18 +963,18 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), KnownZero, KnownOne, TLO, Depth+1)) return true; - KnownZero <<= SA->getValue(); - KnownOne <<= SA->getValue(); + KnownZero <<= SA->getZExtValue(); + KnownOne <<= SA->getZExtValue(); // low bits known zero. - KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getValue()); + KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); } break; case ISD::SRL: if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { MVT VT = Op.getValueType(); - unsigned ShAmt = SA->getValue(); + unsigned ShAmt = SA->getZExtValue(); unsigned VTSize = VT.getSizeInBits(); - SDOperand InOp = Op.getOperand(0); + SDValue InOp = Op.getOperand(0); // If the shift count is an invalid immediate, don't do anything. if (ShAmt >= BitWidth) @@ -734,7 +986,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, if (InOp.getOpcode() == ISD::SHL && isa(InOp.getOperand(1))) { if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { - unsigned C1 = cast(InOp.getOperand(1))->getValue(); + unsigned C1= cast(InOp.getOperand(1))->getZExtValue(); unsigned Opc = ISD::SRL; int Diff = ShAmt-C1; if (Diff < 0) { @@ -742,7 +994,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, Opc = ISD::SHL; } - SDOperand NewSA = + SDValue NewSA = TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT, InOp.getOperand(0), NewSA)); @@ -764,7 +1016,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, case ISD::SRA: if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) { MVT VT = Op.getValueType(); - unsigned ShAmt = SA->getValue(); + unsigned ShAmt = SA->getZExtValue(); // If the shift count is an invalid immediate, don't do anything. if (ShAmt >= BitWidth) @@ -930,8 +1182,8 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, // If the input is only used by this truncate, see if we can shrink it based // on the known demanded bits. - if (Op.getOperand(0).Val->hasOneUse()) { - SDOperand In = Op.getOperand(0); + if (Op.getOperand(0).getNode()->hasOneUse()) { + SDValue In = Op.getOperand(0); unsigned InBitWidth = In.getValueSizeInBits(); switch (In.getOpcode()) { default: break; @@ -941,13 +1193,13 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, if (ConstantSDNode *ShAmt = dyn_cast(In.getOperand(1))){ APInt HighBits = APInt::getHighBitsSet(InBitWidth, InBitWidth - BitWidth); - HighBits = HighBits.lshr(ShAmt->getValue()); + HighBits = HighBits.lshr(ShAmt->getZExtValue()); HighBits.trunc(BitWidth); - if (ShAmt->getValue() < BitWidth && !(HighBits & NewMask)) { + if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { // None of the shifted in bits are needed. Add a truncate of the // shift input, then shift it. - SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, + SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, Op.getValueType(), In.getOperand(0)); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(), @@ -984,10 +1236,10 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { // Make a FGETSIGN + SHL to move the sign bit into the appropriate // place. We expect the SHL to be eliminated by other optimizations. - SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), + SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), Op.getOperand(0)); unsigned ShVal = Op.getValueType().getSizeInBits()-1; - SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); + SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), Sign, ShAmt)); } @@ -1011,7 +1263,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, /// computeMaskedBitsForTargetNode - Determine which of the bits specified /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. -void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, +void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, APInt &KnownZero, APInt &KnownOne, @@ -1029,7 +1281,7 @@ void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, /// ComputeNumSignBitsForTargetNode - This method can be implemented by /// targets that want to expose additional information about sign bits to the /// DAG Combiner. -unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, +unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, unsigned Depth) const { assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || @@ -1042,9 +1294,9 @@ unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op, /// SimplifySetCC - Try to simplify a setcc built with the specified operands -/// and cc. If it is unable to simplify it, return a null SDOperand. -SDOperand -TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, +/// and cc. If it is unable to simplify it, return a null SDValue. +SDValue +TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; @@ -1058,9 +1310,9 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, case ISD::SETTRUE2: return DAG.getConstant(1, VT); } - if (ConstantSDNode *N1C = dyn_cast(N1.Val)) { + if (ConstantSDNode *N1C = dyn_cast(N1.getNode())) { const APInt &C1 = N1C->getAPIntValue(); - if (isa(N0.Val)) { + if (isa(N0.getNode())) { return DAG.FoldSetCC(VT, N0, N1, Cond); } else { // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an @@ -1069,7 +1321,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && N0.getOperand(0).getOpcode() == ISD::CTLZ && N0.getOperand(1).getOpcode() == ISD::Constant) { - unsigned ShAmt = cast(N0.getOperand(1))->getValue(); + unsigned ShAmt = cast(N0.getOperand(1))->getZExtValue(); if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { if ((C1 == 0) == (Cond == ISD::SETEQ)) { @@ -1081,7 +1333,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, // (srl (ctlz x), 5) == 1 -> X == 0 Cond = ISD::SETEQ; } - SDOperand Zero = DAG.getConstant(0, N0.getValueType()); + SDValue Zero = DAG.getConstant(0, N0.getValueType()); return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0), Zero, Cond); } @@ -1145,7 +1397,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) return DAG.getConstant(Cond == ISD::SETNE, VT); - SDOperand ZextOp; + SDValue ZextOp; MVT Op0Ty = N0.getOperand(0).getValueType(); if (Op0Ty == ExtSrcTy) { ZextOp = N0.getOperand(0); @@ -1155,7 +1407,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, DAG.getConstant(Imm, Op0Ty)); } if (!DCI.isCalledByLegalizer()) - DCI.AddToWorklist(ZextOp.Val); + DCI.AddToWorklist(ZextOp.getNode()); // Otherwise, make this a use of a zext. return DAG.getSetCC(VT, ZextOp, DAG.getConstant(C1 & APInt::getLowBitsSet( @@ -1168,7 +1420,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC if (N0.getOpcode() == ISD::SETCC) { - bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1); + bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1); if (TrueWhenTrue) return N0; @@ -1192,7 +1444,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, APInt::getHighBitsSet(BitWidth, BitWidth-1))) { // Okay, get the un-inverted input value. - SDOperand Val; + SDValue Val; if (N0.getOpcode() == ISD::XOR) Val = N0.getOperand(0); else { @@ -1277,12 +1529,12 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, dyn_cast(N0.getOperand(1))) { if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 // Perform the xform if the AND RHS is a single bit. - if (isPowerOf2_64(AndRHS->getValue())) { + if (isPowerOf2_64(AndRHS->getZExtValue())) { return DAG.getNode(ISD::SRL, VT, N0, - DAG.getConstant(Log2_64(AndRHS->getValue()), + DAG.getConstant(Log2_64(AndRHS->getZExtValue()), getShiftAmountTy())); } - } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { + } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) { // (X & 8) == 8 --> (X & 8) >> 3 // Perform the xform if C1 is a single bit. if (C1.isPowerOf2()) { @@ -1292,16 +1544,16 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, } } } - } else if (isa(N0.Val)) { + } else if (isa(N0.getNode())) { // Ensure that the constant occurs on the RHS. return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); } - if (isa(N0.Val)) { + if (isa(N0.getNode())) { // Constant fold or commute setcc. - SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond); - if (O.Val) return O; - } else if (ConstantFPSDNode *CFP = dyn_cast(N1.Val)) { + SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond); + if (O.getNode()) return O; + } else if (ConstantFPSDNode *CFP = dyn_cast(N1.getNode())) { // If the RHS of an FP comparison is a constant, simplify it away in // some cases. if (CFP->getValueAPF().isNaN()) { @@ -1363,9 +1615,10 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, if (ConstantSDNode *RHSC = dyn_cast(N1)) { if (ConstantSDNode *LHSR = dyn_cast(N0.getOperand(1))) { // Turn (X+C1) == C2 --> X == C2-C1 - if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { + if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { return DAG.getSetCC(VT, N0.getOperand(0), - DAG.getConstant(RHSC->getValue()-LHSR->getValue(), + DAG.getConstant(RHSC->getAPIntValue()- + LHSR->getAPIntValue(), N0.getValueType()), Cond); } @@ -1384,7 +1637,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, // Turn (C1-X) == C2 --> X == C1-C2 if (ConstantSDNode *SUBC = dyn_cast(N0.getOperand(0))) { - if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { + if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { return DAG.getSetCC(VT, N0.getOperand(1), DAG.getConstant(SUBC->getAPIntValue() - @@ -1403,14 +1656,14 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, if (DAG.isCommutativeBinOp(N0.getOpcode())) return DAG.getSetCC(VT, N0.getOperand(0), DAG.getConstant(0, N0.getValueType()), Cond); - else if (N0.Val->hasOneUse()) { + else if (N0.getNode()->hasOneUse()) { assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); // (Z-X) == X --> Z == X<<1 - SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), + SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N1, DAG.getConstant(1, getShiftAmountTy())); if (!DCI.isCalledByLegalizer()) - DCI.AddToWorklist(SH.Val); + DCI.AddToWorklist(SH.getNode()); return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); } } @@ -1426,13 +1679,13 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, if (DAG.isCommutativeBinOp(N1.getOpcode())) { return DAG.getSetCC(VT, N1.getOperand(0), DAG.getConstant(0, N1.getValueType()), Cond); - } else if (N1.Val->hasOneUse()) { + } else if (N1.getNode()->hasOneUse()) { assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); // X == (Z-X) --> X<<1 == Z - SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, + SDValue SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, DAG.getConstant(1, getShiftAmountTy())); if (!DCI.isCalledByLegalizer()) - DCI.AddToWorklist(SH.Val); + DCI.AddToWorklist(SH.getNode()); return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); } } @@ -1440,7 +1693,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, } // Fold away ALL boolean setcc's. - SDOperand Temp; + SDValue Temp; if (N0.getValueType() == MVT::i1 && foldBooleans) { switch (Cond) { default: assert(0 && "Unknown integer setcc!"); @@ -1448,7 +1701,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); if (!DCI.isCalledByLegalizer()) - DCI.AddToWorklist(Temp.Val); + DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETNE: // X != Y --> (X^Y) N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); @@ -1458,21 +1711,21 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) - DCI.AddToWorklist(Temp.Val); + DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETLT: // X X == 1 & Y == 0 --> Y^1 & X case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); if (!DCI.isCalledByLegalizer()) - DCI.AddToWorklist(Temp.Val); + DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) - DCI.AddToWorklist(Temp.Val); + DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X @@ -1482,7 +1735,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, } if (VT != MVT::i1) { if (!DCI.isCalledByLegalizer()) - DCI.AddToWorklist(N0.Val); + DCI.AddToWorklist(N0.getNode()); // FIXME: If running after legalize, we probably can't do this. N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); } @@ -1490,7 +1743,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, } // Could not fold it. - return SDOperand(); + return SDValue(); } /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the @@ -1505,18 +1758,18 @@ bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, } if (N->getOpcode() == ISD::ADD) { - SDOperand N1 = N->getOperand(0); - SDOperand N2 = N->getOperand(1); - if (isGAPlusOffset(N1.Val, GA, Offset)) { + SDValue N1 = N->getOperand(0); + SDValue N2 = N->getOperand(1); + if (isGAPlusOffset(N1.getNode(), GA, Offset)) { ConstantSDNode *V = dyn_cast(N2); if (V) { - Offset += V->getSignExtended(); + Offset += V->getSExtValue(); return true; } - } else if (isGAPlusOffset(N2.Val, GA, Offset)) { + } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { ConstantSDNode *V = dyn_cast(N1); if (V) { - Offset += V->getSignExtended(); + Offset += V->getSExtValue(); return true; } } @@ -1531,14 +1784,14 @@ bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA, bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist, const MachineFrameInfo *MFI) const { - if (LD->getOperand(0).Val != Base->getOperand(0).Val) + if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode()) return false; MVT VT = LD->getValueType(0); if (VT.getSizeInBits() / 8 != Bytes) return false; - SDOperand Loc = LD->getOperand(1); - SDOperand BaseLoc = Base->getOperand(1); + SDValue Loc = LD->getOperand(1); + SDValue BaseLoc = Base->getOperand(1); if (Loc.getOpcode() == ISD::FrameIndex) { if (BaseLoc.getOpcode() != ISD::FrameIndex) return false; @@ -1554,18 +1807,18 @@ bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base, GlobalValue *GV2 = NULL; int64_t Offset1 = 0; int64_t Offset2 = 0; - bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1); - bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2); + bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1); + bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); if (isGA1 && isGA2 && GV1 == GV2) return Offset1 == (Offset2 + Dist*Bytes); return false; } -SDOperand TargetLowering:: +SDValue TargetLowering:: PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { // Default implementation: no optimization. - return SDOperand(); + return SDValue(); } //===----------------------------------------------------------------------===// @@ -1619,9 +1872,10 @@ const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. -void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, +void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, - std::vector &Ops, + bool hasMemory, + std::vector &Ops, SelectionDAG &DAG) const { switch (ConstraintLetter) { default: break; @@ -1657,7 +1911,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, if (GA) { // Either &GV or &GV+C if (ConstraintLetter != 'n') { int64_t Offs = GA->getOffset(); - if (C) Offs += C->getValue(); + if (C) Offs += C->getZExtValue(); Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getValueType(), Offs)); return; @@ -1666,7 +1920,8 @@ void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op, if (C) { // just C, no GV. // Simple constants are not allowed for 's'. if (ConstraintLetter != 's') { - Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType())); + Ops.push_back(DAG.getTargetConstant(C->getAPIntValue(), + Op.getValueType())); return; } } @@ -1724,6 +1979,21 @@ getRegForInlineAsmConstraint(const std::string &Constraint, //===----------------------------------------------------------------------===// // Constraint Selection. +/// isMatchingInputConstraint - Return true of this is an input operand that is +/// a matching constraint like "4". +bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { + assert(!ConstraintCode.empty() && "No known constraint!"); + return isdigit(ConstraintCode[0]); +} + +/// getMatchedOperand - If this is an input matching constraint, this method +/// returns the output operand it matches. +unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { + assert(!ConstraintCode.empty() && "No known constraint!"); + return atoi(ConstraintCode.c_str()); +} + + /// getConstraintGenerality - Return an integer indicating how general CT /// is. static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { @@ -1762,8 +2032,8 @@ static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { /// 'm' over 'r', for example. /// static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, - const TargetLowering &TLI, - SDOperand Op, SelectionDAG *DAG) { + bool hasMemory, const TargetLowering &TLI, + SDValue Op, SelectionDAG *DAG) { assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); unsigned BestIdx = 0; TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; @@ -1778,11 +2048,11 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, // For example, on X86 we might have an 'rI' constraint. If the operand // is an integer in the range [0..31] we want to use I (saving a load // of a register), otherwise we must use 'r'. - if (CType == TargetLowering::C_Other && Op.Val) { + if (CType == TargetLowering::C_Other && Op.getNode()) { assert(OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint"); - std::vector ResultOps; - TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], + std::vector ResultOps; + TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory, ResultOps, *DAG); if (!ResultOps.empty()) { BestType = CType; @@ -1808,7 +2078,8 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, /// type to use for the specific AsmOperandInfo, setting /// OpInfo.ConstraintCode and OpInfo.ConstraintType. void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, - SDOperand Op, + SDValue Op, + bool hasMemory, SelectionDAG *DAG) const { assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); @@ -1817,7 +2088,7 @@ void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, OpInfo.ConstraintCode = OpInfo.Codes[0]; OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); } else { - ChooseConstraint(OpInfo, *this, Op, DAG); + ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG); } // 'X' matches anything. @@ -2053,53 +2324,53 @@ static mu magicu64(uint64_t d) /// return a DAG expression to select that will generate the same value by /// multiplying by a magic number. See: /// -SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, - std::vector* Created) const { +SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, + std::vector* Created) const { MVT VT = N->getValueType(0); // Check to see if we can do this. if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) - return SDOperand(); // BuildSDIV only operates on i32 or i64 + return SDValue(); // BuildSDIV only operates on i32 or i64 - int64_t d = cast(N->getOperand(1))->getSignExtended(); + int64_t d = cast(N->getOperand(1))->getSExtValue(); ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); // Multiply the numerator (operand 0) by the magic value - SDOperand Q; + SDValue Q; if (isOperationLegal(ISD::MULHS, VT)) Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), DAG.getConstant(magics.m, VT)); else if (isOperationLegal(ISD::SMUL_LOHI, VT)) - Q = SDOperand(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), + Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), N->getOperand(0), - DAG.getConstant(magics.m, VT)).Val, 1); + DAG.getConstant(magics.m, VT)).getNode(), 1); else - return SDOperand(); // No mulhs or equvialent + return SDValue(); // No mulhs or equvialent // If d > 0 and m < 0, add the numerator if (d > 0 && magics.m < 0) { Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); if (Created) - Created->push_back(Q.Val); + Created->push_back(Q.getNode()); } // If d < 0 and m > 0, subtract the numerator. if (d < 0 && magics.m > 0) { Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); if (Created) - Created->push_back(Q.Val); + Created->push_back(Q.getNode()); } // Shift right algebraic if shift value is nonzero if (magics.s > 0) { Q = DAG.getNode(ISD::SRA, VT, Q, DAG.getConstant(magics.s, getShiftAmountTy())); if (Created) - Created->push_back(Q.Val); + Created->push_back(Q.getNode()); } // Extract the sign bit and add it to the quotient - SDOperand T = + SDValue T = DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, getShiftAmountTy())); if (Created) - Created->push_back(T.Val); + Created->push_back(T.getNode()); return DAG.getNode(ISD::ADD, VT, Q, T); } @@ -2107,45 +2378,45 @@ SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, /// return a DAG expression to select that will generate the same value by /// multiplying by a magic number. See: /// -SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, - std::vector* Created) const { +SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, + std::vector* Created) const { MVT VT = N->getValueType(0); // Check to see if we can do this. if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) - return SDOperand(); // BuildUDIV only operates on i32 or i64 + return SDValue(); // BuildUDIV only operates on i32 or i64 - uint64_t d = cast(N->getOperand(1))->getValue(); + uint64_t d = cast(N->getOperand(1))->getZExtValue(); mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); // Multiply the numerator (operand 0) by the magic value - SDOperand Q; + SDValue Q; if (isOperationLegal(ISD::MULHU, VT)) Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), DAG.getConstant(magics.m, VT)); else if (isOperationLegal(ISD::UMUL_LOHI, VT)) - Q = SDOperand(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), + Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), N->getOperand(0), - DAG.getConstant(magics.m, VT)).Val, 1); + DAG.getConstant(magics.m, VT)).getNode(), 1); else - return SDOperand(); // No mulhu or equvialent + return SDValue(); // No mulhu or equvialent if (Created) - Created->push_back(Q.Val); + Created->push_back(Q.getNode()); if (magics.a == 0) { return DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(magics.s, getShiftAmountTy())); } else { - SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); + SDValue NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); if (Created) - Created->push_back(NPQ.Val); + Created->push_back(NPQ.getNode()); NPQ = DAG.getNode(ISD::SRL, VT, NPQ, DAG.getConstant(1, getShiftAmountTy())); if (Created) - Created->push_back(NPQ.Val); + Created->push_back(NPQ.getNode()); NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); if (Created) - Created->push_back(NPQ.Val); + Created->push_back(NPQ.getNode()); return DAG.getNode(ISD::SRL, VT, NPQ, DAG.getConstant(magics.s-1, getShiftAmountTy())); }